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Электронный компонент: X28C010DI-15C7681

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1
FN8105.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28C010
5 Volt, Byte Alterable EEPROM
The Intersil X28C010 is a 128K x 8 EEPROM, fabricated
with Intersil's proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable non-
volatile memories, the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pin out for byte-
wide memories, compatible with industry standard
EEPROMs.
The X28C010 supports a 256-byte page write operation,
effectively providing a 19s/byte write cycle and enabling the
entire memory to be typically written in less than 2.5
seconds. The X28C010 also features DATA Polling and
Toggle Bit Polling, system software support schemes used to
indicate the early completion of a write cycle. In addition, the
X28C010 supports Software Data Protection option.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Data retention is specified to
be greater than 100 years.
Features
Access time: 120ns
Simple byte and page write
- Single 5V supply
- No external high voltages or V
PP
control
circuits
- Self-timed
No erase before write
No complex programming algorithms
No overerase problem
Low power CMOS
- Active: 50mA
- Standby: 500A
Software data protection
- Protects data against system level inadvertent writes
High speed page write capability
Highly reliable Direct Write
TM
cell
- Endurance: 100,000 write cycles
- Data retention: 100 years
Early end of write detection
- DATA polling
- Toggle bit polling
Pinouts
2
32
4 3
31
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
X28C010
CERDIP
Flat Pack
SOIC (R)
PGA
X28C010
(Bottom View)
14
A0
16
I/O1
18
VSS
11
A3
9
A5
7
A7
15
I/O0
17
I/O2
19
I/O3
5
A15
2
NC
36
VCC
20
I/O4
21
I/O5
34
NC
23
I/O7
25
A10
27
A11
29
A8
22
I/O6
32
NC
24
CE
26
OE
28
A 9
30
A 13
13
A1
12
A2
10
A4
8
A6
4
A
16
3
NC
1
NC
35
WE
33
NC
31
A 14
6
A12
X28C010
(Top View)
A6
A5
A4
A3
A2
A1
A0
I/O0
A13
A8
A9
A11
A10
I/O7
A14
I/O



1

I/O



2

V

SS


I/O



3

I/O



4

I/O



5

I/O



6

A

12


A

15


A

16


NC


V
CC


WE


NC


6
1
5
8
7
9
10
11
12
13
15
17
16
18 19 20
22
23
24
25
26
27
28
29
OE
CE
A7
14
21
30
X28C010
(Top View)
A6
A5
A4
A3
A2
A1
A0
I/O 0
A13
A8
A9
A11
A10
I/O7
A14
I/
O



1

I/
O



2

V
SS


I/
O



3

I/
O



4

I/
O



5

I/
O
6

A

12


A

15


A

16


NC


V

CC


WE
NC


OE
CE
A7
30
PLCC
LCC
EXTENDED LCC
22
23
24
25
26
27
28
29
21
6
5
8
7
9
10
11
12
13
2
32
4 3
31
1
15
17
16
18 19 20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
X28C010
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
A16
A15
A12
A7
A6
A5
TSOP
14
20
A3
21
A4
Data Sheet
May 11, 2005
2
FN8105.0
May 11, 2005
Ordering Information
PART NUMBER
ACCESS
TIME
PACKAGE
TEMP
RANGE (C)
X28C010D
-
32-Ld Cerdip
0 to 70
X28C010D-12
120ns
32-Ld Cerdip
0 to 70
X28C010D-15
150ns
32-Ld Cerdip
0 to 70
X28C010DI
-
32-Ld Cerdip
-40 to +85
X28C010DI-12
120ns
32-Ld Cerdip
-40 to +85
X28C010DI-15
150ns
32-Ld Cerdip
-40 to +85
X28C010DI-
15C7681
150ns
32-Ld Cerdip
-40 to +85
X28C010DM
-
32-Ld Cerdip
-55 to +125
X28C010DM-12
120ns
32-Ld Cerdip
-55 to +125
X28C010DMB-12
120ns
32-Ld Cerdip
MIL-STD-883
X28C010DMB-
12C7309
120ns
32-Ld Cerdip
MIL-STD-883
X28C010DMB-
12C7729
120ns
32-Ld Cerdip
MIL-STD-883
X28C010DMB-15
150ns
32-Ld Cerdip
MIL-STD-883
X28C010DMB-
15C7762
150ns
32-Ld Cerdip
MIL-STD-883
X28C010DMB-20
200ns
32-Ld Cerdip
MIL-STD-883
X28C010DMC7237
-
32-Ld Cerdip
X28C010FI-12
120ns
32-Ld Flat Pack
-40 to +85
X28C010FI-15
150ns
32-Ld Flat Pack
-40 to +85
X28C010FI-
15C1009
150ns
32-Ld Flat Pack
-40 to +85
X28C010FI-20
200ns
32-Ld Flat Pack
-40 to +85
X28C010FI-25
250ns
32-Ld Flat Pack
-40 to +85
X28C010FM
-
32-Ld Flat Pack
-55 to +125
X28C010FM-12
120ns
32-Ld Flat Pack
-55 to +125
X28C010FMB-15
150ns
32-Ld Flat Pack
MIL-STD-883
X28C010FMB-
15C7619
150ns
32-Ld Flat Pack
MIL-STD-883
X28C010FMB-
15C7808
150ns
32-Ld Flat Pack
MIL-STD-883
X28C010K-25
250ns
36-Ld Pin Grid
Array
0 to 70
X28C010KM-12
120ns
36-Ld Pin Grid
Array
-55 to +125
X28C010KM-25
250ns
36-Ld Pin Grid
Array
-55 to +125
X28C010KM-
25C7237
250ns
36-Ld Pin Grid
Array
-55 to +125
X28C010KMB-15
150ns
36-Ld Pin Grid
Array
MIL-STD-883
X28C010NM-12
120ns
32-Ld Extended
LCC
-55 to +125
X28C010NM-15
150ns
32-Ld Extended
LCC
-55 to +125
X28C010NMB-12
120ns
32-Ld Extended
LCC
MIL-STD-883
X28C010NMB-15
150ns
32-Ld Extended
LCC
MIL-STD-883
X28C010NMB-
15C7309
150ns
32-Ld Extended
LCC
MIL-STD-883
X28C010RI-12
120ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI-20
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI-
20C7168
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI-
20C7975
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI-20T1
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI-
20T1C7168
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RM-15
150ns
32-Ld Ceramic
SOIC (Gull Wing)
-55 to +125
X28C010RMB-25
250ns
32-Ld Ceramic
SOIC (Gull Wing)
MIL-STD-883
Ordering Information
(Continued)
PART NUMBER
ACCESS
TIME
PACKAGE
TEMP
RANGE (C)
X28C010
3
FN8105.0
May 11, 2005
Block Diagram
Pin Descriptions
Addresses (A
0
-A
16
)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers,
and is used to initiate read operations.
Data In/Data Out (I/O
0
-I/O
7
)
Data is written to or read from the X28C010 through the I/O
pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010.
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs
last. Similarly, the data is latched internally by the rising edge
of either CE or WE, whichever occurs first. A byte write
operation, once initiated, will automatically continue to
completion, typically within 5ms.
X Buffers
Latches and
Decoder
I/O Buffers
and Latches
Y Buffers
Decoder
Control
Logic and
Timing
1Mbit
EEPROM
Array
I/O
0
-I/O
7
Data Inputs/Outputs
CE
OE
V
CC
V
SS
WE
A
0
-A
7
Latches and
A
8
-A
16
Pin Names
SYMBOL
DESCRIPTION
A
0
-A
16
Address Inputs
I/O
0
-I/O
7
Data Input/Output
WE
Write Enable
CE
Chip Enable
OE
Output Enable
V
CC
+5V
V
SS
Ground
NC
No Connect
X28C010
4
FN8105.0
May 11, 2005
Page Write Operation
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows two to
two hundred fifty-six bytes of data to be consecutively written
to the X28C010 prior to the commencement of the internal
programming cycle. The host can fetch data from another
device within the system during a page write operation
(change the source address), but the page address (A
8
through A
16
) for each subsequent valid write cycle to the part
during this operation must be the same as the initial page
address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to two hundred fifty six bytes in the
same manner as the first byte was written. Each successive
byte load cycle, started by the WE HIGH to LOW transition,
must begin within 100s of the falling edge of the preceding
WE. If a subsequent WE HIGH to LOW transition is not
detected within 100s, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively the page write window is infinitely wide,
so long as the host continues to access the device within the
byte load cycle time of 100s.
Write Operation Status Bits
The X28C010 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.
DATA Polling (I/O
7
)
The X28C010 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28C010, eliminating additional
interrupt inputs or external hardware. During the internal
programming cycle, any attempt to read the last byte written
will produce the complement of that data on I/O
7
(i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true data.
Note: If the X28C010 is in the protected state, and an illegal
write operation is attempted, DATA Polling will not operate.
Toggle Bit (I/O
6
)
The X28C010 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle, I/O
6
will toggle from HIGH to LOW and
LOW to HIGH on subsequent attempts to read the device.
When the internal cycle is complete the toggling will cease
and the device will be accessible for additional read or write
operations.
DATA Polling I/O
7
5
TB
DP
4
3
2
1
0
I/O
Reserved
Toggle Bit
DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
CE
OE
WE
I/O
7
X28C010
Last
Write
HIGH Z
V
OL
V
IH
A
0
-A
14
A
n
A
n
A
n
A
n
A
n
A
n
V
OH
A
n
Ready
FIGURE 2. DATA POLLING BUS SEQUENCE
X28C010
5
FN8105.0
May 11, 2005
DATA Polling can effectively halve the time for writing to the
X28C010. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.
The Toggle Bit I/O
6
Write Data
Save Last Data
and Address
Read Last
Address
IO
7
Compare?
No
Yes
No
Yes
Writes
Complete?
Ready
X28C010
FIGURE 3. DATA POLLING SOFTWARE FLOW
CE
OE
WE
I/O
6
X28C010
V
OH
V
OL
Last
Write
HIGH Z
* Beginning and ending state of I/O
6
will vary
*
*
Ready
FIGURE 4. TOGGLE BIT BUS SEQUENCE
X28C010