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FN8108.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28HC256
256K, 32K x 8 Bit
5 Volt, Byte Alterable EEPROM
FEATURES
Access time: 70ns
Simple byte and page write
--Single 5V supply
--No external high voltages or V
PP
control circuits
--Self-timed
--No erase before write
--No complex programming algorithms
--No overerase problem
Low power CMOS
--Active: 60mA
--Standby: 500A
Software data protection
--Protects data against system level inadvertent
writes
High speed page write capability
Highly reliable Direct Write
TM
cell
--Endurance: 1,000,000 cycles
--Data retention: 100 years
Early end of write detection
--DATA polling
--Toggle bit polling
DESCRIPTION
The X28HC256 is a second generation high perfor-
mance CMOS 32K x 8 EEPROM. It is fabricated with
Intersil's proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvola-
tile memory.
The X28HC256 supports a 128-byte page write opera-
tion, effectively providing a 24s/byte write cycle, and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a mini-
mum 1,000,000 write cycles per byte and an inherent
data retention of 100 years.
BLOCK DIAGRAM
X Buffers
Latches and
Decoder
I/O Buffers
and Latches
Y Buffers
Latches and
DECODER
Control
Logic and
Timing
256Kbit
EEPROM
Array
I/O
0
I/O
7
Data Inputs/Outputs
CE
OE
V
CC
V
SS
A
0
A
14
WE
Address
Inputs
Data Sheet
June 1, 2005
2
FN8108.0
June 1, 2005
PIN CONFIGURATION
PIN DESCRIPTIONS
Addresses (A
0
-A
14
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers, and is used to initiate read operations.
Data In/Data Out (I/O
0
-I/O
7
)
Data is written to or read from the X28HC256 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28HC256.
PIN NAMES
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
X28HC256
Plastic DIP
CERDIP
Flat Plastic
SOIC
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
4 3 2 1 32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
LCC
PLCC
A
7
I/
O
1


I/
O
2
V
SS
I/
O
3


I/
O
4

I/O
5


(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A 3
A 4
A 5
A 6
A 7
A 12
A 14
NC
VCC
NC
WE
A13
A 8
A 9
A11
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A 2
A 1
A 0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A
12
A
14
NC
V
CC
WE
A
13
NC
X28HC256
X28HC256
11
I/O
0
10
A
0
14
V
SS
9
A
1
8
A
2
7
A
3
6
A
4
5
A
5
2
A
12
28
V
CC
12
I/O
1
13
I/O
2
15
I/O
3
4
A
6
3
A
7
1
16
I/O
4
20
CE
22
OE
24
A
9
17
I/O
5
27
WE
19
I/O
7
21
A
10
23
A
11
25
A
8
18
I/O
6
26
A
13
(Bottom View)
PGA
A
14
X28HC256
TSOP
Symbol
Description
A
0
-A
14
Address Inputs
I/O
0
-I/O
7
Data Input/Output
WE
Write Enable
CE
Chip Enable
OE
Output Enable
V
CC
+5V
V
SS
Ground
NC
No Connect
X28HC256
3
FN8108.0
June 1, 2005
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28HC256 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 3ms.
Page Write Operation
The page write feature of the X28HC256 allows the
entire memory to be written in typically 0.8 seconds.
Page write allows up to one hundred twenty-eight
bytes of data to be consecutively written to the
X28HC256, prior to the commencement of the internal
programming cycle. The host can fetch data from
another device within the system during a page write
operation (change the source address), but the page
address (A
7
through A
14
) for each subsequent valid
write cycle to the part during this operation must be the
same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to one hundred
twenty-seven bytes in the same manner as the first
byte was written. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin
within 100s of the falling edge of the preceding WE. If
a subsequent WE HIGH to LOW transition is not
detected within 100s, the internal automatic program-
ming cycle will commence. There is no page write win-
dow limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100s.
Write Operation Status Bits
The X28HC256 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
DATA Polling (I/O
7
)
The X28HC256 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28HC256. This eliminates additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O
7
(i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the pro-
gramming cycle is complete, I/O
7
will reflect true data.
Toggle Bit (I/O
6
)
The X28HC256 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease, and the device will be
accessible for additional read and write operations.
5
TB
DP
4
3
2
1
0
I/O
Reserved
Toggle Bit
DATA Polling
X28HC256
4
FN8108.0
June 1, 2005
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
Figure 3. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing
to the X28HC256. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The soft-
ware flow diagram in Figure 3 illustrates one method
of implementing the routine.
CE
OE
WE
I/O
7
X28HC256
Ready
Last
Write
HIGH Z
V
OL
V
IH
A
0
A
14
An
An
An
An
An
An
V
OH
An
Write Data
Save Last Data
and Address
Read Last
Address
IO
7
Compare?
X28HC256
No
Yes
Writes
Complete?
No
Yes
Ready
X28HC256
5
FN8108.0
June 1, 2005
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an
array comprised of multiple X28HC256 memories that
is frequently updated. The timing diagram in Figure 4
illustrates the sequence of events on the bus. The
software flow diagram in Figure 5 illustrates a method
for polling the Toggle Bit.
HARDWARE DATA PROTECTION
The X28HC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.
Default V
CC
Sense--All write functions are inhibited
when V
CC
is 3.5V typically.
Write Inhibit--Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28HC256 offers a software-controlled data pro-
tection feature. The X28HC256 is shipped from Intersil
with the software data protection NOT ENABLED; that
is, the device will be in the standard operating mode.
In this mode data should be protected during power-
up/down operations through the use of external cir-
cuits. The host would then have open read and write
access of the device once V
CC
was stable.
The X28HC256 can be automatically protected during
power-up and power-down (without the need for exter-
nal circuits) by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation, utilizing the soft-
ware algorithm. This circuit is nonvolatile, and will
remain set for the life of the device unless the reset
command is issued.
Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in
the powered-up state. That is, the software algorithm must
be issued prior to writing additional data to the device.
CE
OE
WE
X28C512/513
Last
Write
I/O
6
HIGH Z
*
*
V
OH
V
OL
Ready
* I/O
6
Beginning and ending state of I/O
6
will vary.
Compare
X28C256
No
Yes
ok?
Compare
Accum with
Addr n
Load Accum
From Addr n
Last Write
Ready
Yes
X28HC256