F5210SL.p65
IRF5210S/L
HEXFET
Power MOSFET
PD - 91405C
l
Advanced Process Technology
l
Surface Mount (IRF5210S)
l
Low-profile through-hole (IRF5210L)
l
175C Operating Temperature
l
Fast Switching
l
P-Channel
l
Fully Avalanche Rated
5/13/98
S
D
G
Absolute Maximum Ratings
Fifth Generation HEXFETs from International Rectifier utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
HEXFET Power MOSFETs are well known for, provides the
designer with an extremely efficient and reliable device for
use in a wide variety of applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the highest
power capability and the lowest possible on-resistance in
any existing surface mount package. The D
2
Pak is suitable
for high current applications because of its low internal
connection resistance and can dissipate up to 2.0W in a
typical surface mount application.
The through-hole version (IRF5210L) is available for low-
profile applications.
Description
V
DSS
= -100V
R
DS(on)
= 0.06
I
D
= -40A
2
D P ak
T O -26 2
Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
0.75
R
JA
Junction-to-Ambient ( PCB Mounted,steady-state)**
40
Thermal Resistance
C/W
Parameter
Max.
Units
I
D
@ T
C
= 25C
Continuous Drain Current, V
GS
@ -10V
-40
I
D
@ T
C
= 100C
Continuous Drain Current, V
GS
@ -10V
-29
A
I
DM
Pulsed Drain Current
-140
P
D
@T
A
= 25C
Power Dissipation
3.8
W
P
D
@T
C
= 25C
Power Dissipation
200
W
Linear Derating Factor
1.3
W/C
V
GS
Gate-to-Source Voltage
20
V
E
AS
Single Pulse Avalanche Energy
780
mJ
I
AR
Avalanche Current
-21
A
E
AR
Repetitive Avalanche Energy
20
mJ
dv/dt
Peak Diode Recovery dv/dt
-5.0
V/ns
T
J
Operating Junction and
-55 to + 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
C
IRF5210S/L
Starting T
J
= 25C, L = 3.1mH
R
G
= 25
, I
AS
= -21A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Notes:
** When mounted on 1" square PCB (FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
I
SD
-21A, di/dt
-480A/s, V
DD
V
(BR)DSS
,
T
J
175C
Pulse width
300s; duty cycle
2%.
Uses IRF5210 data and test conditions
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
-100
V
V
GS
= 0V, I
D
= -250A
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
-0.11
V/C
Reference to 25C, I
D
= -1mA
R
DS(on)
Static Drain-to-Source On-Resistance
0.06
V
GS
= -10V, I
D
= -24A
V
GS(th)
Gate Threshold Voltage
-2.0
-4.0
V
V
DS
= V
GS
, I
D
= -250A
g
fs
Forward Transconductance
10
S
V
DS
= -50V, I
D
= -21A
-25
A
V
DS
= -100V, V
GS
= 0V
-250
V
DS
= -80V, V
GS
= 0V, T
J
= 150C
Gate-to-Source Forward Leakage
100
V
GS
= 20V
Gate-to-Source Reverse Leakage
-100
n A
V
GS
= -20V
Q
g
Total Gate Charge
180
I
D
= -21A
Q
gs
Gate-to-Source Charge
25
nC
V
DS
= -80V
Q
gd
Gate-to-Drain ("Miller") Charge
97
V
GS
= -10V, See Fig. 6 and 13
t
d(on)
Turn-On Delay Time
17
V
DD
= -50V
t
r
Rise Time
86
I
D
= -21A
t
d(off)
Turn-Off Delay Time
79
R
G
= 2.5
t
f
Fall Time
81
R
D
= 2.4
,
See Fig. 10
Between lead,
and center of die contact
C
iss
Input Capacitance
2700
V
GS
= 0V
C
oss
Output Capacitance
790
pF
V
DS
= -25V
C
rss
Reverse Transfer Capacitance
450
= 1.0MHz, See Fig. 5
Electrical Characteristics @ T
J
= 25C (unless otherwise specified)
I
GSS
ns
I
DSS
Drain-to-Source Leakage Current
nH
7.5
L
S
Internal Source Inductance
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
-1.6
V
T
J
= 25C, I
S
= -24A, V
GS
= 0V
t
rr
Reverse Recovery Time
170
260
ns
T
J
= 25C, I
F
= -21A
Q
rr
Reverse Recovery Charge
1.2
1.8
C
di/dt = -100A/s
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
A
S
D
G
-40
-140
IRF5210S/L
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
1 0
1 0 0
1 0 0 0
0 . 1
1
1 0
1 0 0
D
D S
A
-I
,
D
r
a
i
n
-
t
o
-S
o
u
rc
e
C
u
rre
n
t
(A
)
-V , D rain-to-S ourc e V oltage (V )
VGS
TO P - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOT TOM - 4.5V
-4.5 V
4 0 s P U LS E W ID T H
T = 2 5C
c
1
1 0
1 0 0
1 0 0 0
0.1
1
1 0
1 0 0
D
D S
A
-
I
,
Dr
ai
n
-
t
o
-
S
ou
r
c
e Cur
r
e
n
t
(
A
)
-V , D rain-to-S ource V oltage (V )
VGS
TOP - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
-4 .5V
4 0 s P U LS E W ID T H
T = 1 75 C
C
1
1 0
1 0 0
1 0 0 0
4
5
6
7
8
9
1 0
T = 2 5 C
J
G S
D
A
-
I
,
D
r
ai
n-
t
o
-
S
ourc
e
C
u
rr
ent
(
A
)
-V , Ga te -to-S ource V olta ge (V )
T = 17 5 C
V = -5 0 V
4 0 s P U L S E W ID TH
DS
J
0 . 0
0 . 5
1 . 0
1 . 5
2 . 0
2 . 5
3 . 0
- 6 0
- 4 0
- 2 0
0
2 0
4 0
6 0
8 0
1 0 0 1 2 0 1 4 0 1 6 0 1 8 0
J
T , J unc tion T em perature (C )
R
, D
r
a
i
n
-
to
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
D
S
(
on)
(N
o
r
m
a
li
z
e
d
)
A
V = -10 V
G S
I = -3 5A
D
IRF5210S/L
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
1 0 0 0
2 0 0 0
3 0 0 0
4 0 0 0
5 0 0 0
6 0 0 0
1
1 0
1 0 0
C
,
Cap
ac
i
t
a
n
c
e
(
p
F
)
A
D S
-V , D rain-to-S ourc e V oltage (V )
V = 0V , f = 1 M H z
C = C + C , C S H O R TE D
C = C
C = C + C
G S
iss g s g d d s
rs s g d
o ss ds g d
C
is s
C
os s
C
rs s
0
4
8
1 2
1 6
2 0
0
4 0
8 0
1 2 0
1 6 0
2 0 0
G
GS
A
-
V
, G
a
te
-
t
o
-
S
o
u
r
c
e
V
o
l
t
a
g
e
(
V
)
Q , Total G ate C harge (nC )
V = -80 V
V = -50 V
V = -20 V
D S
D S
D S
F O R T E S T C IR C U IT
S E E F IG U R E 1 3
I = -2 1A
D
1
1 0
1 0 0
1 0 0 0
0 . 4
0 . 8
1 . 2
1 . 6
2 . 0
2 . 4
T = 2 5C
J
V = 0V
G S
S D
SD
A
-
I
,
Rev
er
s
e
D
r
a
i
n Cur
r
e
n
t
(
A
)
-V , S ourc e-to-D rain V oltage (V )
T = 1 75 C
J
1
1 0
1 0 0
1 0 0 0
1
1 0
1 0 0
1 0 0 0
O P E R A T IO N IN T H IS A R E A L IM ITE D
B Y R
D S (o n)
1 0 m s
A
-I
,
D
r
a
i
n
C
u
rre
n
t
(A
)
-V , D ra in -to -S o urc e V o lta g e (V )
D S
D
1 0 s
1 0 0 s
1 m s
T = 25 C
T = 17 5C
S ing le P u ls e
C
J
IRF5210S/L
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
V
DS
-10V
Pulse Width
1
s
Duty Factor
0.1 %
R
D
V
GS
V
DD
R
G
D.U.T.
+
-
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
25
50
75
100
125
150
175
0
10
20
30
40
50
T , Case Temperature ( C)
-I , Drain Current (A)
C
D
0.01
0.1
1
0.00001
0.0001
0.001
0.01
0.1
1
Notes:
1. Duty factor D =
t / t
2. Peak T = P
x Z
+ T
1
2
J
DM
thJC
C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response
(Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
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