ISD 2727 North First Street, San Jose, CA 95134 TEL: 408/943-6666 FAX: 408/544-1787 http://www.isd.com
August 2000
Figure: ISD5008 Block Diagram
AUX IN
AMP
1.0/1.414/2.0/2.828
AGC
SUM1 MUX
Vol
MUX
Filter
MUX
SUM1
FTHRU
INP
ANA OUT MUX
VOL
SUM2
ANA IN
SUM2
SP+
SP-
SPEAKER
AUX OUT
ANA OUT-
ANA OUT+
MIC+
MIC -
AGCCAP
MICROPHONE
AUX IN
XCLK
ANA IN
V
SSA
V
CCA
Input Source MUX
FILTO
SUM1
INP
ANA IN
SUM2
FILTO
VOL
SUM1
Summing
AMP
ANA IN
AMP
0.625/0.883/1.25/1.76
6dB
SUM2
Summing
AMP
Output MUX
Volume
Control
MIC IN
AUX IN
FILTO
ANA IN
SUM1
ANA IN
FILTO
ARRAY
INP
SUM1 MUX
ARRAY
Spkr.
AMP
AUX
OUT
AMP
V
SSA
V
SSD
V
SSD
V
CCD
V
CCD
Device Control
ANA
OUT
AMP
2
( )
VLS0
VLS1
2
( )
AIG0
AIG1
2
( )
AXG0
AXG1
2
( )
S1S0
S1S1
2
( )
S1M0
S1M1
2
( )
S2M0
S2M1
( )
OPA0
OPA1
2
( )
OPS0
OPS1
2
Internal
Clock
Multilevel
Storage Array
( )
FLD0
FLD1
2
(INS0)
1
1
(AXPD)
1
(AGPD)
1
(FLPD)
1
(FLS0)
1
(AIPD)
1
(AOPD)
( )
3
AOS0
AOS1
AOS2
3
( )
VOL0
VOL1
VOL2
CAR KIT
CHIP SET
CAR KIT
CHIP SET
Low Pass
Filter
V
SSA
Power Conditioning
MISO
MOSI
SS
SCLK
RAC
INT
1
(VLPD)
AUX IN
AMP
1.0/1.414/2.0/2.828
AGC
SUM1 MUX
Vol
MUX
Filter
MUX
SUM1
FTHRU
INP
ANA OUT MUX
VOL
SUM2
ANA IN
SUM2
SP+
SP-
SPEAKER
AUX OUT
ANA OUT-
ANA OUT+
MIC+
MIC -
AGCCAP
MICROPHONE
AUX IN
XCLK
ANA IN
V
SSA
V
CCA
Input Source MUX
FILTO
SUM1
INP
ANA IN
SUM2
FILTO
VOL
SUM1
Summing
AMP
ANA IN
AMP
0.625/0.883/1.25/1.76
6dB
SUM2
Summing
AMP
Output MUX
Volume
Control
MIC IN
AUX IN
FILTO
ANA IN
SUM1
ANA IN
FILTO
ARRAY
INP
SUM1 MUX
ARRAY
Spkr.
AMP
AUX
OUT
AMP
V
SSA
V
SSD
V
SSD
V
CCD
V
CCD
Device Control
ANA
OUT
AMP
2
( )
VLS0
VLS1
( )
VLS0
VLS1
2
( )
AIG0
AIG1
2
( )
AXG0
AXG1
2
( )
S1S0
S1S1
2
( )
S1M0
S1M1
2
( )
S2M0
S2M1
( )
S2M0
S2M1
( )
OPA0
OPA1
2
( )
OPS0
OPS1
2
Internal
Clock
Multilevel
Storage Array
( )
FLD0
FLD1
( )
FLD0
FLD1
2
2
(INS0)
1
1
(AXPD)
1
(AGPD)
1
(FLPD)
1
(FLPD)
1
(FLS0)
1
(AIPD)
1
(AOPD)
( )
3
AOS0
AOS1
AOS2
3
3
( )
VOL0
VOL1
VOL2
( )
VOL0
VOL1
VOL2
CAR KIT
CHIP SET
CAR KIT
CHIP SET
Low Pass
Filter
V
SSA
Power Conditioning
MISO
MOSI
SS
SCLK
RAC
INT
1
(VLPD)
ISD5008 PRODUCT SUMMARY
The ISD5008 ChipCorder product is a fully-inte-
grated, single-chip solution which provides seam-
less integration of enhanced voice record and
playback features for digital cellular phones (GSM,
CDMA, TDMA, PDC, and PHS), automotive com-
munications, GPS/navigation systems, and porta-
ble communication products. This low-power, 3-
volt product enables customers to quickly and
easily integrate 4 to 8 minutes of voice storage
features such as one-way and two-way (full du-
plex) call record, voice memo record, and call
screening/answering machine functionality.
Like other ChipCorder products, the ISD5008 inte-
grates the sampling clock, anti-aliasing and
smoothing filters, and the multi-level storage array
on a single-chip. For enhanced voice features,
the ISD5008 eliminates external circuitry by also in-
tegrating automatic gain control (AGC), a power
amplifier/speaker driver, volume control, sum-
ming amplifiers, analog switches, and a car kit in-
terface. Input level adjustable amplifiers are also
included, providing a flexible interface for multiple
applications.
ISD5008
Single-Chip Voice Record/Playback Device
4-, 5-, 6-, and 8-Minute Durations
Preliminary Datasheet
ISD5008 Product
ii
Voice Solutions in Silicon
TM
Duration/sample rate selection is accomplished
via software, allowing customers to optimize qual-
ity and duration for various features within the
same end product.
The ISD5008 device is designed for use in a micro-
processor- or microcontroller-based system. Ad-
dress, control, and duration selection are
accomplished through a Serial Peripheral Inter-
face (SPI) or Microwire Serial Interface to minimize
pin count.
Recordings are stored in on-chip nonvolatile
memory cells, providing zero-power message
storage. This unique, single-chip solution is made
possible through ISD's patented multilevel storage
technology. Voice and audio signals are stored
directly into solid-state memory in their natural, un-
compressed form, providing superior quality voice
and music reproduction.
ISD5008 FEATURES
FULLY-INTEGRATED SOLUTION
Single-chip voice record/playback solution
Integrated sampling clock, anti-aliasing and
smoothing filters, and multi-level storage array
Integrated analog features such as automatic
gain control (AGC), audio gating switches,
speaker driver (23mW with 8 ohm load),
summing amplifiers, volume control, and an
AUX IN/AUX OUT interface (e.g., for car kits).
LOW-POWER CONSUMPTION
Single +3 volt supply
Operating current:
I
CC Play
= 15 mA (typical)
I
CC Rec
= 25 mA (typical)
I
CC Feedthru
= 12 mA (typical)
Standby current:
I
SB
= 1 A
Power consumption controlled by SPI or
Microwire control register
Most stages can be individually powered
down for minimum power consumption
ENHANCED VOICE FEATURES
One or two-way (full duplex) conversation
record (record signal summation)
One- or two-way (full duplex) message
playback (while on a call)
Voice memo record and playback
Private call screening
In-terminal answering machine
Personalized outgoing message (given caller
ID information from host chip set)
Private call announce while on call (given
CIDCW information from host chip set)
EASY-TO-USE AND CONTROL
No compression algorithm development
required
User-controllable sample rates of 8.0 kHz,
6.4 kHz, 5.3 kHz, or 4.0 kHz providing up to
8 minutes of voice storage.
Microcontroller SPI or MicrowireTM Serial
Interface
Fully addressable to handle multiple
messages in 1200 rows
HIGH QUALITY SOLUTION
High quality voice and music reproduction
ISD's standard 100-year message retention
(typical)
100,000 record cycles (typical)
OPTIONS
Available in die form, PDIP, SOIC, TSOP, and
chip scale packaging (CSP)
Compact BGA chip scale package
available for portable applications
Extended temperature (-20 to +70C) and
industrial temperature (-40 to +85C) versions
available
Table of Contents
1 DETAILED
DESCRIPTION
................................................. .................... 1
1.1 Speech/Sound
Quality
...................................... .................... 1
1.2 Duration
............................................................ .................... 1
1.3 Flash
Storage
.................................................... .................... 1
1.4 Microcontroller
Interface
....................................................... 1
1.5 Programming
.................................................... .................... 1
2 PIN
DESCRIPTIONS
........................................................ .................... 2
2.1
Digital I/O Pins ................................................... .................... 2
2.2
Analog I/O Pins .................................................. .................... 3
2.3
Power and Ground Pins .................................... .................... 6
3
INTERNAL FUNCTIONAL BLOCKS .................................... .................... 7
4
SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION .......... .................... 13
4.1 Message
Cueing
.............................................. .................... 13
4.2 Power-Up
Sequence
......................................... .................... 14
4.3 SPI
Port
.............................................................. .................... 15
4.4
SPI Control Register ........................................... .................... 15
5
OPERATIONAL MODES DESCRIPTION ............................. .................... 21
5.1
Feed Through Mode ......................................... .................... 21
5.2 Call
Record
...................................................... .................... 23
5.3 Memo
Record
.................................................. .................... 24
5.4
Memo and Call Record Playback .................... .................... 24
6 TIMING
DIAGRAMS
....................................................... .................... 34
7
DEVICE PHYSICAL DIMENSIONS ..................................... .................... 36
8
ORDERING INFORMATION ........................................... .................... 42
ISD5008 Product
1
ISD
1
DETAILED DESCRIPTION
1.1
SPEECH/SOUND QUALITY
The ISD5008 ChipCorder product can be config-
ured via software to operate at 4.0, 5.3, 6.4, and
8.0 kHz sampling frequencies, allowing the user a
choice of speech quality options. Increasing the
duration decreases the sampling frequency and
bandwidth, which affects sound quality. Table 1
compares filter pass band and product durations.
The speech samples are stored directly into on-chip
nonvolatile memory without the digitization and
compression associated with other solutions. Di-
rect analog storage provides a natural sounding
reproduction of voice, music, tones, and sound
effects not available with most solid-state solu-
tions.
1.2
DURATION
To meet end system requirements, the ISD5008
device is a single-chip solution which provides
from 4 to 8 minutes of voice record and playback,
depending on the sample rates defined by cus-
tomer software.
1.3
FLASH STORAGE
One of the benefits of ISD's ChipCorder technology
is the use of on-chip nonvolatile memory, which pro-
vides zero-power message storage. The message
is retained for up to 100 years (typically) without
power. In addition, the device can be re-record-
ed over 100,000 times (typically).
1.4
MICROCONTROLLER INTERFACE
A four-wire (SCLK, MOSI, MISO, SS) SPI interface is
provided for ISD5008 control, addressing func-
tions, and sample rate selection. The ISD5008 is
configured to operate as a peripheral slave de-
vice with a microcontroller-based SPI bus inter-
face. Read/Write access to all the internal registers
occurs through this SPI interface. An interrupt sig-
nal (INT) and internal read-only Status Register are
provided for handshake purposes.
1.5
PROGRAMMING
The ISD5008 series is also ideal for playback-only
applications, where single or multiple message
Playback is controlled through the SPI port. Once
the desired message configuration is created, du-
plicates can easily be generated via an ISD or
third-party programmers. For more information on
available application tools and programmers
please see the ISD web site at www.isd.com.
Table 1:
Input Sample Rate to Duration
Input Sample
Rate (kHz)
Duration
(Minutes)
Typical Filter Pass Band
(kHz)
8.0
4.0
3.4
6.4
5.0
2.7
5.3
6.0
2.3
4.0
8.0
1.7
ISD5008 Product
2
Voice Solutions in Silicon
TM
2
PIN DESCRIPTIONS
2.1
DIGITAL I/O PINS
SCLK
(Serial Clock)
The SCLK is the clock input to the ISD5008. Gener-
ated by the master microcontroller, the SCLK syn-
chronizes data transfers in and out of the device
through the MISO and MOSI lines. Data is latched
into the ISD5008 on the rising edge of SCLK and
shifted out on the falling edge.
SS
(Slave Select)
This input, when LOW, will select the ISD5008 de-
vice.
MOSI
(Master Out Slave In)
MOSI is the serial data input to the ISD5008 de-
vice. The master microcontroller places data to
be clocked into the ISD5008 device on the MOSI
line one-half cycle before the rising edge of SCLK.
Data is clocked into the device LSB (Least Signifi-
cant Bit) first.
MISO
(Master In Slave Out)
MISO is the serial data output of the ISD5008 de-
vice. Data is clocked out on the falling edge of
SCLK. This output goes into a high-impedance
state when the device is not selected. Data is
clocked out of the device LSB first.
INT
(Interrupt)
INT is an open drain output pin. The ISD5008 inter-
rupt pin goes LOW and stays LOW when an Over-
flow (OVF) or End of Message (EOM) marker is
detected. Each operation that ends in an EOM or
OVF generates an interrupt, including the mes-
sage cueing cycles. The interrupt is cleared the
next time an SPI cycle is completed. The interrupt
status can be read by a RINT instruction that will
give one of the two flags out the MISO line.
OVF Flag
. The overflow flag indicates that the end
of the ISD5008's analog memory has been
reached during a record or playback operation.
EOM Flag.
The end of message flag is set only
during playback, when an EOM is found. There are
eight possible EOM markers per row.
RAC
(Row Address Clock)
RAC is an open drain output pin that marks the
end of a row. At the 8 kHz sample frequency, the
duration of this period is 200 ms. There are 1,200
rows of memory in the ISD5008 devices. RAC stays
HIGH for 175 ms and stays LOW for the remaining
25 ms before it reaches the end of the row.
The RAC pin remains HIGH for 109.38 sec and
stays LOW for 15.63 sec under the Message Cue-
ing mode. See Table 15 Timing Parameters for
RAC timing information at other sample rates.
When a record command is first initiated, the RAC
pin remains HIGH for an extra T
RACLO
period, to
load sample and hold circuits internal to the de-
vice. The RAC pin can be used for message man-
agement techniques.
XCLK
(External Clock Input)
The external clock input for the ISD5008 product
has an internal pull-down device. Normally, the
ISD5008 is operated at one of four internal rates
selected for its internal oscillator by the Sample
Rate Select bits. If greater precision is required, the
device can be clocked through the XCLK pin as
described in Table 2.
Because the antialiasing and smoothing filters
track the Sample Rate Select bits, one must, for
optimum performance, change the external
clock
AND the Sample Rate Configuration bits to
one of the four values to properly set the filters to
the correct cutoff frequency as described in Table
3. The duty cycle on the input clock is not critical,
as the clock is immediately divided by two inter-
nally. If the XCLK is not used, this input should be
connected to V
SSD
.
ISD5008 Product
3
ISD
Table 3:
Internal Clock Rate/Filter Edge
2.2
ANALOG I/O PINS
MIC+, MIC
(Microphone Input+/)
The microphone input transfers the voice signal to
the on-chip AGC preamplifier or directly to the
ANA OUT MUX, depending on the selected path.
The direct path to the ANA OUT MUX has a gain of
6 dB so a 208 mVp-p signal across the differential
microphone inputs would give 416 mVp-p across
the ANA OUT pins. The AGC circuit has a range of
45 dB in order to deliver a nominal 694 mVp-p into
the storage array from a typical electret micro-
phone output of 2 to 20 mVp-p. The input imped-
ance is typically 10 k
.
Figure 1: Microphone Input
Table 2:
External Clock Input Table
Duration
(Minutes)
Sample Rate
(kHz)
Required Clock
(kHz)
4
8.0
1024
5
6.4
819.2
6
5.3
682.7
8
4.0
512
FLD1
FLD0
Sample Rate
(kHz)
Filter Pass Band
(kHz)
0
0
8
3.4
0
1
6.4
2.7
1
0
5.3
2.3
1
1
4
1.7
R
a
= 10 k
10 k
C
COUP
= 0.1 F
0.1 F
Internal to the device
Electret
Microphone
WM-54B
Panasonic
1.5 k
1.5 k
1.5 k
220 F
VCC
MIC+
MIC
NOTE:
f
CUTOFF
=
1
2 R
a
C
COUP
ISD5008 Product
4
Voice Solutions in Silicon
TM
ANA IN
(Analog Input)
The ANA IN pin is the analog input from the tele-
phone chip set. It can be switched (by the SPI bus)
to the speaker output, the array input or to various
other paths. This pin is designed to accept a nom-
inal 1.11 Vp-p when at its minimum gain (6 dB)
setting. There is additional gain available in 3 dB
steps controlled from the SPI bus, if required, up to
15 dB.
Figure 2: ANA IN Input Modes
1. Gain from ANA IN to SP+/
2. Gain from ANA IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping.
4. Speaker Out gain set to 1.6 (High). (Differential)
Gain
Setting
Resistor Ratio
(Rb/Ra)
Gain
Gain
2
(dB)
00
63.9/102
0.625
4.1
01
77.9/88.1
0.88
1.1
10
92.3/73.8
1.25
1.9
11
106/60
1.77
4.9
Table 4: ANA IN Amplifier Gain Settings
Setting
(1)
0TLP Input
V
PP
(3)
CFG0
Gain
(2)
Array In/Out
V
PP
Speaker Out
V
PP
(4)
AIG1
AIG0
6 dB
1.11
0
0
.625
.694
2.22
9 dB
.785
0
1
.883
.694
2.22
12 dB
.555
1
0
1.250
.694
2.22
15 dB
.393
1
1
1.767
.694
2.22
ISD5008 Product
5
ISD
AUX IN
(Auxiliary Input)
The AUX IN is an additional audio input to the
ISD5008, such as from the microphone circuit in a
mobile phone "car kit." This input has a nominal
700 mVp-p level at its minimum gain setting
(0 dB). See Table 5. Additional gain is available in
3 dB steps (controlled by the SPI bus) up to 9 dB.
Figure 3: AUX IN Input Modes
1. Gain from AUX IN to ANA OUT
2. Gain from AUX IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping.
4. Differential
Gain
Setting
Resistor Ratio
(Rb/Ra)
Gain
Gain
(dB)
00
40.1/40.1
1.0
0
01
47.0/33.2
1.414
3
10
53.5/26.7
2.0
6
11
59.2/21
2.82
9
Table 5: AUXIN Amplifier Gain Settings
Setting
(1)
0TLP Input
V
PP
(3)
CFG0
Gain
(2)
Array In/Out
V
PP
Ana Out V
PP
(4)
AXG1
AXG0
0 dB
.694
0
0
1.00
.694
.694
3 dB
.491
0
1
1.41
.694
.694
6 dB
.347
1
0
2.00
.694
.694
9 dB
.245
1
1
2.82
.694
.694
ISD5008 Product
6
Voice Solutions in Silicon
TM
ANAOUT+/
(Analog Outputs)
This differential output is designed to go to the mi-
crophone input of the telephone chip set. It is de-
signed to drive a minimum of 5 k
between the
"+" and "" pins to a nominal voltage level of
700 mVp-p. Both pins have DC bias of approxi-
mately 1.2 VDC. The AC signal is superimposed
upon this analog ground voltage. These pins can
be used single-ended, getting only half the volt-
age. Do NOT ground the unused pin.
AUX OUT
(Auxiliary Output)
The AUXOUT is an additional audio output pin, to
be used, for example, to drive the speaker circuit
in a "car kit." It drives a minimum load of 5 k
and
up to a maximum of 1 Vp-p. The AC signal is su-
perimposed on approximately 1.2 VDC bias and
must be capacitively coupled to the load.
SP+, SP
(Speaker+/)
This is the speaker differential output circuit. It is de-
signed to drive an 8
speaker connected across
the speaker pins up to a maximum of 23.5 mW
power. This stage has two selectable gains, 1.32
and 1.6, which can be chosen through the con-
figuration registers. These pins are biased to ap-
proximately 1.2 VDC and, if used single-ended,
must be capacitively coupled to their load. Do
NOT ground the unused pin.
ACAP
(AGC Capacitor)
This pin provides the capacitor connection for
setting the parameters of the microphone AGC
circuit. It should have a 4.7 F capacitor con-
nected to ground. It cannot be left floating. This is
because the capacitor is also used in the
playback mode for the AutoMute circuit. This
circuit reduces the amount of noise present in the
output during quiet pauses. Tying this pin to
ground gives maximum gain; to V
CCA
gives
minimum gain for the AGC amplifier but will
cancel the AutoMute function.
2.3
POWER AND GROUND PINS
V
CCA
, V
CCD
(Voltage Inputs)
To minimize noise, the analog and digital circuits
in the ISD5008 device uses separate power bus-
ses. These +3 V busses lead to separate pins. Tie
the V
CCD
pins together as close as possible and
decouple both supplies as near to the package
as possible.
V
SSA
, V
SSD
(Ground Inputs)
The ISD5008 series utilizes separate analog and
digital ground busses. The analog ground (V
SSA
)
pins should be tied together as close to the pack-
age as possible and connected through a low-
impedance path to power supply ground. The
digital ground (V
SSD
) pin should be connected
through a separate low-impedance path to pow-
er supply ground. These ground paths should be
large enough to ensure that the impedance be-
tween the V
SSA
pins and the V
SSD
pin is less than
3
. The backside of the die is connected to V
SSD
through the substrate resistance. In a chip-on-
board design, the die attach area must be con-
nected to V
SSD
.
ISD5008 Product
7
ISD
Figure 4: ISD5008 Series TSOP and PDIP/SOIC Pinouts
3
INTERNAL FUNCTIONAL BLOCKS
Figure 5: Microphone Amplifier
28-PIN TSOP
ISD5008
PDIP/SOIC
ISD5008
Microphone
(300 mVp-p Max)
MIC+
MIC
ACAP
FTHRU
AGC
1 (AGPD)
6 dB
To AutoMute
(Playback Only)
*
* Differential Path
AGPD
0
Power Up
1
Power Down
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
CFG1
AGC
ISD5008 Product
8
Voice Solutions in Silicon
TM
Figure 6: AUX IN and ANA IN
Car Kit
AUX IN
AUX IN AMP
AUX IN
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AIG1
AIG0
AIPD
AXG1
AXG0
AXPD
INS0
AOS2
AOS1
AOS0
AOPD
OPS1
OPS0
OPA1
OPA0
VLPD
CFG0
AMP
1.
0 / 1.
414
/ 2.
0 / 2.
828
1 (AXPD)
AXPD
0
Power Up
1
Power Down
2 (AXG1, AXG0)
AXG1
AXG0
Input Gain
0TLP Input Level
0
0
1
.694
0
1
1.414
.491
1
0
2
.347
1
1
2.828
.245
Chip Set
ANA IN
ANA IN AMP
ANA IN
AMP
.
6
2
5
/
.
883 / 1.
25 / 1.
767
1 (AIPD)
AIPD
0
Power Up
1
Power Down
2 (AIG1,AIG0)
AIG1
AIG0
Input Gain
0TLP Input Level
0
0
0.625
1.11
0
1
0.883
.785
1
0
1.250
.555
1
1
1.767
.393
ISD5008 Product
9
ISD
Figure 7: ISD5008 Core (Left Half)
INPUT
AGC AMP
SUM1
2 (S1M1,S1M0)
S1M1
S1M0
SOURCE
0
0
BOTH
0
1
SUM1 MUX ONLY
1
0
INP ONLY
1
1
Power Down
SOURCE
MUX
SUM1 SUMMING
AMP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AIG1
AIG0
AIPD
AXG1
AXG0
AXPD
INS0
AOS2
AOS1
AOS0
AOPD
OPS1
OPS0
OPA1
OPA0
VLPD
CFG0
AUX IN AMP
FILTO
SUM1
MUX
ANA IN AMP
ARRAY
2 (S1S1,S1S0)
S1S1
S1S0
SOURCE
0
0
ANA IN AMP
0
1
ARRAY
1
0
FILTO
1
1
N/C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
CFG1
INSO
Source
0
AGC AMP
1
AUX IN AMP
(INS0)
ISD5008 Product
10
Voice Solutions in Silicon
TM
Figure 8: ISD5008 Core (Right Half)
SUM1
SUM2
2 (S2M1,S2M0)
S2M1
S2M0
SOURCE
0
0
BOTH
0
1
ANA IN ONLY
1
0
FILTO ONLY
1
1
Power Down
FILTER
MUX
SUM2 SUMMING
AMP
ARRAY
2
FLD1
FLD0
SAMPLE RATE
FILTER PASS BAND
0
0
8 kHz
3.4 kHz
0
1
6.4 kHz
2.7 kHz
1
0
5.3 kHz
2.3 kHz
1
1
4 kHz
1.7 kHz
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
CFG1
FILTO
LOW PASS
FILTER
INTERNAL
CLOCK
MULTILEVEL
STORAGE
ARRAY
FLS0
Source
0
SUM1
1
ARRAY
1
(FLS0)
1
(FLPD)
FLPD
0
Power Up
1
Power Down
ARRAY
ANA IN AMP
XCLK
(FLD1,FLD0)
ISD5008 Product
11
ISD
Figure 9: Volume Control
INS0
VOL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AIG1
AIG0
AIPD
AXG1
AXG0
AXPD
AOS2
AOS1
AOS0
AOPD
OPS1
OPS0
OPA1
OPA0
VLPD
CFG0
SUM2
VOL
MUX
SUM1
INP
2
VLS1
VLS0
SOURCE
0
0
ANA IN AMP
0
1
SUM2
1
0
SUM1
1
1
INP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
CFG1
ANA IN AMP
VOLUME
CONTROL
(VLS1,VLS0)
3
VOL2
VOL1
VOL0
Attenuation
0
0
0
0 dB
0
0
1
4 dB
0
1
0
8 dB
0
1
1
12 dB
1
0
0
16 dB
1
0
1
20 dB
1
1
0
24 dB
1
1
1
28 dB
(VOL2,VOL1,VOL0)
1 (VLPD)
VLPD
0
Power Up
1
Power Down
VOL0
ISD5008 Product
12
Voice Solutions in Silicon
TM
Figure 10: Speaker and AUX OUT
Figure 11: ANA OUT Output
Speaker
SP+
SP
AUX OUT
Car Kit
(1 Vp-p Max)
ANA IN AMP
OUTPUT
MUX
FILTO
SUM2
2
OPS1
OPS0
SOURCE
0
0
VOL
0
1
ANA IN
1
0
FILTO
1
1
SUM2
VOL
(OPS1,OPS0)
2
OPA1
OPA0
SPKR Drive
AUX OP
0
0
Power Down
Power Down
0
1
3.6 Vp-p @ 150
Power Down
1
0
23 mWatt @ 8
Power Down
1
1
Power Down
1 Vp-p Max @ 5k
(OPA1, OPA0)
INS0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AIG1
AIG0
AIPD
AXG1
AXG0
AXPD
AOS2
AOS1
AOS0
AOPD
OPS1
OPS0
OPA1
OPA0
VLPD
CFG0
Chip Set
ANA OUT+
ANA OUT
*VOL
ANA OUT
MUX
*FILTO
*SUM2
3 (AOS2,AOS1,AOS0)
AOS2
AOS1
AOS0
0
0
0
FTHRU
0
0
1
INP
0
1
0
VOL
0
1
1
FILTO
1
0
0
SUM1
1
0
1
SUM2
1
1
0
N/C
1
1
1
N/C
*FTHRU
1
AOPD
0
Power Up
1
Power Down
(AOPD)
INS0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AIG1
AIG0
AIPD
AXG1
AXG0
AXPD
AOS2
AOS1
AOS0
AOPD
OPS1
OPS0
OPA1
OPA0
VLPD
CFG0
*INP
*SUM1
(1 Vp-p max. from AUX IN or ARRAY)
(600 mVp-p max. from microphone input)
*DIFFERENTIAL PATH
ISD5008 Product
13
ISD
4
SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION
The ISD5008 product operates from an SPI serial in-
terface. The SPI interface operates with the following
protocol.
The data transfer protocol assumes that the mi-
crocontroller's SPI shift registers are clocked on the
falling edge of the SCLK. With the ISD5008, data is
clocked in on the MOSI pin on the rising clock
edge. Data is clocked out on the MISO pin on the
falling clock edge.
1.
All serial data transfers begin with the falling
edge of SS pin.
2.
SS is held LOW during all serial communica-
tions and held HIGH between instructions.
3.
Data is clocked in on the rising clock edge
and data is clocked out on the falling clock
edge.
4.
Play and Record operations are initiated by
enabling the device by asserting the SS pin
LOW, shifting in an opcode and an address
field to the ISD5008 device (refer to the Op-
code Summary on the page 14).
5.
The opcodes and address fields are as fol-
lows: <8 control bits> and <16 address
bits>.
6.
Each operation that ends in an EOM or
Overflow will generate an interrupt, includ-
ing the Message Cueing cycles. The Inter-
rupt will be cleared the next time an SPI
cycle is completed.
7.
As Interrupt data is shifted out of the
ISD5008 MISO pin, control and address
data is simultaneously being shifted into
the MOSI pin. Care should be taken such
that the data shifted in is compatible with
current system operation. It is possible to
read interrupt data and start a new opera-
tion within the same SPI cycle.
8.
A record or playback operation begins with
the RUN bit set and the operation ends with
the RUN bit reset.
9.
All operations begin with the rising edge
of SS.
4.1
MESSAGE CUEING
Message cueing allows the user to skip through
messages, without knowing the actual physical lo-
cation of the message. This operation is used dur-
ing playback. In this mode, the messages are
skipped 1600 times faster than in normal play-
back mode. It will stop when an EOM marker is
reached. Then, the internal address counter will
point to the next message.
ISD5008 Product
14
Voice Solutions in Silicon
TM
1. X = Don't Care.
2. Changes in CFG0 are not recognized until CFG1 is loaded. The changes will occur at the rising edge of SS during
the cycle that CFG1 is loaded.
4.2
POWER-UP SEQUENCE
The ISD5008 will be ready for an operation after
T
PUD
(25 ms approximately for 8 kHz sample rate).
The user needs to wait T
PUD
before issuing an opera-
tional command. For example, to play from ad-
dress 00 the following programing cycle should
be used.
Playback Mode
1.
Send POWERUP command.
2.
Wait T
PUD
(power-up delay).
3.
Load CFG0 and CFG1 for desired opera-
tion.
4.
Send SETPLAY command with address 00.
The device will start playback at address 00 and it
will generate an interrupt when an EOM is
reached. It will then stop playback.
Record Mode
1.
Send POWERUP command.
2.
Wait T
PUD
(power-up delay).
3.
Load CFG0 and CFG1 for desired opera-
tion.
4.
Send SETREC command with address 00.
The device will start recording at address 00 and it
will generate an interrupt when an overflow is
reached (end of memory array) or when it has re-
ceived a STOP command. It will then stop record-
ing.
Table 6: Opcode Summary
Instruction
Opcode <8 bits>
(1)
Address <16 bits>
Operational Summary
POWERUP
0110 0000
Power-Up: See "Power-Up Sequence"
LOADCFG0
(2)
01X0 0010 <D15D0>
Loads a 16-bit value into Configuration Register 0
LOADCFG1
01X0 0100 <D15D0>
Loads a 16-bit value into Configuration Register 1
SETPLAY
1110 0000 <A15A0>
Initiates Playback from address <A15A0>
PLAY
1111 0000
Playback from current address (until EOM or OVF)
SETREC
1010 0000 <A15A0>
Initiates Record at address <A15A0>
REC
1011 0000
Records from current address until OVF is reached
MC
1111 1000
Performs a Message Cue. Proceeds to the end of the current
message (EOM) or enters OVF condition if it reaches the end of
the array.
STOP
0111 0000
Stops current operation
STOPWRDN
0101 0000
Stops current operation and enters stand-by (power-down) mode.
RINT
0111 0000
Read interrupt status bits: OVF and EOM.
15
ISD5008 Product
ISD
4.3
SPI PORT
The following diagram describes the SPI port and the control bits associated with it.
Figure 12: SPI Port
NOTE:
Bytes 1 and 2 of the MOSI input may be address bits or configuration bits, depending on the selected mode
in byte 3.
4.4
SPI CONTROL REGISTER
The SPI control register provides control of individual device functions such as Play, Record, Message
Cueing, Power-Up and Power-Down, Start and Stop operations, Ignore Address Pointers and Load Con-
figuration Registers.
Table 7: SPI Control Register
Control
Register
Bit
Device Function
Control
Register
Bit
Device Function
RUN
Enable or Disable an operation
PU
Master power control
=
=
1
0
Start
Stop
=
=
1
0
Power-Up
Power-Down
P/R
Selects Play or Record operation
IAB
Ignore address control bit
=
=
1
0
Play
Record
=
=
1
0
Ignore input address register (A15A0)
Use the input address register contents
for an operation (A15A0)
MC
Enable or Disable Message Cueing
A15A0
Output of the row pointer register
=
=
1
0
Enable Message Cueing
Disable Message Cueing
D15D0
Input control and address register
LC0
LC1
=
=
1
0
Load Configuration Reg 0
No Load
=
=
1
0
Load Configuration Reg 1
No Load
16
ISD5008 Product
Voice Solutions in SiliconTM
NOTE:
See details on following pages.
Table 8:
Configuration Register 0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CFG0
AIG1
AIG0
AIPD
AXG1 AXG0 AXPD
INS0
AOS2
AOS1
AOS0 AOPD OPS1
OPS0
OPA1 OPA0
VLPD
AN
A IN
A
M
P
G
a
i
n
SE
T
(
2
bi
t
s
)
AN
A IN
P
o
we
r D
o
wn
AU
X IN
A
M
P
G
a
i
n
SE
T
(
2
bi
t
s
)
AU
X IN
P
o
we
r D
o
wn
I
N
PU
T
SOU
R
CE
MU
X Se
lect
(
1
bit
)
AN
A O
U
T
MUX Se
l
e
c
t
(3
bi
t
s
)
AN
A O
U
T
Po
we
r
D
o
w
n
OU
P
U
T
M
U
X
S
e
lec
t
(
2
b
i
ts
)
SPK
R
& AUX O
U
T
C
o
n
t
ro
l
(
2
bi
t
s
)
V
o
lu
m
e
C
o
n
t
r
o
l P
o
w
e
r
Do
w
n
NOTE:
See details on following pages.
Table 9:
Configuration Register 1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CFG1
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLSO
FLD1
FLD0
FLPD
AGPD
VOL
U
M
E
CO
NT
.
M
U
X
Se
lect
(
2
bit
s
)
VOL
U
M
E
CO
NT
ROL
(
3
b
i
ts)
SU
M
1
MUX Se
l
e
c
t
(2 bi
t
s
)
SU
M 1
SUMMI
N
G
AMP
Co
n
t
r
o
l
(
2
bi
t
s
)
SU
M2 SUMMI
N
G
AMP C
o
n
t
ro
l
(
2
bi
t
s
)
FIL
T
E
R
M
U
X
Selec
t
S
A
M
P
LE
R
A
T
E
(
&
F
i
l
t
er
)
S
e
t
U
p
(
2
b
i
t
s
)
Filte
r
P
o
wer
Do
wn
AG
C AMP Po
w
e
r D
o
wn
17
ISD5008 Product
ISD
Detail of Configuration Register 0
Volume Control
Power Bit
Bit 0
(VLPD)
0 = Power ON
1 = Power OFF
SPEAKER and AUX
OUT Control Bits
Bits 2,1
(OPA1, OPA0)
00 = Power down SPKR and AUX
01 = SPKR ON, HIGH GAIN, AUX Power down
10 = SPKR ON, LOW GAIN, AUX Power down
11 = SPKR Powered down, AUX ON
OUTPUT MUX Control
Bits
Bits 4,3
(OPS1, OPS0)
00 = Source is VOL CONTROL (VOL)
01 = Source is ANA IN Input (ANA IN AMP)
10 = Source is LOW PASS FILTER (FILT0)
11 = Source is SUM2 SUMMING AMP (SUM2)
ANA OUT Power Bit
Bit 5
(AOPD)
0 = Power ON
1 = Power OFF
ANA OUT MUX Con-
trol Bits
Bits 8,7,6
(AOS2, AOS1, AOS0)
000 = Source is MICROPHONE AMP (FTHRU)
001 = Source is INPUT MUX (INP)
010 = Source is VOLUME CONTROL (VOL)
011 = Source is LOW PASS FILTER (FILT0)
100 = Source is SUM1 SUMMING AMP (SUM1)
101 = Source is SUM2 SUMMING AMP (SUM2)
110 = Unused
111 = Unused
INPUT SOURCE MUX
Control Bit
Bit 9
(INS0)
0 = Source is Microphone AGC AMP (AGC)
1 = Source is AUX IN Input (AUX IN AMP)
AUX IN AMP Power Bit
Bit 10
(AXPD)
0 = Power ON
1 = Power OFF
AUX IN AMP Control
Bits
Bits 12,11
(AXG1, AXG0)
00 = Input Gain = 1, O
TLP
input Level = 0.694
01 = Input Gain = 1.414, O
TLP
input Level = 0.491
10 = Input Gain = 2, O
TLP
input Level = 0.347
11 = Input Gain = 2.828, O
TLP
input Level = 0.245
ANA IN AMP Power Bit
Bit 13
(AIPD)
0 = Power ON
1 = Power OFF
ANA IN AMP Control
Bits
Bits 15,14
(AIG1, AIG0)
00 = Input Gain = 0.625, O
TLP
input Level = 1.11
01 = Input Gain = 0.883, O
TLP
input Level = 0.7l85
10 = Input Gain = 1.250, O
TLP
input Level = 0.555
11 = Input Gain = 1.767, O
TLP
input Level = 0.393
18
ISD5008 Product
Voice Solutions in SiliconTM
Configuration Register Notes
1.
Important:
All changes to the internal settings of the ISD5008 are synchronized with the load of Configuration
Register 1. A command to load Configuration Register 1 immediately transfers the input data to the internal
settings of the device and the changes take place immediately at the end of the command when SS\ goes
HIGH. A load to Configuration Register 0 sends the new data to a temporary register in the ISD5008 and does
not affect the internal settings of the device. The next time Configuration Register 1 is loaded, data will also
transfer from the temporary register to the Configuration 0 Register and effect the desired changes. See Figure
Table 13.
2. Configuration Registers may be loaded with data at any time, including when the chip is powered down using
the PU bit in the SPI Control Register. The PU bit in the SPI Control Word will have to be set to a "1" before the
changes in configuration will be seen.
Detail of Configuration Register 1
AGC Power Control
Bit
Bit 0
(AGPD)
0 = Power ON
1 = Power OFF
LOW PASS FILTER
Power Control Bit
Bit 1
(FLPD)
0 = Power ON
1 = Power OFF
SAMPLE RATE and
LOW PASS FILTER
Control Bits
Bits 3,2
(FLD1, FLD0)
00 = Sample Rate = 8 KHz, FPB = 3.4 KHz
01 = Sample Rate = 6.4 KHz, FPB = 2.7 KHz
10 = Sample Rate = 5.3 KHz, FPB = 2.3 KHz
11 = Sample Rate = 4 KHz, FPB = 1.7 KHz
FILTER MUX Control
bits
Bit 4
(FLS0)
0 = Source is SUM1 SUMMING AMP (SUM1)
1 = Source is Analog Memory Array (ARRAY)
SUM 2 SUMMING AMP
Control Bits
Bits 6,5
(S2M1, S2M0)
00 = Source is both ANA IN AMP and FILT0
01 = Source is ANA IN Input (ANA IN AMP) ONLY
10 = Source is LOW PASS FILTER (FILT0) ONLY
11 = Power Down SUM2 SUMMING AMP
SUM1 SUMMING AMP
Control Bits
Bit 8,7
(S1M1, S1M0)
00 = Source is both SUM1 and INP
01 = Source is SUM1 SUMMING AMP (SUM1) ONLY
10 = Source is INPUT MUX (INP) ONLY
11 = Power Down SUM1 SUMMING AMP
SUM1MUX Control Bits
Bit 10,9
(S1S1, S1S0)
00 = Source is ANA IN Input (ANA IN AMP)
01 = Source is Analog Memory Array (ARRAY)
10 = Source is LOW PASS FILTER (FILT0)
11 = UNUSED
VOLUME CONTROL
Control Bits
Bits 13,12,11
(VOL2, VOL1, VOL0)
000 = Attenuation = 0 dB
001 = Attenuation = 4 dB
010 = Attenuation = 8 dB
011 = Attenuation = 12 dB
100 = Attenuation = 16 dB
101 = Attenuation = 20 dB
110 = Attenuation = 24 dB
111 = Attenuation = 28 dB
VOL MUX Control Bits
Bit 15,14 (VLS1, VLS0)
00 = Source is ANA IN Input (ANA IN AMP)
01 = Source is SUM2 SUMMING AMP (SUM2)
10 = Source is SUM1 SUMMING AMP (SUM1)
11 = Source is INPUT MUX (INP)
ISD5008 Product
19
ISD
Figure 13: Configuration Register Programming Sequence
Figure 14: SPI Interface Simplified Block Diagram
1. See Table 8 for bit details.
{
Command =
Load Configuration Register 1
}
Command =
Load Configuration Register 0
Temporary Register
Configuration Register 1
Configuration Register 0
Input Shift Register (16 bits)
MOSI
Control Word (C7-C0)
{
Command =
Load Configuration Register 1
}
Command =
Load Configuration Register 0
Temporary Register
Configuration Register 1
Configuration Register 0
Input Shift Register (16 bits)
MOSI
Control Word (C7-C0)
Configuration Registers
(1)
D15
D15
D0
D0
CFG1
CFG0
D15 - D0
ISD5008 Product
20
Voice Solutions in Silicon
TM
Figure 15: Typical Digital Cellular Phone Integration
RF
Section
Flash
DSP
IF
Interface
Microcontroller
Keypad
Display
EEPROM
Voice Band
Codec
Microphone
Earpiece
ANA OUT+
ANA OUT-
ANA IN
ISD5008
SP+
SP
MIC+
MIC-
SPI
MIC IN+
MIC IN
SP OUT+
SP OUT
AUX IN
AUX OUT
Car Kit
SPI
ISD5008 Product
21
ISD
5
OPERATIONAL MODES DESCRIPTION
The ISD5008 can operate in many different
modes. It's flexibility allows the user to configure
the chip such that almost any input can mixed
with any other input and then be directed to any
output. The variable settings for the ANA and AUX
input amplifiers plus the microphone AGC and
speaker volume controls make it possible to use
the device with most existing cell phone or cord-
less phone chip sets with no external level adjust-
ment. Several modes will be found in most
applications, however. Please refer to the ISD5008
block diagram to better understand the following
modes. In all cases, we are assuming that the
chip has been powered up with the PU bit in the
SPI control register and that a time period of T
PUD
has elapsed after that bit was set:
5.1
FEED THROUGH MODE
This mode enables the ISD5008 to connect to a
base band cell phone or cordless phone chip set
without affecting the audio source or destination.
There are two paths involved, the transmit path
and the receive path. The transmit path connects
the ISD chip's microphone source through to the
microphone input on the base band chip set. The
receive path connects the base band chip set's
speaker output through to the speaker driver on
the ISD chip. This allows the ISD chip to substitute
for those functions and incidentally gain access to
the audio to and from the base band chip set.
Figure 15 shows one possible connection to such
a chip set.
Figure 16 shows the part of the ISD5008 block dia-
gram that is used in Feed Through Mode. The rest
of the chip will be powered down to conserve
power. The bold lines highlight the audio paths.
Note that the Microphone to ANA OUT +/ path is
differential.
Figure 16: Basic Feed-Thru Mode
Chip Set
ANA OUT+
ANA OUT
VOL
ANA OUT
MUX
FILTO
SUM2
3 (AOS2,AOS1,AOS0)
FTHRU
1
(AOPD)
INP
SUM1
Speaker
SP+
SP
ANA IN AMP
OUTPUT
MUX
FILTO
SUM2
2
VOL
(OPS1,OPS0)
2
(OPA1, OPA0)
Chip Set
ANA IN
ANA IN
AMP
.
6
25 /
.
88
3 /
1.
25
/
1
.
7
6
7
1 (AIPD)
2 (AIG1,AIG0)
Microphone
MIC+
MIC
6 dB
ISD5008 Product
22
Voice Solutions in Silicon
TM
To select this mode, the following control bits must
be configured in the ISD5008 configuration regis-
ters. To set up the transmit path:
1.
Select the FTHRU path through the ANA OUT
MUX--
Bits AOS0, AOS1 and AOS2 control
the state of the ANAOUT MUX. These are the
D6, D7 and D8 bits respectively of Configu-
ration Register 0 (CFG0) and they should all
be ZERO to select the FTHRU path.
2.
Power up the ANA OUT amplifier
--Bit AOPD
controls the power up state of ANA OUT. This
is bit D5 of CFG0 and it should be a ZERO
to power up the amplifier.
To set up the receive path:
1.
Set up the ANA IN amplifier for the correct
gain
--Bits AIG0 and AIG1 control the gain
settings of this amplifier. These are bits D14
and D15 respectively of CFG0. The input
level at this pin determines the setting of
this gain stage. Table 4 will help determine
this setting. In this example we will assume
that the peak signal never goes above 1
volt p-p single ended. That would enable
us to use the 9dB attenuation setting, or
where D14 is ONE and D15 is ZERO.
2.
Power up the ANA IN amplifier
--Bit AIPD
controls the power up state of ANA IN. This
is bit D13 of CFG0 and should be a ZERO to
power up the amplifier.
3.
Select the ANA IN path through the OUTPUT
MUX
--Bits OPS0 and OPS1 control the state
of the OUTPUT MUX. These are bits D3 and
D4 respectively of CFG0 and they should
be set to the state where D3 is ONE and D4
is ZERO to select the ANA IN path.
4.
Power up the Speaker Amplifier
--Bits OPA0
and OPA1 control the state of the Speaker
and AUX amplifiers. These are bits D1 and
D2 respectively of CFG0. They should be
set to the state where D1 is ONE and D2 is
ZERO. This powers up the Speaker Amplifier
and configures it for it's higher gain setting
for use with a piezo speaker element and
also powers down the AUX output stage.
The status of the rest of the functions in the ISD5008
chip must be defined before the configuration
registers settings are updated:
1.
Power down the Volume Control Ele-
ment--Bit VLPD controls the power up state
of the Volume Control. This is bit D0 of CFG0
and it should be set to a ONE to power
down this stage.
2.
Power down the AUX IN amplifier--Bit
AXPD controls the power up state of the
AUX IN input amplifier. This is bit D10 of
CFG0 and it should be set to a ONE to pow-
er down this stage.
3.
Power down the SUM1 and SUM2 Mixer
amplifiers--Bits S1M0 and S1M1 control
the SUM1 mixer and bits S2M0 and S2M1
control the SUM2 mixer. These are bits D7
and D8 in CFG1 and bits D5 and D6 in
CFG1 respectively. All 4 bits should be set
to a ONE to power down these two amplifi-
ers.
4.
Power down the FILTER stage--Bit FLPD
controls the power up state of the FILTER
stage in the device. This is bit D1 in CFG1
and should be set to a ONE to power down
the stage.
5.
Power down the AGC amplifier--Bit
AGPD controls the power up state of the
AGC amplifier. This is bit D0 in CFG1 and
should be set to a ONE to power down this
stage.
6.
Don't Care bits--The following stages are
not used in Feed Through Mode. Their bits
may be set to either level. In this example
we will set all the following bits to a ZERO.
(a). Bit INS0, bit D9 of CFG0 controls the In-
put Source Mux. (b). Bits AXG0 and AXG1
are bits D11 and D12 respectively in CFG0.
They control the AUX IN amplifier gain set-
ting. (c). Bits FLD0 and FLD1 are bits D2 and
D3 respectively in CFG1. They control the
sample rate and filter band pass setting.
(d). Bit FLS0 is bit D4 in CFG1. It controls the
FILTER MUX. (e). Bits S1S0 and S1S1 are bits
ISD5008 Product
23
ISD
D9 and D10 of CFG1. They control the
SUM1 MUX. (f). Bits VOL0, VOL1 and VOL2
are bits D11, D12 and D13 of CFG1. They
control the setting of the Volume Control.
(g). Bits VLS0 and VLS1 are bits D14 and D15
of CFG1. They control the Volume Control
MUX.
The end result of the above set up is
CFG0=0100 0100 0000 1011 (hex 440B)
and
CFG1=0000 0001 1110 0011 (hex 01E3).
Since both registers are being loaded, CFG0 is
loaded followed by the loading of CFG1. These
two registers must be loaded in this order. The in-
ternal set up for both registers will take effect syn-
chronously with the rising edge of SS.
5.2
CALL RECORD
The call record mode adds the ability to record
the incoming phone call. In most applications,
the ISD5008 would first be set up for Feed Through
Mode as described above. When the user wishes
to record the incoming call, the set up of the chip
is modified to add that ability. For the purpose of
this explanation, we will use the 6.4 kHz sample
rate during recording.
The block diagram of the ISD5008 shows that the
Multilevel Storage array is always driven from the
SUM2 SUMMING amplifier. The path traces back
from there through the LOW PASS Filter, THE FILTER
MUX, THE SUM1 SUMMING amplifier, the SUM1
MUX, then from the ANA in amplifier. Feed Through
Mode has already powered up the ANA IN amp
so we only need to power up and enable the path
to the Multilevel Storage array from that point:
1.
Select the ANA IN path through the SUM1
MUX
--Bits S1S0 and S1S1 control the state
of the SUM1 MUX. These are bits D9 and
D10 respectively of CFG1 and they should
be set to the state where both D9 and D10
are ZERO to select the ANA IN path.
2.
Select the SUM1 MUX input (only) to the S1
SUMMING amplifier
--Bits S1M0 and S1M1
control the state of the SUM1 SUMMING
amplifier. These are bits D7 and D8 respec-
tively of CFG1 and they should be set to the
state where D7 is ONE and D8 is ZERO to se-
lect the SUM1 MUX (only) path.
3.
Select
the SUM1 SUMMING amplifier path
through the FILTER MUX
--Bit FLS0 controls
the state of the FILTER MUX. This is bit D4 of
CFG1 and it must be set to ZERO to select
the SUM1 SUMMING amplifier path.
4.
Power up the LOWPASS FILTER
--Bit FLPD
controls the power up state of the LOWPASS
FILTER stage. This is bit D1 of CFG1 and it
must be set to ZERO to power up the LOW
PASS FILTER STAGE.
5.
Select the 6.4 kHz sample rate--Bits
FLD0 and FLD1 select the Low Pass filter set-
ting and sample rate to be used during
record and playback. These are bits D2
and D3 of CFG1. To enable the 6.4 kHz
sample rate, D2 must be set to ONE and
D3 set to ZERO.
6.
Select the LOW PASS FILTER input (only)
to the S2 SUMMING amplifier--Bits S2M0
and S2M1 control the state of the SUM2
SUMMING amplifier. These are bits D5 and
D6 respectively of CFG1 and they should
be set to the state where D5 is ZERO and D6
is ONE to select the LOW PASS FILTER (only)
path.
In this mode, the elements of the original PASS
THROUGH mode do not change. The sections of
the chip not required to add the record path re-
main powered down. In fact, CFG0 does not
change and remains
CFG0=0100 0100 0000 1011 (hex 440B).
CFG1 changes to
CFG1=0000 0000 1100 0101 (hex 00C5).
Since CFG0 is not changed, it is only necessary to
load CFG1. Note that if only CFG0 was changed,
it would be necessary to load both registers.
ISD5008 Product
24
Voice Solutions in Silicon
TM
5.3
MEMO RECORD
The Memo Record mode sets the chip up to
record from the local microphone into the chip's
Multilevel Storage Array. A connected cellular
telephone or cordless phone chip set may remain
powered down and is not active in this mode. The
path to be used is microphone input to AGC am-
plifier, then through the INPUT SOURCE MUX to the
SUM1 SUMMING amplifier. From there the path
goes through the FILTER MUX, the LOW PASS FILTER,
the SUM2 SUMMING amplifier, then to the MULTI-
LEVEL STORAGE ARRAY. In this instance, we will se-
lect the 5.3 kHz sample rate. The rest of the chip
may be powered down.
1.
Power up the AGC amplifier--Bit AGPD
controls the power up state of the AGC
amplifier. This is bit D0 of CFG1 and must
be set to ZERO to power up this stage.
2.
Select the AGC amplifier through the INPUT
SOURCE MUX
--Bit INS0 controls the state of
the INPUT SOURCE MUX. This is bit D9 of
CFG0 and must be set to a ZERO to select
the AGC amplifier.
3.
Select the INPUT SOURCE MUX (only) to
the S1 SUMMING amplifier--Bits S1M0
and S1M1 control the state of the SUM1
SUMMING amplifier. These are bits D7 and
D8 respectively of CFG1 and they should
be set to the state where D7 is ZERO and D8
is ONE to select the INPUT SOURCE MUX
(only) path.
4.
Select the SUM1 SUMMING amplifier
path through the FILTER MUX--Bit FLS0
controls the state of the FILTER MUX. This is
bit D4 of CFG1 and it must be set to ZERO
to select the SUM1 SUMMING amplifier
path.
5.
Power up the LOWPASS FILTER--Bit FLPD
controls the power up state of the LOWPASS
FILTER stage. This is bit D1 of CFG1 and it
must be set to ZERO to power up the LOW
PASS FILTER STAGE.
6.
Select the 5.3 kHz sample rate
--Bits FLD0
and FLD1 select the Low Pass filter setting
and sample rate to be used during record
and playback. These are bits D2 and D3 of
CFG1. To enable the 5.3 kHz sample rate,
D2 must be set to ZERO and D3 set to ONE.
7.
Select the LOW PASS FILTER input (only)
to the S2 SUMMING amplifier--Bits S2M0
and S2M1 control the state of the SUM2
SUMMING amplifier. These are bits D5 and
D6 respectively of CFG1 and they should
be set to the state where D5 is ZERO and D6
is ONE to select the LOW PASS FILTER (only)
path.
To set up the chip for Memo Record, the configu-
ration registers are set up as follows:
CFG0=0010 0100 0010 0001 (hex 2421).
CFG1=0000 0001 0100 1000 (hex 0148).
Only those portions necessary for this mode are
powered up.
5.4
MEMO AND CALL PLAYBACK
This mode sets the chip up for local playback of
messages recorded earlier. The playback path is
from the MULTILEVEL STORAGE ARRAY to the FILTER
MUX, then to the LOW PASS FILTER stage. From
there the audio path goes through the SUM2 SUM-
MING amplifier to the VOLUME MUX, through the
VOLUME CONTROL then to the SPEAKER output
stage. We will assume that we are driving a pizeo
speaker element. This audio was previously re-
corded at 8 kHz. All unnecessary stages will be
powered down.
1.
Select the MULTILEVEL STORAGE ARRAY
path through the FILTER MUX--Bit FLS0,
the state of the FILTER MUX. This is bit D4 of
CFG1 and must be set to ONE to select the
MULTILEVEL STORAGE ARRAY.
2.
Power up the LOWPASS FILTER--Bit FLPD
controls the power up state of the LOWPASS
FILTER stage. This is bit D1 of CFG1 and it
must be set to ZERO to power up the LOW
PASS FILTER STAGE.
3.
Select the 8.0 kHz sample rate
--Bits FLD0
and FLD1 select the Low Pass filter setting
and sample rate to be used during record
ISD5008 Product
25
ISD
and playback. These are bits D2 and D3 of
CFG1. To enable the 8.0 kHz sample rate,
D2 and D3 must be set to ZERO.
4.
Select the LOW PASS FILTER input (only) to
the S2 SUMMING amplifier
--Bits S2M0 and
S2M1 control the state of the SUM2 SUM-
MING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be
set to the state where D5 is ZERO and D6 is
ONE to select the LOW PASS FILTER (only)
path.
5.
Select the SUM2 SUMMING amplifier
path through the VOLUME MUX--Bits
VLS0 and VLS1 control the state VOLUME
MUX. These bits are bits D14 and D15, re-
spectively of CFG1. They should be set to
the state where D14 is ONE and D15 is ZERO
to select the SUM2 SUMMING amplifier.
6.
Power up the VOLUME CONTROL LEVEL--
Bit VLPD controls the power-up state of the
VOLUME CONTROL attenuator. This is Bit D0
of CFG0. This bit must be set to a ZERO to
power-up the VOLUME CONTROL.
7.
Select a VOLUME CONTROL LEVEL--Bits
VOL0, VOL1, and VOL2 control the state of
the VOLUME CONTROL LEVEL. These are bits
D11, D12, and D13, respectively, of CFG1.
A binary count of 000 through 111 controls
the amount of attenuation through that
state. In most cases, the software will select
an attenuation level according to the de-
sires of the current users of the product. In
this example, we will assume the user wants
an attenuation of 12 dB. For that setting,
D11 should be set to ONE, D12 should be
set to ONE, and D13 should be set to a ZE-
RO.
8.
Select the VOLUME CONTROL path
through the OUTPUT MUX--These are bits
D3 and D4, respectively, of CFG0. They
should be set to the state where D3 is ZERO
and D4 is a ZERO to select the VOLUME
CONTROL.
9.
Power up the SPEAKER amplifier and se-
lect the HIGH GAIN mode--Bits OPA0
and OPA1 control the state of the speaker
(SP+ and SP) and AUX OUT outputs. These
are bits D1 and D2 of CFG0. They must be
set to the state where D1 is ONE and D2 is
ZERO to power-up the speaker outputs in
the HIGH GAIN mode and to power-down
the AUX OUT.
To set up the chip for Memo or Call Playback, the
configuration registers are set up as follows:
CFG0=0010 0100 0010 0010 (hex 2422).
CFG1=0101 1001 1101 0001 (hex 59D1).
Only those portions necessary for this mode are
powered up.
26
ISD5008 Product
Voice Solutions in SiliconTM
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum
ratings may affect device reliability. Functional operation is not implied at these conditions.
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum
ratings may affect device reliability. Functional operation is not implied at these conditions.
1. Case Temperature
2. V
CC
= V
CCA
= V
CCD
3. V
SS
= V
SSA
= V
SSD
1. V
CC
= V
CCA
= V
CCD
2. V
SS
= V
SSA
= V
SSD
Table 10: Absolute Maximum Ratings (Packaged Parts)
(1)
Condition
Value
Junction temperature
150C
Storage temperature range
65C to +150C
Voltage applied to any pin
(V
SS
0.3 V) to (V
CC
+ 0.3 V)
Voltage applied to MOSI, SCLK, INT, RAC and SS pins (Input
current limited to 20mA)
(V
SS
1.0 V) to 5.5V
Lead temperature (soldering 10 seconds)
300C
V
CC
V
SS
0.3 V to +7.0 V
Table 11: Absolute Maximum Ratings (Die)
(1)
Condition
Value
Junction temperature
150C
Storage temperature range
65C to +150C
Voltage applied to MOSI, SCLK, INT, RAC and SS pins (Input
current limited to 20mA)
(V
SS
0.3 V) to 5.5V
V
CC
V
SS
0.3 V to +7.0 V
Table 12: Operating Conditions (Packaged Parts)
Condition
Value
Commercial operating temperature range
(1)
0 C t o + 7 0 C
Extended operating temperature
(1)
20C to +70C
Industrial operating temperature
( 1 )
40C to +85C
Supply voltage (V
C C
)
( 2 )
+2.7 V to +3.3 V
Ground voltage (V
SS
)
( 3 )
0 V
Table 13: Operating Conditions (Die)
Condition
Value
Commercial operating temperature range
0C to +50C
Supply voltage (V
C C
)
( 1 )
+2.7 V to +3.3 V
Ground voltage (V
SS
)
( 2 )
0 V
27
ISD5008 Product
ISD
1. Typical values: T
A
= 25C and Vcc = 3.0 V.
2. All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are
100 percent tested.
3. V
CCA
and V
CCD
summed together.
4. SS = V
CCA
= V
CCD,
XCLK = MOSI = V
SSA
= V
SSD
and all other pins floating.
Table 14: General Parameters
Symbol
Parameters
Min(2)
Typ(1)
Max(2)
Units
Conditions
V
IL
Input Low Voltage
V
CC
x 0.2
V
V
IH
Input High Voltage
V
CC
x 0.8
V
V
OL
Output Low Voltage
0.4
V
I
OL
= 10 A
V
OL1
RAC, INT Output Low
Voltage
0.4
V
I
OL
= 1 mA
V
OH
Output High Voltage
V
CC
0.4
V
I
OH
= 10 A
I
CC
V
CC
Current (Operating)
-- Playback
-- Record
-- Feedthru
15
25
12
mA
mA
mA
No load
(3)
No load
(3)
No load
(3)
I
SB
V
CC
Current (Standby)
1
10
A
(3) (4)
I
IL
Input Leakage Current
1
A
I
HZ
MISO Tristate Current
1
10
A
28
ISD5008 Product
Voice Solutions in SiliconTM
Table 15: Timing Parameters
Symbol
Characteristic
Min
(2)
Typ
(1)
Max
(2)
Units
Conditions
F
S
Sampling Frequency
8.0
6.4
5.3
4.0
kHz
kHz
kHz
kHz
(5)
(5)
(5)
(5)
F
CF
Filter Pass Band
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
3.4
2.7
2.3
1.7
kHz
kHz
kHz
kHz
3-dB Roll-Off Point
(3) (7)
3-dB Roll-Off Point
(3) (7)
3-dB Roll-Off Point
(3) (7)
3-dB Roll-Off Point
(3) (7)
T
REC
Record Duration
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
4
5
6
8
min
min
min
min
(6)
(6)
(6)
(6)
T
PLAY
Playback Duration
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
4
5
6
8
min
min
min
min
(6)
(6)
(6)
(6)
T
PUD
Power-Up Delay
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
25
31.25
37.5
50
msec
msec
msec
msec
T
STOP
OR
PAUSE
Stop or Pause
Record or Play
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
50
62.5
75
100
msec
msec
msec
msec
T
RAC
RAC Clock Period
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
200
250
300
400
msec
msec
msec
msec
(9)
(9)
(9)
(9)
T
RACLO
RAC Clock Low Time
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
25
31.25
37.5
50
msec
msec
msec
msec
29
ISD5008 Product
ISD
T
RACM
RAC Clock Period in
Message Cueing
Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
125
156.3
187.5
250
sec
sec
sec
sec
T
RACML
RAC Clock Low Time in
Message Cueing
Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
15.63
19.53
23.44
31.25
sec
sec
sec
sec
THD
Total Harmonic
Distortion
ANA IN to ARRAY,
ARRAY to SPKR
1
2
%
@1 kHz at 0TLP, sample rate =
5.3kHz
Table 16: Analog Parameters
Symbol
Characteristic
Min
(2)
Typ
(1)
Max
(2)
Units
Conditions
MICROPHONE INPUT
(14)
V
MIC+/
MIC +/ Input Voltage
3
300
mV
Peak-to-Peak
(4)(8)
V
MIC (0TLP)
MIC +/ input
reference transmission
level point (0TLP)
208
mV
Peak-to-Peak
(4)(10)
A
MIC
Gain from MIC+/
input to ANA OUT
5.5
6.0
6.5
dB
1 kHz at V
MIC (0TLP)
(4)
A
MIC (GT)
MIC +/ Gain Tracking
0.1
dB
1 kHz, +3 to 40 dB 0TLP Input
R
MIC
Microphone
input
resistance
5
10
15
k
MIC and MIC+ pins
A
AGC
Microphone AGC
Amplifier Range
6
40
dB
Over 3300 mV Input Range
ANA IN
(14)
V
ANA
IN
ANA IN Input Voltage
1.6
V
Peak-to-Peak (6dB gain
setting)
V
ANA
IN (0TLP)
ANA IN (0TLP) Input
Voltage
1.11
V
Peak-to-Peak (6dB gain
setting)
(10)
A
ANA
IN (SP)
Gain from ANA IN to
SP+/
6 to 15
dB
4 Steps of 3 dB
Table 15: Timing Parameters
Symbol
Characteristic
Min
(2)
Typ
(1)
Max
(2)
Units
Conditions
30
ISD5008 Product
Voice Solutions in SiliconTM
Symbol
Characteristic
Min
(2)
Typ
(1)
Max
(2)
Units
Conditions
A
ANA
IN (AUX OUT)
Gain from ANA IN to
AUX OUT
4 to +5
dB
4 Steps of 3 dB
A
ANA
IN (GA)
ANA IN Gain Accuracy
0.5
+0.5
dB
(11)
A
ANA
IN (GT)
ANA IN Gain Tracking
0.1
dB
1000 Hz, +3 to
40 dB 0TLP Input, 6dB setting
R
ANA
IN
ANA IN Input
Resistance
60 to 102
k
See Ra in Figure 2
AUX IN
(14)
V
AUX
IN
AUX IN Input Voltage
1.0
V
Peak-to-Peak (0 dB gain
setting)
V
AUX
IN (0TLP)
AUX IN (0TLP) Input
Voltage
694.2
mV
Peak-to-Peak (0 dB gain
setting)
(10)
A
AUX
IN (ANA OUT)
Gain from AUX IN to
ANA OUT
0 to 9
dB
4 Steps of 3dB
A
AUX
IN (GA)
AUX IN Gain Accuracy
0.5
+0.5
dB
(11)
A
Aux
IN (GT)
AUX IN Gain Tracking
0.1
dB
1000 Hz, +3 to
40 dB 0TLP Input, 0dB setting
R
Aux
IN
AUX IN Input
Resistance
21 to 40
k
See Ra in Figure 3
SPEAKER OUTPUTS
(14)
V
SPHG
SP+/ Output Voltage
(High Gain setting)
3.6
V
Peak-to-Peak, differential load
= 150
; OPA1, OPA0 = 01
R
SPLG
SP+/ Output Load
Imp. (Low Gain)
8
OPA1, OPA0 = 10
R
SPHG
SP+/ Output Load
Imp. (High Gain)
70
OPA1, OPA0 = 01
C
SP
SP+/ Output Load
Cap.
100
pF
V
SPAG
SP+/ Output Bias
Voltage (analog
ground)
1.2
VDC
V
SPDCO
Speaker Output DC
Offset
100
100
mVDC
With ANA IN to Speaker, ANA IN
AC coupled to V
SSA
ICN
ANA IN/(SP+/)
ANA IN to SP+/ Idle
Channel Noise
65
dB
Speaker load = 150
(12)(13)
C
R
T
(SP+/)/ANA
OUT
SP+/ to ANA OUT
Cross Talk
65
dB
1kHz 0TLP input to ANA IN, with
MIC+/ and AUX IN AC
coupled to V
SSA
, and
measured at ANA OUT
feedthrough mode
(12)
PSRR
Power Supply
Rejection Ratio
50
dB
Measured with a 1kHz,100
mVpp sine wave input at V
CCA
and V
CCD
pins
Table 16: Analog Parameters
31
ISD5008 Product
ISD
Symbol
Characteristic
Min
(2)
Typ
(1)
Max
(2)
Units
Conditions
F
R
Frequency Response
(3003400 Hz)
0.25
+0.25
dB
With 0TLP input to ANA IN, 6dB
setting
(12)
P
OUTLG
Power Output (Low
Gain Setting)
23.5
mW
RMS
Differential load at 8
SINAD
SINAD ANA IN to
SP+/
62.5
dB
0TLP ANA IN input minimum
gain, 150
load
(12)(13)
ANA OUT
(14)
SINAD
SINAD MIC IN to ANA
OUT +/-
62.5
dB
Load = 5k
(12)(13)
SINAD
SINAD AUX IN to ANA
OUT (0 to 9 dB)
62.5
dB
Load = 5k
(12)(13)
ICN
MIC/ANA OUT
Idle Channel Noise--
Microphone
65
dB
Load = 5k
(12)(13)
ICN
AUX IN/ANA
OUT
Idle Channel Noise--
AUX IN (0 to 9 dB)
65
dB
Load = 5k
(12)(13)
PSRR
(ANA OUT)
Power Supply
Rejection Ratio
-50
dB
Measured with a 1kHz,
100mVpp sine wave to V
CCA
,
V
CCD
pins
V
BIAS
ANA OUT+ and ANA
OUT
1.2
VDC
Inputs AC coupled to V
SSA
V
OFFSET
ANA OUT+ to ANA
OUT
100
+100
mVDC
Inputs AC coupled to V
SSA
R
L
Minimum Load
Impedence
5
k
Differential Load
F
R
Frequency Response
(3003400 Hz)
0.25
+0.25
dB
0TLP input to MIC+/- in
feedthrough mode.
0TLP input to AUX IN in
feedthrough mode
(12)
C
R
T
ANA OUT/(SP+/-)
ANA OUT to SP+/-
Cross Talk
65
dB
1kHz 0TLP output from ANA
OUT, with ANA IN AC coupled
to V
SSA
, and measured at
SP+/-
(12)
C
R
T
ANA OUT/AUX OUT
ANA OUT to AUX OUT
Cross Talk
65
dB
1kHz 0TLP output from ANA
OUT, with ANA IN AC coupled
to V
SSA
, and measured at AUX
OUT(12)
AUX OUT
(14)
V
AUX OUT
AUX OUT--Maximum
Output Swing
1.0
Vpp
5 k
Load
R
L
Minimum Load
Impedence
5
k
C
L
Maximum Load
Capacitance
100
pF
Table 16: Analog Parameters
32
ISD5008 Product
Voice Solutions in SiliconTM
1. Typical values: T
A
= 25C and Vcc = 3.0V.
2. All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are
100 percent tested.
3. Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions).
4. Differential input mode. Nominal differential input is 208 mVp-p. (0 dBm0)
5. Sampling frequency can vary as much as 6/+4 percent over the industrial temperature and voltage ranges.
For greater stability, an external clock can be utilized (see Pin Descriptions). Sampling frequency will be accurate
within 1% for 5.3kHz, and 5% for 4.0, 6.4 and 8.0 kHz sampling rates at room temperature.
6. Playback and Record Duration can vary as much as 6/+4 percent over the industrial temperature and voltage
ranges. For greater stability, an external clock can be utilized (See Pin Descriptions). Playback and record durations
are accurate within 1% for 5.3kHz, and 5% for 4.0, 6.4 and 8.0kHz sampling rates at room temperature.
7. Filter specification applies to the low pass filter. Therefore, from input to output, expect a 6 dB drop by nature
of passing through the filter twice.
8. For optimal signal quality, this maximum limit is recommended.
9. When a record command is sent, T
RAC
= T
RAC
+ T
RACLO
on the first row addressed.
10. The maximum signal level at any input is defined as 3.17dB higher than the reference transmission level point.
(0TLP) This is the point where signal clipping may begin.
11. Measured at 0TLP point for each gain setting. See Table 4 and Table 5.
12. 0TLP is the reference test level through inputs and outputs. See Table 4 and Table 5.
13. Referenced to 0TLP input at 1kHz, measured over 300 to 3,400 Hz bandwidth.
14. For die, only typical values from Analog Parameters are applicable.
Symbol
Characteristic
Min
(2)
Typ
(1)
Max
(2)
Units
Conditions
V
BIAS
AUX OUT
1.2
VDC
SINAD
SINAD--ANA IN to AUX
OUT
62.5
dB
0TLP ANA IN input, minimum
gain, 5k load
(12)(13)
ICN
(AUX OUT)
Idle Channel Noise--
ANA IN to AUX OUT
65
dB
Load = 5k
(12)(13)
C
R
T
AUX OUT/ANA
OUT
AUX OUT to ANA OUT
cross Talk
65
dB
1 kHz 0TLP input to ANA IN, with
MIC +/- and AUX IN AC
coupled to V
SSA
, and
measured at SP+/-, load =
5k
. Referenced to nominal
0TLP @ output
VOLUME CONTROL
(14)
A
OUT
Output Gain
28 to 0
dB
8 Steps of 4 dB, referenced to
output
Gain Accuracy
-0.5
0.5
dB
ANA IN = 1 kHz 0TLP, 6dB Gain
setting, measured differentially
at SP+/
Table 16: Analog Parameters
33
ISD5008 Product
ISD
Table 17: SPI AC Parameters
(1)
1. Typical values: T
A
= 25C and V
cc
= 3.0 V. Timing measured at 50 percent of the V
CC
level.
2. Tristate test condition
Symbol
Characteristics
Min
Max
Units
Conditions
T
SSS
SS Setup Time
500
nsec
T
SSH
SS Hold Time
500
nsec
T
DIS
Data in Setup Time
200
nsec
T
DIH
Data in Hold Time
200
nsec
T
PD
Output Delay
500
nsec
T
DF
Output Delay to hiZ
500
nsec
(2)
T
SSmin
SS HIGH
1
sec
T
SCKhi
SCLK High Time
400
nsec
T
SCKlow
SCLK Low Time
400
nsec
F
0
CLK Frequency
1,000
kHz
34
ISD5008 Product
Voice Solutions in SiliconTM
6
TIMING DIAGRAMS
Figure 17: SPI Timing Diagram
Figure 18: 8-Bit SPI Command Format
35
ISD5008 Product
ISD
Figure 19: 24-Bit SPI Command Format
Figure 20: Playback/Record and Stop Cycle
SS
MOSI
MISO
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
C3
C4
C5
C6
C7
D0
D1
D2
D3
D4
D5
A4
A5
A6
A7
A8
A9
OVF
EOM
A0
A1
A2
A3
A10
SCLK
BYTE 1
BYTE 2
BYTE 3
A11
A12
A13
A14
A15
X
X
X
X
X
X
C2
C1
C0
36
ISD5008 Product
Voice Solutions in SiliconTM
7
DEVICE PHYSICAL DIMENSIONS
Figure 21: 28-Lead 8x13.4 mm Plastic Thin Small Outline Package (TSOP) Type I (E)
NOTE:
Lead coplanarity to be within 0.004 inches.
Table 18: Plastic Thin Small Outline Package (TSOP) Type I (E) Dimensions
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
0.520
0.528
0.535
13.20
13.40
13.60
B
0.461
0.465
0.469
11.70
11.80
11.90
C
0.311
0.315
0.319
7.90
8.00
8.10
D
0.002
0.006
0.05
0.15
E
0.007
0.009
0.011
0.17
0.22
0.27
F
0.0217
0.55
G
0.037
0.039
0.041
0.95
1.00
1.05
H
0
3
6
0
3
6
I
0.020
0.022
0.028
0.50
0.55
0.70
J
0.004
0.008
0.10
0.21
37
ISD5008 Product
ISD
Figure 22: 28-Lead 0.600-Inch Plastic Dual Inline Package (PDIP) (P)
Table 19: Plastic Dual Inline Package (PDIP) (P) Dimensions
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
1.445
1.450
1.455
36.70
36.83
36.96
B1
0.150
3.81
B2
0.065
0.070
0.075
1.65
1.78
1.91
C1
0.600
0.625
15.24
15.88
C2
0.530
0.540
0.550
13.46
13.72
13.97
D
0.19 4.83
D1
0.015
0.38
E
0.125
0.135
3.18
3.43
F
0.015
0.018
0.022
0.38
0.46
0.56
G
0.055
0.060
0.065
1.40
1.52
1.65
H
0.100
2.54
J
0.008
0.010
0.012
0.20
0.25
0.30
S
0.070
0.075
0.080
1.78
1.91
2.03
0
15
0
15
ISD5008 Product
38
Voice Solutions in Silicon
TM
Figure 23: 28-Lead 0.300-Inch Plastic Small Outline Integrated Circuit (SOIC) (S)
NOTE:
Lead coplanarity to be within 0.004 inches.
Table 20: Plastic Small Outline Integrated Circuit (SOIC) (S) Dimensions
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
0.701
0.706
0.711
17.81
17.93
18.06
B
0.097
0.101
0.104
2.46
2.56
2.64
C
0.292
0.296
0.299
7.42
7.52
7.59
D
0.005
0.009
0.0115
0.127
0.22
0.29
E
0.014
0.016
0.019
0.35
0.41
0.48
F
0.050
1.27
G
0.400
0.406
0.410
10.16
10.31
10.41
H
0.024
0.032
0.040
0.61
0.81
1.02
ISD5008 Product
39
ISD
Figure 24: ISD5008 Series Bonding Physical Layout
(1)
(Unpackaged Die)
1. The backside of die is internally connected to V
SS
. It MUST NOT be connected to any other potential or damage
may occur.
2. Double bond recommended.
3. This figure reflects the current die thickness. Please contact ISD as this thickness may change in the future.
ISD5008 Series
I.
Die Dimensions
X: 166.5 1 mils
Y: 302.4 1 mils
II.
Die Thickness
(3)
11.5 1.0 mils
III.
Pad Opening (min)
90 x 90 microns
3.5 x 3.5 mils
V
S S D
ISD5008
V
SSA
V
SSA
MIC+
AUX IN
ANA IN
ANAOUT+
M I C
V
SSA
( 2 )
ANAOUT
ACAP
AUXOUT
S P
V
CCA
(2)
SP+
R A C
V
S S D
MISO
MOSI
SS
S C L K
V
CCD
V
CCD
INT
X C L K
ISD5008 Product
40
Voice Solutions in Silicon
TM
Table 21: ISD5008 Series Device Pin/Pad Designations,
with Respect to Die Center (m)
1. Double bond recommended.
Pin
Pin Name
X Axis
Y Axis
V
SSD
V
SS
Digital Power Supply
1837.0
3623.7
V
SSD
V
SS
Digital Power Supply
1665.4
3623.7
MISO
Master In Slave Out
1325.7
3623.7
MOSI
Master Out Slave In
1063.8
3623.7
SS
Slave Select
198.2
3623.7
SCLK
Slave Clock
14.8
3623.7
V
CCD
V
CC
Digital Power Supply
169.4
3623.7
V
CCD
V
CC
Digital Power Supply
384.8
3623.7
XCLK
External Clock Input
564.7
3623.7
INT
Interrupt
794.7
3623.7
RAC
Row Address Clock
1483.7
3623.7
V
SSA
V
SS
Analog Power Supply
1885.1
3623.7
V
SSA
V
SS
Analog Power Supply
1943.2
3615.9
MIC+
Noninverting Microphone Input
1735.4
3615.9
MIC
Inverting Microphone Input
1502.9
3615.9
ANA OUT+
Noninverting Analog Output
--1251.2
3615.9
ANA OUT
Inverting Analog Output
917.0
3615.9
ACAP
AGC/AutoMute Cap
632.6
3615.9
SP
Inverting Speaker Output
138.4
3615.9
V
SSA
(1)
V
SS
Analog Power Supply
240.2
3615.9
SP+
Noninverting Speaker Output
618.8
3615.9
V
CCA
(1)
V
CC
Analog Power Supply
997.4
3615.9
ANA IN
Analog Input
1249.9
3615.9
AUX IN
Auxiliary Input
1515.5
3615.9
AUX OUT
Auxiliary Output
1758.4
3615.9
ISD5008 Product
41
ISD
Figure 25:
SD5008 Chip Scale Package (CSP) (Z)
Table 22:
CSP Dimensions (mm)
e
TOP VIEW
BOTTOM VIEW
G
F
e
I
H
C
A
A
2
A
1
b
SIDE VIEW
A5
A4
A3
B5
B4
B3
B2
C5
C4
C3
C2
D5
D4
D3
D2
E5
E4
E3
E2
A1 Ball Corner
D
A2
A1
B1
C1
D1
E1
Symbol
Min.
Nom.
Max.
A
--
--
0.86
A
1
0.18
--
--
A
2
--
0.55
--
b
0.30
0.35
0.40
C
--
4.68
--
D
--
8.13
--
e
0.75
F
--
3.00
--
G
--
0.84
--
H
--
2.57
--
I
--
3.00
--
PIN
Name
Ball
Location
MIC-
A1
ACAP
A2
V
SSA
A3
V
CCA
A4
AUX IN
A5
MIC+
B1
ANA OUT-
B2
SP-
B3
ANA IN
B4
AUX OUT
B5
V
SSA
C1
ANA OUT+
C2
SP+
C3
V
CCD
C4
V
SSA
C5
V
SSD
D1
MISO
D2
SS
D3
XCLK
D4
RAC
D5
VSSD
E1
MOSI
E2
SCLK
E3
VCCD
E4
INT
E5
ISD5008 Product
42
Voice Solutions in Silicon
TM
8
ORDERING INFORMATION
When ordering ISD5008 series devices, please refer to the following valid part numbers.
For the latest product information, access ISD's worldwide website at http://www.isd.com.
Part Number
ISD5008E
ISD5008ED
ISD5008EI
ISD5008P
ISD5008S
ISD5008SD
ISD5008SI
ISD5008X
ISD5008Z
ISD5008ZD
ISD5008ZI
Product Family
ISD5008 Product
(4 to 8 minute durations)
Special Temperature Field:
Blank =
Commercial Packaged (0C to +70C)
or
Commercial Die (0C to +50C)
D
=
Extended (20C to +70C)
I
=
Industrial (40C to +85C)
Package Type:
E
=
28-Lead 8x13.4mm Plastic Thin Small Outline
Package (TSOP) Type 1
P
=
28-Lead 0.600-Inch Plastic Dual Inline Package
(PDIP)
S
=
28-Lead 0.300-Inch Plastic Small Outline Package
(SOIC)
X
=
Die
Z
=
Chip Scale Package (CSP)
ISD5008_ _
ISD Part Number Description
ISD5008 Product
43
ISD
Part No. ISD5008PDS1-799
2727 North First Street
San Jose, California 95134
Tel: 408/943-6666
Fax: 408/544-1787
http://www.isd.com
IMPORTANT NOTICES
The warranty for each product of ISD (Information Storage
Devices, Inc.), is contained in a written warranty which governs
sale and use of such product. Such warranty is contained in the
printed terms and conditions under which such product is sold, or
in a separate written warranty supplied with the product. Please
refer to such written warranty with respect to its applicability to
certain applications of such product.
These Products may be subject to restrictions on use. Please
contact ISD for a list of the current additional restrictions on these
Products. By purchasing these Products, the purchaser of these
Products agrees to comply with such use restrictions. Please
contact ISD for clarification of any restrictions described herein.
ISD, reserves the right, without further notice, to change the ISD
ChipCorder product specifications and/or information in this
document and to improve reliability, functions and design.
ISD assumes no responsibility or liability for any use of the ISD
ChipCorder Product. ISD conveys no license or title, either
expressed or implied, under any patent, copyright, or mask work
right to the ISD ChipCorder Product, and ISD makes no warranties
or representations that the ISD ChipCorder Product are free from
patent, copyright, or mask work right infringement, unless
otherwise specified.
Application examples and alternative uses of any integrated
circuit contained in this publication are for illustration purposes
only and ISD makes no representation or warranty that such
applications shall be suitable for the use specified.
The 100-year retention and 100K record cycle projections are
based upon accelerated reliability tests, as published in the ISD
Reliability Report, and are neither warranted nor guaranteed by
ISD.
Information contained in this ISD ChipCorder data sheet
supersedes all data for the ISD ChipCorder Product published by
ISD prior to October, 1999.
This data sheet and any future addendum to this data sheet is
(are) the complete and controlling ISD ChipCorder product
specifications. In the event any inconsistencies exist between the
information in this and other product documentation, or in the
event that other product documentation contains information in
addition to the information in this, the information contained
herein supersedes and governs such other information in its entirety.
Copyright 1999, ISD (Information Storage Devices, Inc.) All rights
reserved. ISD is a registered trademark of ISD. ChipCorder is a
trademark of ISD. All other trademarks are properties of their
respective owners.
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