Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. B
03/10/05
IS61LV51216
ISSI
Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
High-speed access time:
-- 8, 10, and 12 ns
CMOS low power operation
Low stand-by power:
-- Less than 5 m
A
(typ.) CMOS stand-by
TTL compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Lead-free available
512K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
DESCRIPTION
The
ISSI
IS61LV51216 is a high-speed, 8M-bit static RAM
organized as 525,288 words by 16 bits. It is fabricated using
ISSI
's high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques,
yields high-performance and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs,
CE
and
OE
. The active LOW Write Enable
(
WE
) controls both writing and reading of the memory. A data
byte allows Upper Byte (
UB
) and Lower Byte (
LB
) access.
The IS61LV51216 is packaged in the JEDEC standard
44-pin TSOP Type II and 48-pin Mini BGA (9mm x 11mm).
FUNCTIONAL BLOCK DIAGRAM
MARCH 2005
A0-A18
CE
OE
WE
512K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
03/10/05
IS61LV51216
ISSI
TRUTH TABLE
I/O PIN
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
LB
LB
LB
LB
LB
UB
UB
UB
UB
UB
I/O0-I/O7
I/O8-I/O15
V
DD
Current
Not Selected
X
H
X
X
X
High-Z
High-Z
I
SB
1
, I
SB
2
Output Disabled
H
L
H
X
X
High-Z
High-Z
I
CC
X
L
X
H
H
High-Z
High-Z
Read
H
L
L
L
H
D
OUT
High-Z
I
CC
H
L
L
H
L
High-Z
D
OUT
H
L
L
L
L
D
OUT
D
OUT
Write
L
L
X
L
H
D
IN
High-Z
I
CC
L
L
X
H
L
High-Z
D
IN
L
L
X
L
L
D
IN
D
IN
PIN DESCRIPTIONS
A0-A18
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
V
DD
Power
GND
Ground
44-Pin TSOP (Type II)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
A18
A14
A13
A12
A11
A10
PIN CONFIGURATIONS
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. B
03/10/05
1
2
3
4
5
6
7
8
9
10
11
12
IS61LV51216
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to V
DD
+0.5
V
V
DD
V
DD
Related to GND
0.3 to +4.0
V
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
48-Pin mini BGA (9mmx11mm)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
N/C
I/O
8
UB
A3
A4
CE
I/O
0
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
GND
I/O
11
A17
A7
I/O
3
VDD
VDD
I/O
12
GND
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
A18
A8
A9
A10
A11
NC
PIN CONFIGURATIONS
PIN DESCRIPTIONS
A0-A18
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
V
DD
Power
GND
Ground
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
03/10/05
IS61LV51216
ISSI
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8
-10
-12
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
V
DD
Dynamic Operating
V
DD
= Max.,
Com.
--
110
--
100
--
90
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
120
--
110
--
100
I
SB
1
TTL Standby Current
V
DD
= Max.,
Com.
--
30
--
30
--
30
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
--
35
--
35
--
35
CE
V
IH
, f = 0
I
SB
2
CMOS Standby
V
DD
= Max.,
Com.
--
20
--
20
--
20
mA
Current (CMOS Inputs)
CE
V
DD
0.2V,
Ind.
--
25
--
25
--
25
V
IN
V
DD
0.2V, or
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
DD
+ 0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
DD
Com.
1
1
A
Ind.
5
5
I
LO
Output Leakage
GND
V
OUT
V
DD
Com.
1
1
A
Outputs Disabled
Ind.
5
5
Notes:
1. V
IL
(min.) = 2.0V for pulse width less than 10 ns.
OPERATING RANGE
Range
Ambient Temperature
V
DD
Commercial
0C to +70C
3.3V +10%, -5%
Industrial
40C to +85C
3.3V +10%, -5%
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. B
03/10/05
1
2
3
4
5
6
7
8
9
10
11
12
IS61LV51216
ISSI
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST LOADS
Figure 1
Figure 2
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
Z
O
= 50
1.5V
50
OUTPUT
30 pF
Including
jig and
scope
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
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