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Электронный компонент: 61SP6464

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Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. C
01/14/04
IS61SP6464
ISSI
Copyright 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
Fast access time:
117, 100 MHz
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
PentiumTM or linear burst sequence control
using MODE input
Five chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
Power-down control by ZZ input
JEDEC 128-Pin TQFP 14mm x 20mm
package
Single +3.3V power supply
Control pins mode upon power-up:
MODE in interleave burst mode
ZZ in normal operation mode
These control pins can be connected to GND
Q
or V
DDQ
to alter their power-up state
DESCRIPTION
The
ISSI
IS61SP6464 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
secondary cache for the i486TM, PentiumTM, 680X0TM, and
PowerPCTM microprocessors. It is organized as 65,536 words
by 64 bits, fabricated with
ISSI
's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls I/O1-I/O8,
BW2
controls I/O9-I/O16,
BW3
controls I/
O17-I/O24,
BW4
controls I/O25-I/O32,
BW5
controls
I/O33-I/O40,
BW6
controls I/O41-I/O48,
BW7
controls I/O49-I/
O56,
BW8
controls I/O57-I/O64, conditioned by
BWE
being
LOW. A LOW on
GW
input would cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP6464 and controlled by the
ADV
(burst address
advance) input pin.
Asynchronous signals include output enable (
OE
), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates after
the wake-up period. A LOW input, i.e., GND
Q
, on MODE pin
selects LINEAR Burst. A V
DDQ
(or no connect) on MODE pin
selects INTERLEAVED Burst.
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
JANUARY 2004
IS61SP6464
ISSI
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C
01/14/04
BLOCK DIAGRAM
16
BINARY
COUNTER
A15-A0
BW1
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
14
16
ADDRESS
REGISTER
CE
D
CLK
Q
DQ57-DQ64
BYTE WRITE
REGISTERS
D
CLK
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW8
CE
CE2
CE2
CE3
CE3
64K x 64
MEMORY
ARRAY
64
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
64
OE
8
64
OE
DATA[64:1]
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. C
01/14/04
PIN CONFIGURATION
128-Pin TQFP/PQFP
VDDQ
I/O
32
I/O
31
I/O
30
I/O
29
I/O
28
I/O
27
I/O
26
I/O
25
I/O
24
I/O
23
I/O
22
GNDQ
VDDQ
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
GNDQ
VDDQ
I/O
11
I/O
10
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
GNDQ
VDDQ
CE3
CE2
CE3
CE2
GND
VDD
CE
BW8
BW7
BW6
BW5
OE
CLK
BWE
GW
BW4
BW3
GND
VDD
BW2
BW1
ADSC
ADSP
ADV
GNDQ
GNDQ
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
VDDQ
GNDQ
I/O
44
I/O
45
I/O
46
I/O
47
I/O
48
I/O
49
I/O
50
I/O
51
I/O
52
I/O
53
VDDQ
GNDQ
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/O
64
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GNDQ
NC
MODE
A15
A14
A13
VDD
GND
A12
A11
A10
A9
A8
NC
A7
A6
A5
A4
A3
VDD
GND
A2
A1
A0
ZZ
VDDQ
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
PIN DESCRIPTIONS
A0-A15
Address Inputs
CLK
Clock
ADSP
Processor Address Status
ADSC
Controller Address Status
ADV
Burst Address Advance
BW1
-
BW8
Synchronous Byte Write Enable
BWE
Byte Write Enable
GW
Global Write Enable
CE
, CE2,
CE2
,
Synchronous Chip Enable
CE3,
CE3
OE
Output Enable
I/O1-I/O64
Data Input/Output
ZZ
Sleep Mode
MODE
Burst Sequence Mode
V
DD
+3.3V Power Supply
GND
Ground
V
DDQ
Isolated Output Buffer Supply:
+3.3V
NC
No Connect
GND
Q
Isolated Output Buffer Ground
IS61SP6464
ISSI
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C
01/14/04
TRUTH TABLE
ADDRESS
OPERATION
USED
CE3
CE2
CE3
CE3
CE3
CE3
CE3
CE2
CE2
CE2
CE2
CE2
CE
CE
CE
CE
CE
ADSP
ADSP
ADSP
ADSP
ADSP ADSC
ADSC
ADSC
ADSC
ADSC ADV
ADV
ADV
ADV
ADV WRITE
WRITE
WRITE
WRITE
WRITE
OE
OE
OE
OE
OE
CLK
I/O
Deselected, Power-down
None
X
X
X
X
H
X
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
L
X
X
X
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
L
X
X
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
H
X
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
X
H
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
L
X
X
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
L
X
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
H
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
X
H
L
H
L
X
X
X
L-H
High-Z
Read Cycle, Begin Burst
External
H
H
L
L
L
L
X
X
X
L
L-H
Dout
Read Cycle, Begin Burst
External
H
H
L
L
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
L
X
L-H
Din
Read Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
H
L
L-H
Dout
Read Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
H
L
L-H
Dout
Read Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
H
L
L-H
Dout
Read Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
L
X
L-H
Din
Write Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
L
X
L-H
Din
Read Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
H
L
L-H
Dout
Read Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
H
L
L-H
Dout
Read Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
L
X
L-H
Din
Write Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
L
X
L-H
Din
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE
=L means any one or more byte write enable signals (
BW
1-
BW
8) and
BWE
are LOW or
GW
is LOW.
WRITE
=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. C
01/14/04
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
OE
OE
OE
OE
OE
I/O STATUS
Pipelined
Read
L
L
Dout
Pipelined
Read
L
H
High-Z
Write
L
L
High-Z
Write
L
H
Din
Deselect
L
X
High-Z
Sleep
H
X
High-Z
WRITE TRUTH TABLE
Operation
GW
GW
GW
GW
GW
BWE
BWE
BWE
BWE
BWE
BW8
BW8
BW8
BW8
BW8
BW7
BW7
BW7
BW7
BW7
BW6
BW6
BW6
BW6
BW6
BW5
BW5
BW5
BW5
BW5
BW4
BW4
BW4
BW4
BW4
BW3
BW3
BW3
BW3
BW3
BW2
BW2
BW2
BW2
BW2
BW1
BW1
BW1
BW1
BW1
Read
H
H
X
X
X
X
X
X
X
X
Read
H
L
H
H
H
H
H
H
H
H
Write all bytes
H
L
L
L
L
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
X
X
X
X
Write Byte 1
H
L
H
H
H
H
H
H
H
L
Write Byte 2
H
L
H
H
H
H
H
H
L
H
Write Byte 3
H
L
H
H
H
H
H
L
H
H
Write Byte 4
H
L
H
H
H
H
L
H
H
H
Write Byte 5
H
L
H
H
H
L
H
H
H
H
Write Byte 6
H
L
H
H
L
H
H
H
H
H
Write Byte 7
H
L
H
L
H
H
H
H
H
H
Write Byte 8
H
L
L
H
H
H
H
H
H
H
INTERLEAVED BURST ADDRESS TABLE
(MODE = V
DD
or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00