IS62LV12816L
Integrated Silicon Solution, Inc.
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ADVANCE INFORMATION SR002-0C
08/20/98
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ISSI
FEATURES
High-speed access time: 70, 100, and 120 ns
CMOS low power operation
120 mW (typical) operating
6
W (typical) CMOS standby
TTL compatible interface levels
Single 3V
10% V
CC
power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Available in the 44-pin TSOP (Type II) and
48-pin mini BGA
IS62LV12816L
128K x 16 CMOS STATIC RAM
DESCRIPTION
The
ISSI
IS62LV12816L is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE
. The active LOW Write
Enable (
WE
) controls both writing and reading of the memory.
A data byte allows Upper Byte (
UB
) and Lower Byte (
LB
)
access.
The IS62LV12816L is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
ADVANCE INFORMATION
AUGUST 1998
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc.
A0-A16
CE
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
ISSI
IS62LV12816L
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Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
ISSI
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
TRUTH TABLE
I/O PIN
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
LB
LB
LB
LB
LB
UB
UB
UB
UB
UB
I/O0-I/O7
I/O8-I/O15
Vcc Current
Not Selected
X
H
X
X
X
High-Z
High-Z
I
SB
1
, I
SB
2
Output Disabled
H
L
H
X
X
High-Z
High-Z
I
CC
X
L
X
H
H
High-Z
High-Z
Read
H
L
L
L
H
D
OUT
High-Z
I
CC
H
L
L
H
L
High-Z
D
OUT
H
L
L
L
L
D
OUT
D
OUT
Write
L
L
X
L
H
D
IN
High-Z
I
CC
L
L
X
H
L
High-Z
D
IN
L
L
X
L
L
D
IN
D
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
PIN DESCRIPTIONS
A0-A16
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
Vcc
Power
GND
Ground
48-Pin mini BGA
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
N/C
I/O
8
UB
A3
A4
CE
I/O
0
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
GND
I/O
11
NC
A7
I/O
3
Vcc
Vcc
I/O
12
NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11
NC
IS62LV12816L
Integrated Silicon Solution, Inc.
3
ADVANCE INFORMATION SR002-0C
08/20/98
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ISSI
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-70
-100
-120
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating
V
CC
= Max.,
Com.
--
40
--
30
--
20
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
60
--
50
--
40
I
SB
1
TTL Standby Current
V
CC
= Max.,
Com.
--
0.4
--
0.4
--
0.4
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
--
1.0
--
1.0
--
1.0
CE
V
IH
, f = 0
I
SB
2
CMOS Standby
V
CC
= Max.,
Com.
--
15
--
15
--
15
A
Current (CMOS Inputs)
CE
V
CC
0.2V,
Ind.
--
25
--
25
--
25
V
IN
V
CC
0.2V, or
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 1 mA
2.0
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 2.1 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.2
V
V
IL
(1)
Input LOW Voltage
0.2
0.4
V
I
LI
Input Leakage
GND
V
IN
V
CC
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
CC
, Outputs Disabled
1
1
A
Notes:
1. V
IL
(min.) = 2.0V for pulse width less than 10 ns.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to Vcc+0.5
V
T
BIAS
Temperature Under Bias
40 to +85
C
V
CC
Vcc Related to GND
0.3 to +4.0
V
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0
C to +70
C
3.0V
10%
Industrial
40
C to +85
C
3.0V
10%
IS62LV12816L
4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
ISSI
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Times
5 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
AC TEST LOADS
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
3070
100 pF
Including
jig and
scope
3150
OUTPUT
2.8V
Figure 1
3070
5 pF
Including
jig and
scope
3150
OUTPUT
2.8V
Figure 2
IS62LV12816L
Integrated Silicon Solution, Inc.
5
ADVANCE INFORMATION SR002-0C
08/20/98
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ISSI
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-70
-100
-120
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
70
--
100
--
120
--
ns
t
AA
Address Access Time
--
70
--
100
--
120
ns
t
OHA
Output Hold Time
10
--
15
--
15
--
ns
t
ACE
CE
Access Time
--
70
--
100
--
120
ns
t
DOE
OE
Access Time
--
35
--
50
--
60
ns
t
HZOE
(2)
OE
to High-Z Output
--
25
--
30
0
40
ns
t
LZOE
(2)
OE
to Low-Z Output
5
--
5
--
5
--
ns
t
HZCE
(2)
CE
to High-Z Output
0
25
0
30
0
40
ns
t
LZCE
(2)
CE
to Low-Z Output
10
--
10
--
10
--
ns
t
BA
LB
,
UB
Access Time
--
35
--
50
--
60
ns
t
HZB
LB
,
UB
to High-Z Output
0
25
0
35
0
50
ns
t
LZB
LB
,
UB
to Low-Z Output
0
--
0
--
0
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4 to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured
500 mV from steady-state voltage. Not 100% tested.
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (
CE
=
OE
= V
IL
,
UB
or
LB
= V
IL
)
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