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Электронный компонент: 65C256

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Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. A
03/24/04
IS65C256
ISSI
Copyright 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
FUNCTIONAL BLOCK DIAGRAM
32K x 8 LOW POWER CMOS
STATIC RAM
FEATURES
High-speed access time: 20 ns
Low active power: 200 mW (typical)
Low standby power:
250 W (typical) CMOS standby
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V power supply
Temperature Offerings:
Option A1: 40
o
C to +85
o
C
Option A2: 40
o
C to +105
o
C
Option A3: 40
o
C to +125
o
C
MARCH 2004
DESCRIPTION
The
ISSI IS65C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using
ISSI's high-
performance, low power CMOS technology.
When CS is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 W (typical) at CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Select (CS) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS65C256 is Packaged in the JEDEC Standard 28-Pin
SOP and 28-Pin TSOP (Type I).
A0-A14
CS
OE
WE
32K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
03/24/04
IS65C256
ISSI
PIN CONFIGURATION
32-Pin SOP
PIN CONFIGURATION
32-Pin TSOP (Type 1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
V
DD
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
V
DD
A14
A12
A7
A6
A5
A4
A3
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN DESCRIPTIONS
A0-A14
Address Inputs
CS
Chip Select Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
V
DD
Power
GND
Ground
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CS
CS
CS
CS
CS
OE
OE
OE
OE
OE
I/O Operation
V
DD
Current
Not Selected
X
H
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
Output Disabled H
L
H
High-Z
I
CC
1
, I
CC
2
Read
H
L
L
D
OUT
I
CC
1
, I
CC
2
Write
L
L
X
D
IN
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
55 to +125
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
0.5
W
I
OUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. A
03/24/04
IS65C256
ISSI
OPERATING RANGE
Range
Ambient Temperature
V
DD
A1
40C to +85C
5V 10%
A2
40C to +105C
5V 10%
A3
40C to +125C
5V 10%
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
= 1.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 2.1 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
DD
+ 0.5
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
DD
10
10
A
I
LO
Output Leakage
GND
V
OUT
V
DD
,
10
10
A
Outputs Disabled
Note:
1. V
IL
= 3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-20 ns
Symbol
Parameter
Test Conditions
Min.
typ
(2)
Max.
Unit
I
CC
1
V
DD
Operating
V
DD
= Max.,
CS
= V
IL
A1
--
40
mA
Supply Current
I
OUT
= 0 mA, f = 0
A2
--
50
A3
--
60
I
CC
2
V
DD
Dynamic Operating
V
DD
= Max.,
CS
= V
IL
A1
--
25
95
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
A2
--
25
105
A3
--
25
115
I
SB
1
TTL Standby Current
V
DD
= Max.,
A1
--
5
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
A2
--
10
CS
= V
IH
, f = 0
A3
--
10
I
SB
2
CMOS Standby
V
DD
= Max.,
A1
--
0.5
mA
Current (CMOS Inputs)
CS
V
DD
0.2V,
A2
--
1.0
V
IN
V
DD
0.2V, or
A3
--
1.5
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
= 5V, T
A
= 25
o
C, t
AA
= 70 ns, and not 100% tested.
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
03/24/04
IS65C256
ISSI
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
8
pF
C
OUT
Output Capacitance
V
OUT
= 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, V
DD
= 5.0V.
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-20 ns
Symbol
Parameter
Min.
Max.
Unit
t
RC
Read Cycle Time
20
--
ns
t
AA
Address Access Time
--
20
ns
t
OHA
Output Hold Time
3
--
ns
t
ACS
CS
Access Time
--
20
ns
t
DOE
OE
Access Time
--
8
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
ns
t
HZOE
(2)
OE
to High-Z Output
0
9
ns
t
LZCS
(2)
CS
to Low-Z Output
3
--
ns
t
HZCS
(2)
CS
to High-Z Output
0
9
ns
t
PU
(3)
CS
to Power-Up
0
--
ns
t
PD
(3)
CS
to Power-Down
--
18
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Conditions
Options
Min.
typ
(1)
Max.
Units
V
DR
V
DD
for retention of data
2.0
--
V
I
DR
1
Data retention current
V
DR
= 3.0V
A1
--
50
150
A
I
DR
2
Data retention current
V
DR
= 3.0V
A2
--
50
300
A
I
DR
3
Data retention current
V
DR
= 3.0V
A3
--
50
500
A
Note:
2. Typical values are measured at V
DD
= 3V, T
A
= 25
o
C, and not 100% tested.
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. A
03/24/04
IS65C256
ISSI
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
AC TEST LOADS
480
100 pF
Including
jig and
scope
255
OUTPUT
5V
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
Figure 1.
Figure 2.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Levels
Output Load
See Figures 1 and 2