Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. B
04/08/05
IS41LV44002A
ISSI
Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
Extended Data-Out (EDO) Page Mode access cycle
TTL compatible inputs and outputs
Refresh Interval:
2,048 cycles/32 ms
Refresh Mode:
RAS
-Only,
CAS
-before-
RAS
(CBR), and Hidden
Single power supply: 3.3V 10%
Byte Write and Byte Read operation via two
CAS
Industrial temperature range -40C to +85C
Lead-free available
DESCRIPTION
The
ISSI
IS41LV44002A is 4,194,304 x 4-bit high-perfor-
mance CMOS Dynamic Random Access Memory. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 2,048 random ac-
cesses within a single row with access cycle time as short
as 20 ns per 4-bit word.
These features make the IS41LV44002A ideally suited for
high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral
applications.
The IS41LV44002A is packaged in a 24-pin 300-mil SOJ
with JEDEC standard pinouts.
4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
APRIL 2005
KEY TIMING PARAMETERS
Parameter
-50
-60
Unit
RAS
Access Time (t
RAC
)
50
60
ns
CAS
Access Time (t
CAC
)
13
15
ns
Column Address Access Time (t
AA
) 25
30
ns
EDO Page Mode Cycle Time (t
PC
)
20
25
ns
Read/Write Cycle Time (t
RC
)
84
104
ns
PRODUCT SERIES OVERVIEW
Part No.
Refresh
Voltage
IS41LV44002A
2K
3.3V 10%
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
I/O0
I/O1
WE
RAS
NC
A10
A0
A1
A2
A3
VDD
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10
Address Inputs
I/O0-3
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
CAS
Column Address Strobe
V
DD
Power
GND
Ground
NC
No Connection
PIN CONFIGURATION: 24-pin SOJ
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
04/08/05
IS41LV44002A
ISSI
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CAS
WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
4,194,304 x 4
ROW DECODER
DATA I/O BUFFERS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O3
RAS
RAS
A0-A10
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
TRUTH TABLE
Function
RAS
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CAS
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
Address t
R
/t
C
I/O
Standby
H
H
X
X
X
High-Z
Read
L
L
H
L
ROW/COL
D
OUT
Write: Word (Early Write)
L
L
L
X
ROW/COL
D
IN
Read-Write
L
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
EDO Page-Mode Read
1st Cycle:
L
H
L
H
L
ROW/COL
D
OUT
2nd Cycle:
L
H
L
H
L
NA/COL
D
OUT
EDO Page-Mode Write
1st Cycle:
L
H
L
L
X
ROW/COL
D
IN
2nd Cycle:
L
H
L
L
X
NA/COL
D
IN
EDO Page-Mode
1st Cycle:
L
H
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
Read-Write
2nd Cycle:
L
H
L
H
L
L
H
NA/COL
D
OUT
, D
IN
Hidden Refresh
Read
L
H
L
L
H
L
ROW/COL
D
OUT
Write
(1)
L
H
L
L
L
X
ROW/COL
D
OUT
RAS
-Only Refresh
L
H
X
X
ROW/NA
High-Z
CBR Refresh
H
L
L
X
X
X
High-Z
Note:
1. EARLY WRITE only.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. B
04/08/05
IS41LV44002A
ISSI
Functional Description
The IS41LV44002A is a CMOS DRAMs optimized for
high-speed bandwidth, low power applications. During
READ or WRITE cycles, each bit is uniquely addressed
through the 11 address bits. These are entered 11 bits
(A0-A10) at a time for the 2K refresh device. The row
address is latched by the Row Address Strobe (
RAS
). The
column address is latched by the Column Address Strobe
(
CAS
).
RAS
is used to latch the first nine bits and
CAS
is
used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bringing
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time
specified by t
AR
. Data Out becomes valid only when t
RAC
,
t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access
time is dependent on the timing relationships between
these parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE
, whichever
occurs last.
Auto Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
, while
holding
CAS
LOW. In
CAS
-before-
RAS
refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the V
DD
supply, an initial pause of 200
s is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
DD
or be held at a valid V
IH
to avoid current surges.
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
04/08/05
IS41LV44002A
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameters
Rating
Unit
V
T
Voltage on Any Pin Relative to GND
3.3V
0.5 to +4.6
V
V
DD
Supply Voltage
3.3V
0.5 to +4.6
V
I
OUT
Output Current
50
mA
P
D
Power Dissipation
1
W
T
A
Commercial Operation Temperature
0 to +70
C
Industrial Operation Temperature
-40 to +85
T
STG
Storage Temperature
55 to +125
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
3.3V
3.0
3.3
3.6
V
V
IH
Input High Voltage
3.3V
2.0
--
V
DD
+ 0.3
V
V
IL
Input Low Voltage
3.3V
0.3
--
0.8
V
T
A
Commercial Ambient Temperature
0
--
+70
C
Industrial Ambient Temperature
-40
--
+85
C
CAPACITANCE
(1,2)
Symbol
Parameter
Max.
Unit
C
IN
1
Input Capacitance: A0-A10
5
pF
C
IN
2
Input Capacitance:
RAS
,
CAS
,
WE
,
OE
7
pF
C
IO
Data Input/Output Capacitance: I/O0-I/O3
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. B
04/08/05
IS41LV44002A
ISSI
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
V
DD
Speed
Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V
V
IN
V
DD
5
5
A
Other inputs not under test = 0V
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
5
5
A
0V
V
OUT
V
DD
V
OH
Output High Voltage Level
I
OH
= 2.0 mA, V
DD
= 3.3V
2.4
--
V
V
OL
Output Low Voltage Level
I
OL
= 2 mA, V
DD
= 3.3V
--
0.4
V
I
CC
1
Standby Current: TTL
RAS
,
CAS
V
IH
Commercial
3.3V
--
0.5
mA
Industrial
3.3V
--
2
I
CC
2
Standby Current: CMOS
RAS
,
CAS
V
DD
0.2V
3.3V
--
0.5
mA
I
CC
3
Operating Current:
RAS
,
CAS
,
-50
--
120
mA
Random Read/Write
(2,3,4)
Address Cycling, t
RC
= t
RC
(min.)
-60
--
110
Average Power Supply Current
I
CC
4
Operating Current:
RAS
= V
IL
,
CAS
,
-50
--
90
mA
EDO Page Mode
(2,3,4)
Cycling t
PC
= t
PC
(min.)
-60
--
80
Average Power Supply Current
I
CC
5
Refresh Current:
RAS
Cycling,
CAS
V
IH
-50
--
120
mA
RAS
-Only
(2,3)
t
RC
= t
RC
(min.)
-60
--
110
Average Power Supply Current
I
CC
6
Refresh Current:
RAS
,
CAS
Cycling
-50
--
120
mA
CBR
(2,3,5)
t
RC
= t
RC
(min.)
-60
--
110
Average Power Supply Current
Notes:
1. An initial pause of 200 s is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
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