Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. 00D
11/21/05
IS42S32200C1
ISSI
Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
Clock frequency: 183, 166, 143 MHz
Fully synchronous; all signals referenced to a
positive clock edge
Internal bank for hiding row access/precharge
Single 3.3V power supply
LVTTL interface
Programmable burst length:
(1, 2, 4, 8, full page)
Programmable burst sequence:
Sequential/Interleave
Self refresh modes
4096 refresh cycles every 64 ms
Random column address every clock cycle
Programmable
CAS latency (2, 3 clocks)
Burst read/write and burst read/single write
operations capability
Burst termination by burst stop and precharge
command
Available in Industrial temperature grade
Available in 400-mil 86-pin TSOP II and 90-ball
BGA
Available in Lead free
OVERVIEW
ISSI
's 64Mb Synchronous DRAM IS42S32200C1 is
organized as 524,288 bits x 32-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-
speed data transfer using pipeline architecture. All inputs
and outputs signals refer to the rising edge of the clock
input.
512K Bits x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
PRELIMINARY INFORMATION
NOVEMBER 2005
KEY TIMING PARAMETERS
Parameter
-55
-6
-7
Unit
Clk Cycle Time
CAS Latency = 3
5.5
6
7
ns
CAS Latency = 2
10
10
10
ns
Clk Frequency
CAS Latency = 3
183
166
143
Mhz
CAS Latency = 2
100
100
100
Mhz
Access Time from Clock
CAS Latency = 3
5
5.5
5.5
ns
CAS Latency = 2
7.5
7.5
8
ns
IS42S32200C1
ISSI
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00D
11/21/05
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 2,048
rows by 256 columns by 32 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE
function enabled. Precharge one bank while accessing one
of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A10 select the row). The READ or
WRITE commands in conjunction with address bits reg-
istered are used to select the starting column location for
the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
A10
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MUL
TIPLEXER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
DATA IN
BUFFER
DATA OUT
BUFFER
DQM0-3
DQ 0-31
V
DD
/V
DDQ
GND/GNDQ
11
11
11
11
32
32
32
32
256
(x 32)
2048
2048
2048
R
O
W DECODER
2048
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROW
ADDRESS
BUFFER
IS42S32200C1
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. 00D
11/21/05
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
PIN DESCRIPTIONS
A0-A10
Row Address Input
A0-A7
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ31
Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
WE
Write Enable
DQM0-DQM3
x32 Input/Output Mask
V
DD
Power
Vss
Ground
V
DDQ
Power Supply for I/O Pin
Vss
Q
Ground for I/O Pin
NC
No Connection
IS42S32200C1
ISSI
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. 00D
11/21/05
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
VDDQ
VDD
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS
WE
DQ7
DQ5
DQ3
VSSQ
DQ0
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
NC
RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
PIN DESCRIPTIONS
A0-A10
Row Address Input
A0-A7
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ31
Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
WE
Write Enable
DQM0-DQM3
x32 Input/Output Mask
V
DD
Power
Vss
Ground
V
DDQ
Power Supply for I/O Pin
Vss
Q
Ground for I/O Pin
NC
No Connection
IS42S32200C1
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. 00D
11/21/05
PIN FUNCTIONS
Symbol
Pin No. (TSOP)
Type
Function (In Detail)
A0-A10
25 to 27
Input Pin
Address Inputs: A0-A10 are sampled during the ACTIVE
60 to 66
command (row-address A0-A10) and READ/WRITE command (A0-A7
24
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
BA0, BA1
22,23
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS
18
Input Pin
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE
67
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.
CLK
68
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
CS
20
Input Pin
The
CS input determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when
CS is HIGH.
DQ0 to
2, 4, 5, 7, 8, 10,11,13
DQ Pin
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
DQ31
74,76,77,79,80,82,83,85
using the DQM0-DQM3 pins
45,47,48,50,51,53,54,56
31,33,34,36,37,39,40,42
DQM0
16,28,59,71
Input Pin
DQMx control thel ower and upper bytes of the DQ buffers. In read mode,
DQM3
the output buffers are place in a High-Z state. During a WRITE cycle the input data is
masked. When DQMx is sampled HIGH and is an input mask signal for write accesses
and an output enable signal for read accesses. DQ0 through DQ7 are controlled by
DQM0. DQ8 throughDQ15 are controlled by DQM1. DQ16 through DQ23 are
controlled by DQM2. DQ24 through DQ31 are controlled by DQM3.
RAS
19
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE
17
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
V
DDQ
3,9,35,41,49,55,75,81
Supply Pin
V
DDQ
is the output buffer power supply.
V
DD
1,15,29,43
Supply Pin
V
DD
is the device internal power supply.
GND
Q
6,12,32,38,46,52,78,84
Supply Pin
GND
Q
is the output buffer ground.
GND
44,58,72,86
Supply Pin
GND is the device internal ground.
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