Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

2K-BIT/4K-BIT SPI SERIAL
ELECTRICALLY ERASABLE PROM

FEATURES

· Serial Peripheral Interface (SPI) Compatible

-- Supports SPI Modes 0 (0,0) and 3 (1,1)

· Low-voltage Operation

-- Vcc = 1.8V to 5.5V

· Low power CMOS

-- Active current less than 3.0 mA (2.5V)
-- Standby current less than 1 µA (2.5V)

· Block Write Protection

-- Protect 1/4, 1/2, or Entire Array

· 16 byte page write mode

-- Partial page writes allowed

· 10 MHz Clock Rate (5V)
· Self timed write cycles

-- 5 ms max. @ 2.5V

· High-reliability

-- Endurance: 1 million cycles per byte
-- Data retention: 100 years

· 8-pin PDIP, 8-pin SOIC, and 8-pin TSSOP packages

are available

· Lead-free available

Preliminary Information

January 2006

The IS25C02 and IS25C04 are electrically erasable
PROM devices that use the Serial Peripheral Interface
(SPI) for communications. The IS25C02 is 2Kbit
(256x 8) and the IS25C04 is 4Kbit (512x 8). The
IS25C02/04 EEPROMs are offered in a wide operating
voltage range of 1.8V to 5.5V to be compatible with
most application voltages. ISSI designed the IS25C02/
04 to be an efficient SPI EEPROM solution. The
devices are packaged in 8-pin PDIP, 8-pin SOIC, and 8-
pin TSSOP.

The functional features of the IS25C02/04 allow them to
be among the most advanced serial non-volatile memo-
ries available. Each device has a Chip-Select (

CS) pin,

and a 3-wire interface of Serial Data In (SI), Serial Data
Out (SO), and Serial Clock (SCK). While the 3-wire
interface of the IS25C02/04 provides for high-speed
access, a

HOLD pin allows the memories to ignore the

interface in a suspended state; later the

HOLD pin re-

activates communication without re-initializing the serial
sequence. A Status Register facilitates a flexible write
protection mechanism, and a device-ready bit (

RDY).

DESCRIPTION

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

Write Protect (

WP): The purpose of this input signal is

to initiate Hardware Write Protection mode. This mode
prevents the 256/512 byte array or the Status Register
from being altered. To cause Hardware Write Protection,
WP must be Low. WP may be hardwired to Vcc or GND.

HOLD (

HOLD

HOLD): This input signal is used to suspend the

device in the middle of a serial sequence and temporarily
ignore further communication on the bus (SI, SO, SCK).
Together with Chip Select, the

HOLD signal allows

multiple slaves to share the bus.

The

HOLD signal

transitions must occur only when SCK is Low, and be
held stable during SCK transitions. (See Figure 8 for
Hold timing) To disable this feature,

HOLD may be

hardwired to Vcc.

PIN DESCRIPTIONS

Chip Select

SCK

Serial Data Clock

Serial Data Input

Serial Data Output

GND

Ground

Power

Write Protect

HOLD

Suspends Serial Input

PIN DESCRIPTIONS

Serial Clock (SCK): This timing signal provides syn-
chronization between the microcontroller and IS25C02/
04. Op-Codes, byte addresses, and data are latched on
SI with a rising edge of the SCK. Data on SO is re-
freshed on the falling edge of SCK for SPI modes (0,0)
and (1,1).

Serial Data Input (SI): This is the input pin for all data
that the IS25C02/04 is required to receive.

Serial Data Output (SO): This is the output pin for all
data transmitted from the IS25C02/04.

PIN CONFIGURATION

8-Pin DIP, SOIC, and TSSOP

Chip Select (

CS): The CS pin activates the device.

Upon power-up,

CS should follow Vcc. When the device

is to be enabled for instruction input, the signal requires
a High-to-Low transition. While

CS is stable Low, the

master and slave will communicate via SCK, SI, and SO
signals. Upon completion of communication,

CS must

be driven High. At this moment, the slave device may
start its internal write cycle. When

CS is high, the

device enters a power-saving standby mode, unless an
internal write operation is underway. During this mode,
the SO pin becomes high impedance.

GND

VCC
HOLD
SCK

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

SERIAL INTERFACE DESCRIPTION

MASTER: The device that provides a clock signal.

SLAVE: The IS25C02/04 is a slave because the clock
signal is an input.

TRANSMITTER/RECEIVER: The IS25C02/04 has both
data input (SI) and data output (SO).

MSB: The most significant bit. It is always the first bit
transmitted or received.

OP-CODE: The first byte transmitted to the slave
following CS transition to LOW. If the OP-CODE is a
valid member of the IS25C02/04 instruction set (Table 3),
then it is decoded appropriately. If the OP-CODE is not
valid, and the SO pin remains in high impedance.

BLOCK DIAGRAM

STATUS

256 x 8/512 x 8

MEMORY ARRAY

HOLD

CLOCK

OUTPUT

BUFFER

SCK

DATA

MODE

DECODE

LOGIC

GND

VCC

ADDRESS

DECODER

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

STATUS REGISTER

Table 1. Status Register Format

Bit 7

Bit 6 Bit 5 Bit 4

Bit 3 Bit 2

Bit1 Bit 0

BP1

BP0

WEN

RDY

The status register contains 8-bits for write protection
control and write status. (See Table 1). It is the only
region of memory other than the main array that is
accessible by the user.

The Status Register is Read-Only if either: a) Hardware
Write Protection is enabled or b) WEN is set to 0. If
neither is true, it can be modified by a valid instruction.

Ready (

RDY

RDY), Bit 0: When RDY = 1, it indicates that

the device is busy with a write cycle.

RDY = 0 indi-

cates that the device is ready for an instruction. If

RDY

= 1, the only command that will be handled by the
device is Read Status Register.

Don't Care, Bits 4-7: Each of these bits can receive
either 0 or 1, but values will not be retained. When
these bits are read from the register, they are always 0.

Notes:
1. X = Don't care bit.

2. During internal write cycles, bits 0 to 7 are temporarily 1's.

Block Protect (BP1, BP0), Bits 2-3: Together, these
bits represent one of four block protection configurations
implemented for the memory array. (See Table 2 for
details.)
BP0 and BP1 are non-volatile cells similar to regular
array cells, and factory programmed to 0. The block of
memory defined by these bits is always protected,
regardless of the setting of

WP or WEN.

Table 2. Block Protection

Status

Register

Bits

Array Addresses Protected

Level

BP1

BP0

IS25C02

IS25C04

None

1(1/4)

C0h

180h

-FFh

-1FFh

2(1/2)

80h

100h

-FFh

-1FFh

3(All)

00h

000h

-FFh

-1FFh

Write Enable (WEN), Bit 1: This bit represents the
status of device write protection. If WEN = 0, the Status
Register and the entire array is protected from modifica-
tion, regardless of the setting of

WP pin or block protec-

tion. The only way to set WEN to 1 is via the Write
Enable command (WREN). WEN is reset to 0 upon
power-up, successful completion of Write, WRDI,
WRSR, or

WP being Low.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

WRITE ENABLE (WREN)
When Vcc is initially applied, the device powers up with
both status register and entire array in a write-disabled
state. Upon completion of Write Disable (WRDI), Write
Status Register (WRSR), or Write Data to Array
(WRITE), the device resets the WEN bit in the Status
Register to 0. Prior to any data modification, a WREN
instruction is necessary to set WEN to 1. (See Figure 2
for timing).

WRITE DISABLE (WRDI)
The device can be completely protected from modifica-
tion by resetting WEN to 0 through the WRDI instruc-
tion. (See Figure 3 for timing).

READ STATUS REGISTER (RDSR)

The Read Status instruction indicates the status of the
Block Protection setting (see Table 2), the Write Enable
state, and the

RDY status. RDSR is the only instruc-

tion accepted when a write cycle is underway. It is
recommended that the status of

RDY be checked,

especially prior to an attempted modification of data.
The 8 bits of the Status Register can be repeatedly
output on SO after the initial Op-code. (See Figure 4 for
timing).

Table 3. Instruction Set

Name

Op-code

Operation

Address

Data(SI)

Data (SO)

WREN

0000 X110

Set Write Enable Latch

WRDI

0000 X100

Reset Write Enable Latch

RDSR

0000 X101

Read Status Register

D7-D0,...

WRSR

0000 X001

Write Status Register

D7-D0

READ

0000 A8011

Read Data from Array

A7-A0

D7-D0,...

WRITE 0000 A8010

Write Data to Array

A7-A0

D7-D0,...

DEVICE OPERATION

The operations of the IS25C02/04 are controlled by a set of instructions that are clocked-in serially SI pin. (See Table
3). To begin an instruction, the chip select (

CS) should be dropped Low. Subsequently, each Low-to-High transition of

the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to input
an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of SK. All
bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-to-High transition
of SK,

CS should be raised High to end the transaction. The device then would enter Standby Mode if no internal

programming were underway.

1. X = Don't care bit. For consistency, it is best to use "0".
2. Some address bits are don't care. See Table 5.
3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no
affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the
array or Status Register to be ignored.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

Table 5. Address Key

Name

IS25C02

IS25C04

Don't

Care Bits

WRITE STATUS REGISTER (WRSR)

This instruction lets the user choose a Block Protection
setting. The values of the other data bits incorporated
into WRSR can be 0 or 1, and are not stored in the
Status Register. WRSR will be ignored unless both the
following are true: a) WEN = 1, due to a prior WREN
instruction; and b) Hardware Write Protection is not
enabled. (See Table 4 for details). Except for the

RDY

status, the values in the Status Register remain un-
changed until the moment when the write cycle is
complete and the register is updated. Once successfully
completed, WEN is reset for complete chip write protec-
tion. (See Figure 5 for timing).

READ DATA (READ)
This instruction begins with the op-code and the 8-bit
address, and causes the selected data byte to be
shifted out on SO. Following this first data byte, addi-
tional sequential bytes are output. If the data byte in the
highest address is output, the address rolls-over to the
lowest address in the array, and the output could loop
indefinitely. At any time, a rising

CS signal completes

the operation. (See Figure 6 for timing).

WRITE DATA (WRITE)
The WRITE instruction begins with the op-code, the 8-bit
address of the first byte to be modified, and the first data
byte. Additional data bytes may be written sequentially
to the array after the first byte. Each WRITE instruction
can affect the contents of a 16 byte page, but no more.
The page begins at address XXXX 0000, and ends with
XXXX 1111. If the last byte of the page is input, the
address rolls over to the beginning of the same page.
More than 16 data bytes can be input during the same
instruction, but upon a completed write cycle, a page
would only contain the last 16 bytes.

The region of the array defined within Block Protection
cannot be modified as long as that block configuration is
selected. The region of the array outside the Block
Protection can only be modified if Write Enable (WEN) is
set to 1. Therefore, it may be necessary that a WREN
instruction occur prior to WRITE. In addition, if Hardware
Write Protection is enabled, the memory array cannot be
modified. Once Write is successfully completed, WEN
is reset for complete chip write protection. (See Figure 7
for timing).

Table 4. Write Protection

Hardware Write

WEN

Inside Block

Outside Block

Status Register

Protection

Enabled

Read-only

Not Enabled

Read-only

Not Enabled

Read-only

Unprotected

Note: X = Don't care bit.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

Supply Voltage

-0.5 to + 6.5

Voltage on Any Pin

0.5 to Vcc + 0.5

BIAS

Temperature Under Bias

55 to +125

°C

STG

Storage Temperature

65 to +150

°C

OUT

Output Current

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions outside those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

OPERATING RANGE (IS25C04-2 and IS25C02-2)

Range

Ambient Temperature

Industrial

40°C to +85°C

1.8V to 5.5V

Note: ISSI offers Industrial grade for Commercial applications (0

C to +70

C).

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

Notes:
1. Tested initially and after any design or process changes that may affect these parameters and not 100%

tested.

2. Test conditions: T

= 25°C, f = 1 MHz, Vcc = 5.0V.

OPERATING RANGE (IS25C04-3 and IS25C02-3)

Range

Ambient Temperature

Automotive

40°C to +125°C

2.5V to 5.5V

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

DC ELECTRICAL CHARACTERISTICS

= 40°C to +85°C for Industrial, T

= 40°C to +125°C for Automotive.

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output LOW Voltage

= 5V, I

= 2 mA

0.4

Output LOW Voltage

= 2.5V, I

= 1.5 mA

0.4

Output LOW Voltage

= 1.8V, I

= 0.15 mA

0.2

Output HIGH Voltage

= 5V, I

= -2 mA

0.8

Output HIGH Voltage

= 2.5V, I

= -0.4mA

0.8

Output HIGH Voltage

= 1.8V, I

= -0.1mA

0.8

Input HIGH Voltage

0.7

+ 1

Input LOW Voltage

-0.3

0.3

Input Leakage Current

= 0V

-2

µA

Output Leakage Current

OUT

= 0V

CS = V

-2

µA

POWER SUPPLY CHARACTERISTICS

= 40°C to +85°C for Industrial.

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Vcc Operating Current

Read/Write at 10 MHz (Vcc = 5V)

5.0

Vcc Operating Current

Read/Write at 5 MHz (Vcc = 2.5V)

3.0

Vcc Operating Current

Read/Write at 2 MHz (Vcc = 1.8V)

1.0

Standby Current

Vcc = 5.0V, V

= V

or GND

µA

CS = Vcc

Standby Current

Vcc = 2.5V, V

= V

or GND

µA

CS = Vcc

Standby Current

Vcc = 1.8V, V

= V

or GND

0.5

µA

CS = Vcc

POWER SUPPLY CHARACTERISTICS

= 40°C to +125°C for Automotive.

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Vcc Operating Current

Read/Write at 5 MHz (Vcc = 5V)

4.0

Vcc Operating Current

Read/Write at 5 MHz (Vcc = 2.5V)

3.0

Standby Current

Vcc = 5.0V, V

= V

or GND

5.0

µA

CS = Vcc

Standby Current

Vcc =2.5V, V

= V

or GND

2.0

µA

CS = Vcc

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

AC Characteristics

= 40°C to +85°C for Industrial.

1.8V

Vcc < 2.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Units

SCK

SCK Clock Frequency

MHz

Input Rise Time

µs

Input Fall Time

µs

SCK High Time

200

SCK Low Time

200

CS High Time

200

100

CSS

CS Setup Time

200

CSH

CS Hold Time

200

Data In Setup Time

Data In Hold Time

Hold Setup Time

100

Hold Hold Time

100

Output Valid

150

Output Hold Time

Hold to Output Low Z

100

Hold to Output High Z

250

100

DIS

Output Disable Time

250

100

Write Cycle Time

= 100pF

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

AC Characteristics

= 40°C to +125°C for Automotive.

2.5V

Vcc < 4.5V

4.5V

Vcc 5.5V

Symbol

Parameter

Min

Max

Min

Max

Units

SCK

SCK Clock Frequency

MHz

Input Rise Time

µs

Input Fall Time

µs

SCK High Time

SCK Low Time

CS High Time

100

CSS

CS Setup Time

CSH

CS Hold Time

Data In Setup Time

Data In Hold Time

Hold Setup Time

Hold Hold Time

Output Valid

Output Hold Time

Hold to Output Low Z

Hold to Output High Z

100

DIS

Output Disable Time

100

Write Cycle Time

= 100pF

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Preliminary Information

Rev. 00F

12/22/05

IS25C02
IS25C04

ISSI

ORDERING INFORMATION

Industrial Range: 40°C to +85°C

Voltage

Range

Part Number

Package

1.8V

IS25C02-2PI

300-mil Plastic DIP

to 5.5V

IS25C02-2GI

Small Outline (JEDEC STD)

IS25C02-2ZI

169-mil TSSOP

1.8V

IS25C04-2PI

300-mil Plastic DIP

to 5.5V

IS25C04-2GI

Small Outline (JEDEC STD)

IS25C04-2ZI

169-mil TSSOP

Automotive Range: 40°C to +125°C, Lead-free

Voltage

Range

Part Number

Package

2.5V

IS25C02-3PLA3

300-mil Plastic DIP

to 5.5V

IS25C02-3GLA3

Small Outline (JEDEC STD)

IS25C02-3ZLA3

169-mil TSSOP

2.5V

IS25C04-3PLA3

300-mil Plastic DIP

to 5.5V

IS25C04-3GLA3

Small Outline (JEDEC STD)

IS25C04-3ZLA3

169-mil TSSOP

Industrial Range: -40°C to +85°C, Lead-free

Voltage

Range

Part Number

Package

1.8V

IS25C02-2PLI

300-mil Plastic DIP

to 5.5V

IS25C02-2GLI

Small Outline (JEDEC STD)

IS25C02-2ZLI

169-mil TSSOP

1.8V

IS25C04-2PLI

300-mil Plastic DIP

to 5.5V

IS25C04-2GLI

Small Outline (JEDEC STD)

IS25C04-2ZLI

169-mil TSSOP

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. D
02/14/03

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

300-mil Plastic DIP
Package Code: N,P

SEATING PLANE

FOR

32-PIN ONLY

MILLIMETERS

INCHES

Sym. Min.

Max.

Min.

Max.

N0.
Leads

3.68

4.57

0.145

0.180

0.38

0.015

0.36

0.56

0.014

0.022

1.14

1.52

0.045

0.060

0.81

1.17

0.032

0.046

0.20

0.33

0.008

0.013

9.12

9.53

0.359

0.375

7.62

8.26

0.300

0.325

6.20

6.60

0.244

0.260

8.13

9.65

0.320

0.380

2.54 BSC

0.100 BSC

3.18

0.125

0.64

0.762

0.025

0.030

Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and

should

be measured from the bottom of the package

4. Formed leads shall be planar with respect to one another within 0.004

inches at the seating plane.

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. C
10/03/01

150-mil Plastic SOP
Package Code: G, GR

SEATING PLANE

Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and

should be

measured from the bottom of the package

4. Formed leads shall be planar with respect to one another within 0.004 inches at the

seating plane.

150-mil Plastic SOP (G, GR)

Symbol

Min

Max

Min

Max

Ref. Std.

Inches

No. Leads

0.068

1.73

0.004

0.009

0.1

0.23

0.013

0.020

0.33

0.51

0.007

0.010

0.18

0.25

0.189

0.197

4.8

0.150

0.157

3.81

3.99

0.228

0.245

5.79

6.22

0.050 BSC

1.27 BSC

0.020

0.035

0.51

0.89

Integrated Silicon Solution, Inc.

PACKAGING INFORMATION

ISSI

Thin Shrink Small Outline TSSOP
Package Code: Z (8 pin, 14 pin)

Rev B 02/01/02

TSSOP (Z)

Ref. Std.

JEDEC MO-153

No. Leads

Millimeters

Inches

Symbol Min

Max

Min

Max

1.20

0.047

0.05

0.15

0.002 0.006

0.80

1.05

0.032 0.041

0.19

0.30

0.007 0.012

0.09

0.20

0.004 0.008

2.90

3.10

0.114 0.122

4.30

4.50

0.169 0.177

6.40 BSC

0.252 BSC

0.65 BSC

0.026 BSC

0.45

0.75

0.018 0.030

8°

TSSOP (Z)

Ref. Std.

JEDEC MO-153

No. Leads

Millimeters

Inches

Symbol Min

Max

Min

Max

1.20

0.047

0.05

0.15

0.002

0.006

0.80

1.05

0.031

0.041

0.19

0.30

0.007

0.012

0.09

0.20

0.0035 0.008

4.90

5.10

0.193

0.201

4.30

4.50

0.170

0.177

6.40 BSC

0.252 BSC

0.65 BSC

0.026 BSC

0.45

0.75

0.0177 0.0295

8°

N/2

SSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may
appear in this publication. © Copyright 2002, Integrated Silicon Solution, Inc.

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