Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D
06/24/01

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

IS41C4400

IS41LV4400

ERIES

ISSI

FEATURES

Extended Data-Out (EDO) Page Mode access cycle

TTL compatible inputs and outputs

Refresh Interval:
2,048 cycles/32 ms
4,096 cycles/64 ms

Refresh Mode:

RAS-Only,

CAS-before-RAS (CBR), and Hidden

Single power supply:
5V±10% or 3.3V ± 10%

Byte Write and Byte Read operation via two

CAS

Industrial temperature range -40°C to 85°C

DESCRIPTION

The

ISSI

4400 Series is a 4,194,304 x 4-bit high-performance

CMOS Dynamic Random Access Memory. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 2,048 or 4096
random accesses within a single row with access cycle
time as short as 20 ns per 4-bit word.

These features make the 4400 Series ideally suited for
high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.

The 4400 Series is packaged in a 24-pin 300-mil SOJ with
JEDEC standard pinouts.

4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE

JUNE, 2001

KEY TIMING PARAMETERS

Parameter

-50

-60

Unit

RAS Access Time (t

RAC

)

CAS Access Time (t

CAC

)

Column Address Access Time (t

)

EDO Page Mode Cycle Time (t

)

Read/Write Cycle Time (t

)

104

PRODUCT SERIES OVERVIEW

Part No.

Refresh

Voltage

IS41C44002

5V ± 10%

IS41C44004

5V ± 10%

IS41LV44002

3.3V ± 10%

IS41LV44004

3.3V ± 10%

VCC

I/O0

I/O1

RAS

*A11(NC)

A10

VCC

GND

I/O3

I/O2

CAS

GND

* A11 is NC for 2K Refresh devices

PIN DESCRIPTIONS

A0-A11

Address Inputs (4K Refresh)

A0-A10

Address Inputs (2K Refresh)

I/O0-3

Data Inputs/Outputs

Write Enable

Output Enable

RAS

Row Address Strobe

CAS

Column Address Strobe

Vcc

Power

GND

Ground

No Connection

PIN CONFIGURATION

24 Pin SOJ

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D

06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

FUNCTIONAL BLOCK DIAGRAM

CAS

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY

4,194,304 x 4

ROW DECODER

DATA I/O BUFFERS

CAS

CONTROL

LOGIC

CONTROL

LOGICS

CONTROL

LOGIC

I/O0-I/O3

RAS

A0-A10(A11)

RAS

CLOCK

GENERATOR

REFRESH

COUNTER

ADDRESS

BUFFERS

TRUTH TABLE

Function

RAS

CAS

Address t

I/O

Standby

High-Z

Read

ROW/COL

OUT

Write: Word (Early Write)

ROW/COL

Read-Write

ROW/COL

OUT

, D

EDO Page-Mode Read

1st Cycle:

ROW/COL

OUT

2nd Cycle:

NA/COL

OUT

EDO Page-Mode Write

1st Cycle:

ROW/COL

2nd Cycle:

NA/COL

EDO Page-Mode

1st Cycle:

ROW/COL

OUT

, D

Read-Write

2nd Cycle:

NA/COL

OUT

, D

Hidden Refresh

Read

ROW/COL

OUT

Write

(1)

ROW/COL

OUT

RAS-Only Refresh

ROW/NA

High-Z

CBR Refresh

High-Z

Note:
1. EARLY WRITE only.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D
06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

Functional Description

The IS41C4400x and IS41LV4400x are CMOS
DRAMs optimized for high-speed bandwidth, low
power applications. During READ or WRITE cycles, each
bit is uniquely addressed through the 11 or 12 address
bits. These are entered 11 bits (A0-A10) at a time for the
2K refresh device or 12 bits (A0-A11) at a time for the 4K
refresh device. The row address is latched by the Row
Address Strobe (

RAS). The column address is latched by

the Column Address Strobe (

CAS). RAS is used to latch

the first nine bits and

CAS is used the latter ten bits.

Memory Cycle

A memory cycle is initiated by bring

RAS LOW and it is

terminated by returning both

RAS and CAS HIGH. To

ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t

RAS

time has expired. A new

cycle must not be initiated until the minimum precharge
time t

, t

has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of

CAS or OE,

whichever occurs last, while holding

WE HIGH. The

column address must be held for a minimum time
specified by t

. Data Out becomes valid only when t

RAC

, t

CAC

and t

OEA

are all satisfied. As a result, the access

time is dependent on the timing relationships between
these parameters.

Write Cycle

A write cycle is initiated by the falling edge of

CAS and

WE, whichever occurs last. The input data must be valid
at or before the falling edge of

CAS or WE, whichever

occurs last.

Auto Refresh Cycle

To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in
each 64ms period. There are two ways to refresh the
memory:

1. By clocking each of the 2,048 row addresses (A0

through A10) or 4096 row addresses (A0 through
A11) with RAS at least once every 32 ms or 64ms
respectively. Any read, write, read-modify-write or
RAS-only cycle refreshes the addressed row.

2. Using a

CAS-before-RAS refresh cycle. CAS-before-RAS

refresh is activated by the falling edge of

RAS, while

holding

CAS LOW. In CAS-before-RAS refresh cycle,

an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.

Power-On

After application of the V

supply, an initial pause of 200

µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a

RAS

signal).

During power-on, it is recommended that

RAS track with

or be held at a valid V

to avoid current surges.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D

06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameters

Rating

Unit

Voltage on Any Pin Relative to GND

1.0 to +7.0

3.3V

0.5 to +4.6

Supply Voltage

1.0 to +7.0

3.3V

0.5 to +4.6

OUT

Output Current

Power Dissipation

Commercial Operation Temperature

0 to +70

°C

Industrial Operation Temperature

-40 to +85

STG

Storage Temperature

55 to +125

°C

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltages are referenced to GND.)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

3.3V

3.0

3.3

3.6

Input High Voltage

2.4

+ 1.0

3.3V

2.0

+ 0.3

Input Low Voltage

1.0

0.8

3.3V

0.3

0.8

Commercial Ambient Temperature

°C

Industrial Ambient Temperature

-40

°C

CAPACITANCE

(1,2)

Symbol

Parameter

Max.

Unit

Input Capacitance: A0-A10(A11)

Input Capacitance:

RAS, CAS, WE, OE

Data Input/Output Capacitance: I/O0-I/O3

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25°C, f = 1 MHz.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D
06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol

Parameter

Test Condition

Speed

Min.

Max.

Unit

Input Leakage Current

Any input 0V

Vcc

µA

Other inputs not under test = 0V

Output Leakage Current

Output is disabled (Hi-Z)

µA

OUT

Vcc

Output High Voltage Level

= 5.0 mA, Vcc = 5V

2.4

= 2.0 mA, Vcc = 3.3V

Output Low Voltage Level

= 4.2 mA, Vcc = 5V

0.4

= 2 mA, Vcc = 3.3V

Standby Current: TTL

RAS, CAS

Commercial

3.3V

0.5

Industrial

3.3V

Standby Current: CMOS

RAS, CAS

0.2V

3.3V

0.5

Operating Current:

RAS, CAS,

-50

120

Random Read/Write

(2,3,4)

Address Cycling, t

= t

(min.)

-60

110

Average Power Supply Current

Operating Current:

RAS = V

CAS,

-50

EDO Page Mode

(2,3,4)

Cycling t

= t

(min.)

-60

Average Power Supply Current

Refresh Current:

RAS Cycling, CAS

-50

120

RAS-Only

(2,3)

= t

(min.)

-60

110

Average Power Supply Current

Refresh Current:

RAS, CAS Cycling

-50

120

CBR

(2,3,5)

= t

(min.)

-60

110

Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight

RAS refresh cycles (RAS-Only or CBR) before proper device

operation is assured. The eight

RAS cycles wake-up should be repeated any time the t

REF

refresh requirement is exceeded.

2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D

06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

AC CHARACTERISTICS

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-50

-60

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

Random READ or WRITE Cycle Time

104

RAC

Access Time from

RAS

(6, 7)

CAC

Access Time from

CAS

(6, 8, 15)

Access Time from Column-Address

(6)

RAS

RAS Pulse Width

10K

RAS Precharge Time

CAS

CAS Pulse Width

(23)

10K

CAS Precharge Time

(9)

CSH

CAS Hold Time

(21)

RCD

RAS to CAS Delay Time

(10, 20)

ASR

Row-Address Setup Time

RAH

Row-Address Hold Time

ASC

Column-Address Setup Time

(20)

CAH

Column-Address Hold Time

(20)

Column-Address Hold Time

(referenced to

RAS)

RAD

RAS to Column-Address Delay Time

(11)

RAL

Column-Address to

RAS Lead Time

RPC

RAS to CAS Precharge Time

RSH

RAS Hold Time

RHCP

RAS Hold Time from CAS Precharge

CLZ

CAS to Output in Low-Z

(15, 24)

CRP

CAS to RAS Precharge Time

(21)

Output Disable Time

(19, 24)

Output Enable Time

(15, 16)

OED

Output Enable Data Delay (Write)

OEHC

OE HIGH Hold Time from CAS HIGH

OEP

OE HIGH Pulse Width

OES

OE LOW to CAS HIGH Setup Time

RCS

Read Command Setup Time

(17, 20)

RRH

Read Command Hold Time

(referenced to

RAS)

(12)

RCH

Read Command Hold Time

(referenced to

CAS)

(12, 17, 21)

WCH

Write Command Hold Time

(17)

WCR

Write Command Hold Time

(referenced to

RAS)

(17)

Write Command Pulse Width

(17)

WPZ

WE Pulse Widths to Disable Outputs

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D
06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

AC CHARACTERISTICS (Continued)

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-50

-60

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

RWL

Write Command to

RAS Lead Time

(17)

CWL

Write Command to

CAS Lead Time

(17, 21)

WCS

Write Command Setup Time

(14, 17, 20)

DHR

Data-in Hold Time (referenced to

RAS)

ACH

Column-Address Setup Time to

CAS

Precharge during WRITE Cycle

OEH

OE Hold Time from WE during

READ-MODIFY-WRITE cycle

(18)

Data-In Setup Time

(15, 22)

Data-In Hold Time

(15, 22)

RWC

READ-MODIFY-WRITE Cycle Time

108

133

RWD

RAS to WE Delay Time during

READ-MODIFY-WRITE Cycle

(14)

CWD

CAS to WE Delay Time

(14, 20)

AWD

Column-Address to

WE Delay Time

(14)

EDO Page Mode READ or WRITE

Cycle Time

RASP

RAS Pulse Width in EDO Page Mode

100K

CPA

Access Time from

CAS Precharge

(15)

PRWC

EDO Page Mode READ-WRITE

Cycle Time

COH

Data Output Hold after

CAS LOW

OFF

Output Buffer Turn-Off Delay from

CAS or RAS

(13,15,19, 24)

WHZ

Output Disable Delay from

CSR

CAS Setup Time (CBR REFRESH)

(20, 25)

CHR

CAS Hold Time (CBR REFRESH)

( 21, 25)

ORD

OE Setup Time prior to RAS during

HIDDEN REFRESH Cycle

REF

Auto Refresh Period

2,048 Cycles

4,096 Cycles

Transition Time (Rise or Fall)

(2, 3)

AC TEST CONDITIONS

Output load:

Two TTL Loads and 50 pF

Input timing reference levels: V

= 2.4V, V

= 0.8V

Output timing reference levels: V

= 2.0V, V

= 0.8V

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D

06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

Notes:
1. An initial pause of 200 µs is required after power-up followed by eight

RAS refresh cycle (RAS-Only or CBR) before proper device

operation is assured. The eight

RAS cycles wake-up should be repeated any time the t

REF

refresh requirement is exceeded.

2. V

(MIN) and V

(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V

and

(or between V

and V

) and assume to be 1 ns for all inputs.

3. In addition to meeting the transition rate specification, all input signals must transit between V

and V

(or between V

and V

) in a

monotonic manner.

4. If

CAS and RAS = V

, data output is High-Z.

5. If

CAS = V

, data output may contain data from the last valid READ cycle.

6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t

RCD

- t

RCD

(MAX). If t

RCD

is greater than the maximum recommended value shown in this table, t

RAC

will increase by the

amount that t

RCD

exceeds the value shown.

8. Assumes that t

RCD

· t

RCD

(MAX).

9. If

CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data

output buffer,

CAS and RAS must be pulsed for t

10. Operation with the t

RCD

(MAX) limit ensures that t

RAC

(MAX) can be met. t

RCD

(MAX) is specified as a reference point only; if t

RCD

greater than the specified t

RCD

(MAX) limit, access time is controlled exclusively by t

CAC

11. Operation within the t

RAD

(MAX) limit ensures that t

RCD

(MAX) can be met. t

RAD

(MAX) is specified as a reference point only; if t

RAD

greater than the specified t

RAD

(MAX) limit, access time is controlled exclusively by t

12. Either t

RCH

or t

RRH

must be satisfied for a READ cycle.

13. t

OFF

(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V

or V

14. t

WCS

, t

RWD

, t

AWD

and t

CWD

are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t

WCS

· t

WCS

(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t

RWD

· t

RWD

(MIN),

AWD

· t

AWD

(MIN) and t

CWD

· t

CWD

(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected

cell. If neither of the above conditions is met, the state of I/O (at access time and until

CAS and RAS or OE go back to V

) is

indeterminate.

OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.

15. Output parameter (I/O) is referenced to corresponding

CAS input.

16. During a READ cycle, if

OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE

WRITE or READ-MODIFY-WRITE is not possible.

17. Write command is defined as

WE going low.

18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t

and t

OEH

met (

OE HIGH during WRITE cycle) in order to ensure

that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if

CAS remains LOW and

OE is taken back to LOW after t

OEH

is met.

19. The I/Os are in open during READ cycles once t

or t

OFF

occur.

20. Determined by falling edge of

CAS.

21. Determined by rising edge of

CAS.

22. These parameters are referenced to

CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-

MODIFY-WRITE cycles.

23.

CAS must meet minimum pulse width.

24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D

06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

EDO-PAGE-MODE READ CYCLE

Note:
1. t

can be measured from falling edge of

CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both

measurements must meet the t

specifications.

RASP

ADDRESS

CAS

RAS

Row

CAS,

CLCH

CRP

RCD

CSH

CAS,

CLCH

CAH

CAS,

CLCH

RAL

RSH

(1)

ASR

RAH

RAD

Column

CAH

Column

ASC

I/O

Open

Valid Data

CPA

CAC

RAC

COH

CLZ

OEP

OES

OEHC

Valid Data

RCH

RRH

CPA

CAC

OFF

CLZ

Valid Data

ASC

RCS

Don't Care

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D

06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

EDO-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY WRITE Cycles)

Note:
1. t

can be measured from falling edge of

CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both

measurements must meet the t

specifications.

RASP

ADDRESS

CAS

RAS

Row

CRP

RCD

CSH

CAH

CAS,

CLCH

RAL

RSH

RAH

RAD

ASR

Column

CAH

Column

ASC

CAS,

CLCH

CAS,

CLCH

I/O

ASC

RWD

RCS

CWL

AWD

CWD

CAC

CLZ

AWD

CWD

CWL

AWD

CWD

CWL

RWL

Open

OUT

OEH

CPA

CAC

CLZ

OUT

CAC

CLZ

OUT

CPA

RAC

/ t

PRWC

(1)

Don't Care

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D
06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

HIDDEN REFRESH CYCLE

(1)

(

WE = HIGH; OE = LOW)

CBR REFRESH CYCLE

(Addresses;

WE, OE = DON'T CARE)

Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case,

WE = LOW and OE = HIGH.

2. t

OFF

is referenced from rising edge of

RAS or CAS, whichever occurs last.

RAS

I/O

CAS

RAS

Open

RPC

CSR

CHR

RPC

CSR

CHR

RAS

CAS

RAS

CRP

RCD

RSH

CHR

ASC

RAD

ADDRESS

Row

Column

RAH

ASR

RAL

CAH

I/O

Open

Valid Data

CAC

RAC

CLZ

OFF

(2)

ORD

Don't Care

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D

06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

ORDERING INFORMATION

Commercial Range: 0°C to 70°C

Voltage: 5V

Speed (ns)

Order Part No.

Refresh

Package

IS41C44002-50J

300-mil SOJ

IS41C44002-60J

300-mil SOJ

Speed (ns)

Order Part No.

Refresh

Package

IS41C44004-50J

300-mil SOJ

IS41C44004-60J

300-mil SOJ

Voltage: 3.3V

Speed (ns)

Order Part No.

Refresh

Package

IS41LV44002-50J

300-mil SOJ

IS41LV44002-60J

300-mil SOJ

Speed (ns)

Order Part No.

Refresh

Package

IS41LV44004-50J

300-mil SOJ

IS41LV44004-60J

300-mil SOJ

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. D
06/24/01

IS41C4400

IS41LV4400

ERIES

ISSI

ORDERING INFORMATION

Industrial Range: -40°C to 85°C

Voltage: 5V

Speed (ns)

Order Part No.

Refresh

Package

IS41C44002-50JI

300-mil SOJ

IS41C44002-60JI

300-mil SOJ

Speed (ns)

Order Part No.

Refresh

Package

IS41C44004-50JI

300-mil SOJ

IS41C44004-60JI

300-mil SOJ

Voltage: 3.3V

Speed (ns)

Order Part No.

Refresh

Package

IS41LV44002-50JI

300-mil SOJ

IS41LV44002-60JI

300-mil SOJ

Speed (ns)

Order Part No.

Refresh

Package

IS41LV44004-50JI

300-mil SOJ

IS41LV44004-60JI

300-mil SOJ

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774
Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

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