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Электронный компонент: IS61C1024L-20

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IS61C1024
IS61C1024L
128K x 8 HIGH-SPEED
CMOS STATIC RAM
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. Copyright 1999, Integrated Silicon Solution, Inc.
DESCRIPTION
The
ISSI
IS61C1024 and IS61C1024L are very high-speed,
low power, 131,072-word by 8-bit CMOS static RAMs. They
are fabricated using
ISSI's high-performance CMOS
technology. This highly reliable process coupled with innovative
circuit design techniques, yields higher performance and low
power consumption devices.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (
WE
)
controls both writing and reading of the memory.
The IS61C1024 and IS61C1024L are available in 32-pin
300-mil SOJ, and TSOP (Type I, 8x20), and sTSOP (Type I,
8 x 13.4) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE1
OE
WE
512 x 2048
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CE2
FEATURES
High-speed access time: 12, 15, 20, 25 ns
Low active power: 600 mW (typical)
Low standby power: 500
W (typical) CMOS
standby
Output Enable (
OE
) and two Chip Enable
(
CE1
and CE2) inputs for ease in applications
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V (
10%) power supply
Low power version available: IS61C1024L
Commercial and industrial temperature ranges
available
MAY 1999
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
SR028-1K
05/12/99
IS61C1024
IS61C1024L
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR028-1J
11/03/98
ISSI
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE1
CE1
CE1
CE1
CE1
CE2
OE
OE
OE
OE
OE
I/O Operation
Vcc Current
Not Selected
X
H
X
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
X
X
L
X
High-Z
I
SB
1
, I
SB
2
Output Disabled H
L
H
H
High-Z
I
CC
1
, I
CC
2
Read
H
L
H
L
D
OUT
I
CC
1
, I
CC
2
Write
L
L
H
X
D
IN
I
CC
1
, I
CC
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
32-Pin SOJ
PIN DESCRIPTIONS
A0-A16
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0
C to +70
C
5V
10%
Industrial
40
C to +85
C
5V
10%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN CONFIGURATION
32-Pin TSOP (Type 1) (T) and sTSOP (Type 1) (H)
IS61C1024
IS61C1024L
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
SR028-1K
05/12/99
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
55 to +125
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.5
W
I
OUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25
C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
Com.
2
2
A
Ind.
5
5
I
LO
Output Leakage
GND
V
OUT
V
CC
Com.
2
2
A
Outputs Disabled
Ind.
5
5
Note:
1. V
IL
= 3.0V for pulse width less than 10 ns.
IS61C1024
IS61C1024L
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR028-1J
11/03/98
ISSI
IS61C1024 POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-12 ns
-15 ns
-20 ns
-25 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
1
Vcc Operating
V
CC
= V
CC
MAX
.,
CE
= V
IL
Com.
--
85
--
85
--
85
--
85
mA
Supply Current
I
OUT
= 0 mA, f = 0
Ind.
--
110
--
110
--
110
--
110
I
CC
2
Vcc Dynamic Operating
V
CC
= V
CC
MAX
.,
CE
= V
IL
Com.
--
170
--
160
--
150
--
140
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
180
--
170
--
160
--
150
I
SB
1
TTL Standby Current
V
CC
= V
CC
MAX
.,
Com.
--
40
--
40
--
40
--
40
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
--
60
--
60
--
60
--
60
CE1
V
IH
, f = 0 or
CE2
V
IL
, f = 0
I
SB
2
CMOS Standby
V
CC
= V
CC
MAX
.,
Com.
--
30
--
30
--
30
--
30
mA
Current (CMOS Inputs)
CE1
V
CC
0.2V,
Ind.
--
40
--
40
--
40
--
40
CE2
0.2V
V
IN
> V
CC
0.2V, or
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS61C1024L POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-15 ns
-20 ns
-25 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
1
Vcc Operating
V
CC
= V
CC
MAX
.,
CE
= V
IL
Com.
--
85
--
85
--
85
mA
Supply Current
I
OUT
= 0 mA, f = 0
Ind.
--
110
--
110
--
110
I
CC
2
Vcc Dynamic Operating
V
CC
= V
CC
MAX
.,
CE
= V
IL
Com.
--
160
--
150
--
140
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
170
--
160
--
150
I
SB
1
TTL Standby Current
V
CC
= V
CC
MAX
,
Com.
--
40
--
40
--
40
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
--
60
--
60
--
60
CE1
V
IH
, f = 0 or
CE2
V
IL
, f = 0
I
SB
2
CMOS Standby
V
CC
= V
CC
MAX
.,
Com.
--
500
--
500
--
500
A
Current (CMOS Inputs)
CE1
V
CC
0.2V,
Ind.
--
750
--
750
--
750
CE2
0.2V
V
IN
> V
CC
0.2V, or
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS61C1024
IS61C1024L
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
SR028-1K
05/12/99
ISSI
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-12
(2)
-15 ns
-20 ns
-25 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
12
--
15
--
20
--
25
--
ns
t
AA
Address Access Time
--
12
--
15
--
20
--
25
ns
t
OHA
Output Hold Time
3
--
3
--
3
--
3
--
ns
t
ACE
1
CE1
Access Time
--
12
--
15
--
20
--
25
ns
t
ACE
2
CE2 Access Time
--
12
--
15
--
20
--
25
ns
t
DOE
OE
Access Time
--
6
--
7
--
9
--
9
ns
t
LZOE
(3)
OE
to Low-Z Output
0
--
0
--
0
--
0
--
ns
t
HZOE
(3)
OE
to High-Z Output
0
6
0
6
0
7
0
10
ns
t
LZCE
1
(3)
CE1
to Low-Z Output
2
--
2
--
3
--
3
--
ns
t
LZCE
2
(3)
CE2 to Low-Z Output
2
--
2
--
3
--
3
--
ns
t
HZCE
(3)
CE1
or CE2 to High-Z Output
0
7
0
8
0
9
0
10
ns
t
PU
(4)
CE1
or CE2 to Power-Up
0
--
0
--
0
--
0
--
ns
t
PD
(4)
CE1
or CE2 to Power-Down
--
12
--
12
--
18
--
20
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. -12 ns device for IS61C1024 only.
3. Tested with the load in Figure 2. Transition is measured
500 mV from steady-state voltage. Not 100% tested.
4. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 1
Figure 2
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
480
30 pF
Including
jig and
scope
255
OUTPUT
5V
IS61C1024
IS61C1024L
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR028-1J
11/03/98
ISSI
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1
t
ACE2
t
LZCE1
t
LZCE2
t
HZOE
HIGH-Z
DATA VALID
ADDRESS
OE
CE1
CE2
D
OUT
t
HZCE1
t
HZCE2
CE2_RD2.eps
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE1
= V
IL
, CE2 = V
IH
.
3. Address is valid prior to or coincident with
CE1
LOW and CE2 HIGH transitions.
READ CYCLE NO. 2
(1,3)
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
IS61C1024
IS61C1024L
Integrated Silicon Solution, Inc. -- 1-800-379-4774
7
SR028-1K
05/12/99
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range, Standard and Low Power)
-12 ns
(3)
-15 ns
-20 ns
-25 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
12
--
15
--
20
--
25
--
ns
t
SCE
1
CE1
to Write End
10
--
12
--
15
--
20
--
ns
t
SCE
2
CE2 to Write End
10
--
12
--
15
--
20
--
ns
t
AW
Address Setup Time to Write End
10
--
12
--
15
--
20
--
ns
t
HA
Address Hold from Write End
0
--
0
--
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
0
--
0
--
ns
t
PWE
(4)
WE
Pulse Width
10
--
10
--
12
--
15
--
ns
t
SD
Data Setup to Write End
7
--
8
--
10
--
12
--
ns
t
HD
Data Hold from Write End
0
--
0
--
0
--
0
--
ns
t
HZWE
(5)
WE
LOW to High-Z Output
--
7
--
7
--
10
--
12
ns
t
LZWE
(5)
WE
HIGH to Low-Z Output
2
--
2
--
2
--
2
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. -12 ns device for IS61C1024 only.
4. Tested with
OE
HIGH.
5. Tested with the load in Figure 2. Transition is measured
500 mV from steady-state voltage. Not 100% tested.
IS61C1024
IS61C1024L
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR028-1J
11/03/98
ISSI
WRITE CYCLE NO. 2
(
OE
is HIGH During Write Cycle)
(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
HIGH
CE2
CE2_WR2.eps
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE1
t
SCE2
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
CE2
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CE2_WR1.eps
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE
Controlled,
OE
is HIGH or LOW)
(1 )
IS61C1024
IS61C1024L
Integrated Silicon Solution, Inc. -- 1-800-379-4774
9
SR028-1K
05/12/99
ISSI
WRITE CYCLE NO. 3
(
OE
is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
HIGH
CE2
CE2_WR3.eps
IS61C1024
IS61C1024L
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
SR028-1J
11/03/98
ISSI
IS61C1024L LOW POWER VERSION
ORDERING INFORMATION
Commercial Range: 0
C to +70
C
Speed (ns)
Order Part No.
Package
15
IS61C1024L-15J
300-mil Plastic SOJ
IS61C1024L-15K
400-mil Plastic SOJ
IS61C1024L-15H
sTSOP (Type I)
IS61C1024L-15T
TSOP (Type I)
20
IS61C1024L-20J
300-mil Plastic SOJ
IS61C1024L-20K
400-mil Plastic SOJ
IS61C1024L-20H
sTSOP (Type I)
IS61C1024L-20T
TSOP (Type I)
25
IS61C1024L-25J
300-mil Plastic SOJ
IS61C1024L-25K
400-mil Plastic SOJ
IS61C1024L-25H
sTSOP (Type I)
IS61C1024L-25T
TSOP (Type I)
IS61C1024L LOW POWER VERSION
ORDERING INFORMATION
Industrial Range: 40
C to +85
C
Speed (ns)
Order Part No.
Package
15
IS61C1024L-15JI
300-mil Plastic SOJ
IS61C1024L-15KI
400-mil Plastic SOJ
IS61C1024L-12HI
sTSOP (Type I)
IS61C1024L-15TI
TSOP (Type I)
20
IS61C1024L-20JI
300-mil Plastic SOJ
IS61C1024L-20KI
400-mil Plastic SOJ
IS61C1024L-12HI
sTSOP (Type I)
IS61C1024L-20TI
TSOP (Type I)
25
IS61C1024L-25JI
300-mil Plastic SOJ
IS61C1024L-25KI
400-mil Plastic SOJ
IS61C1024L-12HI
sTSOP (Type I)
IS61C1024L-25TI
TSOP (Type I)
IS61C1024 STANDARD VERSION
ORDERING INFORMATION
Commercial Range: 0
C to +70
C
Speed (ns)
Order Part No.
Package
12
IS61C1024-12J
300-mil Plastic SOJ
12
IS61C1024-12K
400-mil Plastic SOJ
12
IS61C1024-12H
sTSOP (Type I)
12
IS61C1024-12T
TSOP (Type I)
15
IS61C1024-15J
300-mil Plastic SOJ
15
IS61C1024-15K
400-mil Plastic SOJ
15
IS61C1024-15H
sTSOP (Type I)
15
IS61C1024-15T
TSOP (Type I)
20
IS61C1024-20J
300-mil Plastic SOJ
20
IS61C1024-20K
400-mil Plastic SOJ
20
IS61C1024-20H
sTSOP (Type I)
20
IS61C1024-20T
TSOP (Type I)
25
IS61C1024-25J
300-mil Plastic SOJ
25
IS61C1024-25K
400-mil Plastic SOJ
25
IS61C1024-25H
sTSOP (Type I)
25
IS61C1024-25T
TSOP (Type I)
IS61C1024 STANDARD VERSION
ORDERING INFORMATION
Industrial Range: 40
C to +85
C
Speed (ns)
Order Part No.
Package
12
IS61C1024-12JI
300-mil Plastic SOJ
12
IS61C1024-12KI
400-mil Plastic SOJ
12
IS61C1024-12HI
sTSOP (Type I)
12
IS61C1024-12TI
TSOP (Type I)
15
IS61C1024-15JI
300-mil Plastic SOJ
15
IS61C1024-15KI
400-mil Plastic SOJ
15
IS61C1024-15HI
sTSOP (Type I)
15
IS61C1024-15TI
TSOP (Type I)
20
IS61C1024-20JI
300-mil Plastic SOJ
20
IS61C1024-20KI
400-mil Plastic SOJ
20
IS61C1024-20HI
sTSOP (Type I)
20
IS61C1024-20TI
TSOP (Type I)
25
IS61C1024-25JI
300-mil Plastic SOJ
25
IS61C1024-25KI
400-mil Plastic SOJ
25
IS61C1024-25HI
sTSOP (Type I)
25
IS61C1024-25TI
TSOP (Type I)
IS61C1024
IS61C1024L
Integrated Silicon Solution, Inc. -- 1-800-379-4774
11
SR028-1K
05/12/99
ISSI
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com