Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. B
02/03/06
ISSI
IS61VPD51236A IS61VPD102418A
IS61LPD51236A IS61LPD102418A
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Double cycle deselect
Snooze MODE for reduced-power standby
JTAG Boundary Scan for PBGA package
Power Supply
LPD: V
DD
3.3V + 5%, V
DDQ
3.3V/2.5V + 5%
VPD: V
DD
2.5V + 5%, V
DDQ
2.5V + 5%
JEDEC 100-Pin TQFP and 165-pin PBGA
package
Lead-free available
DESCRIPTION
The
ISSI
IS61LPD/VPD51236A and IS61LPD/
VPD102418A are high-speed, low-power synchronous static
RAMs designed to provide burstable, high-performance memory
for communication and networking applications. The
IS61LPD/VPD51236A is organized as 524,288 words by 36
bits, and the IS61LPD/VPD102418A is organized as
1,048,576 words by 18 bits. Fabricated with
ISSI
's ad-
vanced CMOS technology, the device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive capa-
bility outputs into a single monolithic circuit. All synchro-
nous inputs pass through registers controlled by a positive-
edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to four
bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (
BWE) input combined with one or more
individual byte write signals (
BWx). In addition, Global
Write (
GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either
ADSP (Address Status
Processor) or
ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPELINED,
DOUBLE CYCLE DESELECT STATIC RAM
FEBRUARY 2006
FAST ACCESS TIME
Symbol
Parameter
250
200
Units
t
KQ
Clock Access Time
2.6
3.1
ns
t
KC
Cycle Time
4
5
ns
Frequency
250
200
MHz
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
02/03/06
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
ISSI
PIN DESCRIPTIONS
165 PBGA PACKAGE PIN CONFIGURATION
512K
X
36 (TOP VIEW)
Note: * A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWc
BWb
CE2
BWE
ADSC
ADV
A
NC
B
NC
A
CE2
BWd
BWa
CLK
GW
OE
ADSP
A
NC
C
DQPc
NC
V
DDQ
Vss
Vss
Vss
Vss
Vss
V
DDQ
NC DQPb
D
DQc
DQc
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQb
DQb
E
DQc
DQc
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQb
DQb
F
DQc
DQc
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQb
DQb
G
DQc
DQc
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQb
DQb
H
NC
Vss
NC
V
DD
Vss
Vss
Vss
V
DD
NC
NC
ZZ
J
DQd
DQd
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
DQa
K
DQd
DQd
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
DQa
L
DQd
DQd
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
DQa
M
DQd
DQd
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
DQa
N
DQPd
NC
V
DDQ
Vss
NC
A
Vss
Vss
V
DDQ
NC DQPa
P
NC
NC
A
A
TDI
A
1
*
TDO
A
A
A
A
R
MODE
NC
A
A
TMS
A
0
*
TCK
A
A
A
A
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address
Advance
ADSP
Address Status Processor
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE
Synchronous Chip Select
CE2
Synchronous Chip Select
CE2
Synchronous Chip Select
BWx (x=a,b,c,d) Synchronous Byte Write
Controls
Symbol
Pin Name
BWE
Byte Write Enable
OE
Output Enable
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
TCK, TDO
JTAG Pins
TMS, TDI
NC
No Connect
DQa-DQb
Data Inputs/Outputs
DQPa-Pb
Data Inputs/Outputs
V
DD
Power Supply
V
DDQ
Output Power Supply
Vss
Ground
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. B
02/03/06
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A, IS61LPD102418A
ISSI
Note: * A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
165 PBGA PACKAGE PIN CONFIGURATION
1M
X
18 (TOP VIEW)
PIN DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWb
NC
CE2
BWE
ADSC
ADV
A
A
B
NC
A
CE2
NC
BWa
CLK
GW
OE
ADSP
A
NC
C
NC
NC
V
DDQ
Vss
Vss
Vss
Vss
Vss
V
DDQ
NC
DQPa
D
NC
DQb
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
NC
DQa
E
NC
DQb
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
NC
DQa
F
NC
DQb
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
NC
DQa
G
NC
DQb
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
NC
DQa
H
NC
Vss
NC
V
DD
Vss
Vss
Vss
V
DD
NC
NC
ZZ
J
DQb
NC
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
NC
K
DQb
NC
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
NC
L
DQb
NC
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
NC
M
DQb
NC
V
DDQ
V
DD
Vss
Vss
Vss
V
DD
V
DDQ
DQa
NC
N
DQPb
NC
V
DDQ
Vss
NC
A
Vss
Vss
V
DDQ
NC
NC
P
NC
NC
A
A
TDI
A
1
*
TDO
A
A
A
A
R
MODE
NC
A
A
TMS
A
0
*
TCK
A
A
A
A
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address
Advance
ADSP
Address Status Processor
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE
Synchronous Chip Select
CE2
Synchronous Chip Select
CE2
Synchronous Chip Select
BWx (x=a,b)
Synchronous Byte Write
Controls
Symbol
Pin Name
BWE
Byte Write Enable
OE
Output Enable
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
TCK, TDO
JTAG Pins
TMS, TDI
NC
No Connect
DQa-DQb
Data Inputs/Outputs
DQPa-Pb
Data Inputs/Outputs
V
DD
Power Supply
V
DDQ
Output Power Supply
Vss
Ground
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