Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
FEATURES
100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single Read/Write control pin
Clock controlled, registered address,
data and control
Interleaved or linear burst sequence control using
MODE input
Three chip enables for simple depth expansion
and address pipelining
Power Down mode
Common data inputs and data outputs
CKE
pin to enable clock and suspend operation
JEDEC 100-pin TQFP, 165-ball PBGA and 209-
ball (x72) PBGA packages
Power supply:
NVF: V
DD
2.5V ( 5%), V
DDQ
2.5V ( 5%)
NLF: V
DD
3.3V ( 5%), V
DDQ
3.3V/2.5V ( 5%)
JTAG Boundary Scan for PBGA packages
Industrial temperature available
Lead-free available
DESCRIPTION
The 18 Meg 'NLF/NVF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 72 bits, 512K words
by 36 bits and 1M words by 18 bits, fabricated with
ISSI
's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,
CKE
is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when
WE
is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
256K x 72, 512K x 36 and 1M x 18
18Mb, FLOW THROUGH 'NO WAIT'
STATE BUS SRAM
AUGUST 2005
FAST ACCESS TIME
Symbol
Parameter
6.5
7.5
Units
t
KQ
Clock Access Time
6.5
7.5
ns
t
KC
Cycle Time
7.5
8.5
ns
Frequency
133
117
MHz
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
BLOCK DIAGRAM
ADV
WE
}
BWY
X
(X=a-h, a-d, or a,b)
CE
CE2
CE2
CONTROL
LOGIC
256Kx72; 512Kx36;
1024Kx18
MEMORY ARRAY
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
BUFFER
ADDRESS
REGISTER
x 72: A [0:17] or
x 36: A [0:18] or
x 18: A [0:19]
CLK
CKE
A2-A17 or A2-A18 or A2-A19
A0-A1
A'0-A'1
BURST
ADDRESS
COUNTER
MODE
DATA-IN
REGISTER
DATA-IN
REGISTER
CONTROL
REGISTER
OE
ZZ
72, 36 or 18
K
K
DQx/DQPx
K
K
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
Bottom View
165-Ball, 13 mm x 15mm BGA
Bottom View
209-Ball, 14 mm x 22 mm BGA
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
PIN CONFIGURATION -- 256K X 72, 209-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
DQg
DQg
A
CE2
A
ADV
A
CE2
A
DQb
DQb
B
DQg
DQg
BW
c
BW
g
NC
WE
A
BW
b
BW
f
DQb
DQb
C
DQg
DQg
BW
h
BW
d
NC
CE
NC
BW
e
BW
a
DQb
DQb
D
DQg
DQg
V
SS
NC
NC
OE
NC
NC
V
SS
DQb
DQb
E
DQPg
DQPc
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
DQPf
DQPb
F
DQc
DQc
V
SS
V
SS
V
SS
NC
V
SS
V
SS
V
SS
DQf
DQf
G
DQc
DQc
V
DDQ
V
DDQ
V
DD
NC
V
DD
V
DDQ
V
DDQ
DQf
DQf
H
DQc
DQc
V
SS
V
SS
V
SS
NC
V
SS
V
SS
V
SS
DQf
DQf
J
DQc
DQc
V
DDQ
V
DDQ
V
DD
NC
V
DD
V
DDQ
V
DDQ
DQf
DQf
K
NC
NC
CLK
NC
V
SS
CKE
V
SS
NC
NC
NC
NC
L
DQh
DQh
V
DDQ
V
DDQ
V
DD
NC
V
DD
V
DDQ
V
DDQ
DQa
DQa
M
DQh
DQh
V
SS
V
SS
V
SS
NC
V
SS
V
SS
V
SS
DQa
DQa
N
DQh
DQh
V
DDQ
V
DDQ
V
DD
NC
V
DD
V
DDQ
V
DDQ
DQa
DQa
P
DQh
DQh
V
SS
V
SS
V
SS
ZZ
V
SS
V
SS
V
SS
DQa
DQa
R
DQPd
DQPh
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
DQPa
DQPe
T
DQd
DQd
V
SS
NC
NC
MODE
NC
NC
V
SS
DQe
DQe
U
DQd
DQd
NC
A
NC
A
NC
A
NC
DQe
DQe
V
DQd
DQd
A
A
A
A1
A
A
A
DQe
DQe
W
DQd
DQd
TMS
TDI
A
A0
A
TDO
TCK
DQe
DQe
11 x 19 Ball BGA--14 x 22 mm
2
Body--1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
Pin Name
A
Synchronous Address Inputs
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
ADV
Synchronous Burst Address Advance
BW
a-
BW
h
Synchronous Byte Write Enable
CE
,
CE2
, CE2 Synchronous Chip Enable
CLK
Synchronous Clock
CKE
Clock Enable
DQx
Synchronous Data Input/Output
DQPx
Parity Data I/O
V
SS
Ground
MODE
Burst Sequence Selection
OE
Output Enable
TCK, TDI
JTAG Pins
TDO, TMS
V
DD
3.3V/2.5V Power Supply
V
DDQ
Isolated Output Buffer Supply:
3.3V/2.5V
WE
Write Enable
ZZ
Snooze Enable
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
PIN CONFIGURATION -- 512K
X
36, 165-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BW
c
BW
b
CE
2
CKE
ADV
A
A
NC
B
NC
A
CE2
BW
d
BW
a
CLK
WE
OE
A
A
NC
C
DQPc
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPb
D
DQc
DQc
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQb
DQb
E
DQc
DQc
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQb
DQb
F
DQc
DQc
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQb
DQb
G
DQc
DQc
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQb
DQb
H
NC
VDD
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
NC
ZZ
J
DQd
DQd
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
DQa
K
DQd
DQd
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
DQa
L
DQd
DQd
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
DQa
M
DQd
DQd
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQa
DQa
N
DQPd
NC
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
DQPa
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
NC
R
MODE
NC
A
A
TMS
A0*
TCK
A
A
A
A
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control
Input
CLK
Synchronous Clock
CKE
Clock Enable
CE
Synchronous Chip Select
CE
2
Synchronous Chip Select
CE2
Synchronous Chip Select
BW
x (x=a-d)
Synchronous Byte Write Inputs
Symbol
Pin Name
OE
Output Enable
ZZ
Power Sleep Mode
MODE
Burst Sequence Selection
TCK, TDI
JTAG Pins
TDO, TMS
V
DD
3.3V/2.5V Power Supply
NC
No Connect
DQx
Data Inputs/Outputs
DQPx
Parity Data I/O
V
DDQ
Isolated output Power Supply
3.3V/2.5V
V
SS
Ground
6
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
165-PIN PBGA PACKAGE CONFIGURATION 1024K x 18 (TOP VIEW)
PIN DESCRIPTIONS
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control
Input
CLK
Synchronous Clock
CKE
Clock Enable
CE
Synchronous Chip Select
CE
2
Synchronous Chip Select
CE2
Synchronous Chip Select
BW
x (x=a,b)
Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode
1
2
3
4
5
6
7
8
9
10
11
A
A
BW
b
CKE
B
NC
A
WE
OE
C
NC
NC
Vss
Vss
D
NC
DQb
Vss
Vss
NC
E
NC
DQb
Vss
Vss
Vss
F
NC
DQb
NC
G
NC
DQb
NC
NC
H
NC
V
DD
V
DDQ
J
DQb
NC
DQa
K
DQb
NC
L
DQb
NC
Vss
M
DQb
NC
Vss
N
DQPb
NC
Vss
Vss
NC
P
NC
NC
A
1
*
TDO
R
MODE
A
TCK
CE2
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
CE
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
NC
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
NC
BW
a
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDI
TMS
CE
2
CLK
Vss
NC
A
0
*
NC
Vss
Vss
Vss
Vss
Vss
Vss
ADV
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
NC
NC
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
NC
ZZ
DQa
DQa
DQa
DQa
DQPa
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
MODE
Burst Sequence Selection
TCK, TDI
JTAG Pins
TDO, TMS
V
DD
3.3V/2.5V Power Supply
NC
No Connect
DQx
Data Inputs/Outputs
DQPx
Parity Data I/O
V
DDQ
Isolated output Power Supply
3.3V/2.5V
V
SS
Ground
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
7
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BW
a-
BW
d
Synchronous Byte Write Enable
WE
Write Enable
CKE
Clock Enable
Vss
Ground for Core
NC
Not Connected
CE
, CE2,
CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd
Parity Data I/O
MODE
Burst Sequence Selection
V
DD
+3.3V/2.5V Power Supply
V
SS
Ground for output Buffer
V
DDQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
1M x 18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
V
DDQ
Vss
NC
DQPa
DQa
DQa
Vss
V
DDQ
DQa
DQa
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
NC
NC
Vss
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
Vss
NC
NC
DQb
DQb
Vss
V
DDQ
DQb
DQb
NC
V
DD
NC
Vss
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQPb
NC
Vss
V
DDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
V
DD
Vss
CLK
WE
CKE
OE
ADV
A
A
A
A
MODE
A
A
A
A
A1
A0
NC
NC
Vss
V
DD
NC
NC
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQb
DQb
Vss
V
DDQ
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
DQa
DQa
Vss
V
DDQ
DQa
DQa
DQPa
DQPc
DQc
DQc
V
DDQ
Vss
DQc
DQc
DQc
DQc
Vss
V
DDQ
DQc
DQc
NC
V
DD
NC
Vss
DQd
DQd
V
DDQ
Vss
DQd
DQd
DQd
DQd
Vss
V
DDQ
DQd
DQd
DQPd
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
V
DD
Vss
CLK
WE
CKE
OE
ADV
A
A
A
A
MODE
A
A
A
A
A1
A0
NC
NC
Vss
V
DD
NC
NC
A
A
A
A
A
A
A
512K x 36
PIN CONFIGURATION
100-Pin TQFP
8
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
SYNCHRONOUS TRUTH TABLE
(1)
Address
Operation
Used
CE
CE
CE
CE
CE
CE2
CE
CE
CE
CE
CE
2
ADV
WE
WE
WE
WE
WE
BW
BW
BW
BW
BW
x
OE
OE
OE
OE
OE
CKE
CKE
CKE
CKE
CKE
CLK
Not Selected
N/A
H
X
X
L
X
X
X
L
Not Selected
N/A
X
L
X
L
X
X
X
L
Not Selected
N/A
X
X
H
L
X
X
X
L
Not Selected Continue
N/A
X
X
X
H
X
X
X
L
Begin Burst Read
External Address
L
H
L
L
H
X
L
L
Continue Burst Read
Next Address
X
X
X
H
X
X
L
L
NOP/Dummy Read
External Address
L
H
L
L
H
X
H
L
Dummy Read
Next Address
X
X
X
H
X
X
H
L
Begin Burst Write
External Address
L
H
L
L
L
L
X
L
Continue Burst Write
Next Address
X
X
X
H
X
L
X
L
NOP/Write Abort
N/A
L
H
L
L
L
H
X
L
Write Abort
Next Address
X
X
X
H
X
H
X
L
Ignore Clock
Current Address
X
X
X
X
X
X
X
H
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.
WE
= L means Write operation in Write Truth Table.
WE
= H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and
OE
).
BURST
READ
DESELECT
BURST
WRITE
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ
WRITE
BURST
BURST
BURST
DS
DS
DS
READ
DS
DS
READ
WRITE
WRITE
BURST
BURST
WRITE
READ
STATE DIAGRAM
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
9
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
ASYNCHRONOUS TRUTH TABLE
(1)
Operation
ZZ
OE
OE
OE
OE
OE
I/O STATUS
Sleep Mode
H
X
High-Z
Read
L
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with
OE
, otherwise data bus
contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE
(x18)
Operation
WE
WE
WE
WE
WE
BW
BW
BW
BW
BW
a
BW
BW
BW
BW
BW
b
READ
H
X
X
WRITE BYTE a
L
L
H
WRITE BYTE b
L
H
L
WRITE ALL BYTEs
L
L
L
WRITE ABORT/NOP
L
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE
(x36)
Operation
WE
WE
WE
WE
WE
BW
BW
BW
BW
BW
a
BW
BW
BW
BW
BW
b
BW
BW
BW
BW
BW
c
BW
BW
BW
BW
BW
d
READ
H
X
X
X
X
WRITE BYTE a
L
L
H
H
H
WRITE BYTE b
L
H
L
H
H
WRITE BYTE c
L
H
H
L
H
WRITE BYTE d
L
H
H
H
L
WRITE ALL BYTEs
L
L
L
L
L
WRITE ABORT/NOP
L
H
H
H
H
Notes
:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
10
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Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
INTERLEAVED BURST ADDRESS TABLE
(MODE = V
DD
or NC)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
WRITE TRUTH TABLE
(x72)
Operation
WE
WE
WE
WE
WE
BW
BW
BW
BW
BW
a
BW
BW
BW
BW
BW
b
BW
BW
BW
BW
BW
c
BW
BW
BW
BW
BW
d
BW
BW
BW
BW
BW
e
BW
BW
BW
BW
BW
f
BW
BW
BW
BW
BW
g
BW
BW
BW
BW
BW
h
READ
H
X
X
X
X
X
X
X
X
WRITE BYTE a
L
L
H
H
H
H
H
H
H
WRITE BYTE b
L
H
L
H
H
H
H
H
H
WRITE BYTE c
L
H
H
L
H
H
H
H
H
WRITE BYTE d
L
H
H
H
L
H
H
H
H
WRITE BYTE e
L
H
H
H
H
L
H
H
H
WRITE BYTE f
L
H
H
H
H
H
L
H
H
WRITE BYTE g
L
H
H
H
H
H
H
L
H
WRITE BYTE h
L
H
H
H
H
H
H
H
L
WRITE ALL BYTEs
L
L
L
L
L
L
L
L
L
WRITE ABORT/NOP
L
H
H
H
H
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
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Rev. B
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
LINEAR BURST ADDRESS TABLE
(MODE = V
SS
)
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
T
STG
Storage Temperature
65 to +150
C
P
D
Power Dissipation
1.6
W
I
OUT
Output Current (per I/O)
100
mA
V
IN
, V
OUT
Voltage Relative to V
SS
for I/O Pins
0.5 to V
DDQ
+ 0.3
V
V
IN
Voltage Relative to V
SS
for
0.3 to 4.6
V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however,
precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance
circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1
A1', A0' = 1,1
12
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
6.5
7.5
MAX
MAX
Symbol Parameter
Test Conditions
Temp. range x18
x36
x72
x18
x36
x72
Unit
I
CC
AC Operating
Device Selected,
Com.
450
450
600
425
425
550
mA
Supply Current
OE
= V
IH
, ZZ
V
IL
,
Ind.
500
500
650
475
475
600
All Inputs
0.2V or
V
DD
0.2V,
Cycle Time
t
KC
min.
I
SB
Standby Current
Device Deselected,
C
OM
.
150
150
150
150
150
150
mA
TTL Input
V
DD
= Max.,
Ind.
150
150
150
150
150
150
All Inputs
V
IL
or
V
IH
,
ZZ
V
IL
, f = Max.
I
SBI
Standby Current
Device Deselected,
Com.
110
110
110
110
110
110
mA
CMOS Input
V
DD
= Max.,
Ind.
125
125
125
125
125
125
V
IN
V
SS
+ 0.2V or
V
DD
0.2V
f = 0
I
SB
2
Sleep Mode
ZZ > V
IH
Com.
60
60
60
60
60
60
mA
Ind.
75
75
75
75
75
75
Note:
1. MODE pin has an internal pullup and should be tied to V
DD
or V
SS
. It exhibits 100 A maximum leakage current when tied to
V
SS
+ 0.2V or
V
DD
0.2V.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
3.3V
2.5V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= 4.0 mA (3.3V)
2.4
--
2.0
--
V
I
OH
= 1.0 mA
(2.5V)
V
OL
Output LOW Voltage
I
OL
= 8.0 mA (3.3V)
--
0.4
--
0.4
V
I
OL
= 1.0 mA (2.5V)
V
IH
Input HIGH Voltage
2.0
V
DD
+ 0.3
1.7
V
DD
+ 0.3
V
V
IL
Input LOW Voltage
0.3
0.8
0.3
0.7
V
I
LI
Input Leakage Current
V
SS
V
IN
V
DD
(1)
5
5
5
5
A
I
LO
Output Leakage Current
V
SS
V
OUT
V
DDQ
,
OE
= V
IH
5
5
5
5
A
OPERATING RANGE (IS61NVFx)
Range
Ambient Temperature
V
DD
V
DDQ
Commercial
0C to +70C
2.5V 5%
2.5V 5%
Industrial
-40C to +85C
2.5V 5%
2.5V 5%
OPERATING RANGE (IS61NLFx)
Range
Ambient Temperature
V
DD
V
DDQ
Commercial
0C to +70C
3.3V 5%
3.3V / 2.5V 5%
Industrial
-40C to +85C
3.3V 5%
3.3V / 2.5V 5%
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Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
317
5 pF
Including
jig and
scope
351
OUTPUT
+3.3V
Figure 1
Figure 2
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, V
DD
= 3.3V.
3.3V I/O OUTPUT LOAD EQUIVALENT
1.5V
OUTPUT
Zo= 50
50
14
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 2.5V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
1.25V
and Reference Level
Output Load
See Figures 3 and 4
Z
O
= 50
1.25V
50
OUTPUT
1,667
5 pF
Including
jig and
scope
1,538
OUTPUT
+2.5V
Figure 3
Figure 4
2.5V I/O OUTPUT LOAD EQUIVALENT
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Rev. B
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
6.5
7.5
Symbol
Parameter
Min.
Max.
Min. Max.
Unit
fmax
Clock Frequency
--
133
--
117
MHz
t
KC
Cycle Time
7.5
--
8.5
--
ns
t
KH
Clock High Time
2.2
--
2.5
--
ns
t
KL
Clock Low Time
2.2
--
2.5
--
ns
t
KQ
Clock Access Time
--
6.5
--
7.5
ns
t
KQX
(2)
Clock High to Output Invalid
2.5
--
2.5
--
ns
t
KQLZ
(2,3)
Clock High to Output Low-Z
2.5
--
2.5
--
ns
t
KQHZ
(2,3)
Clock High to Output High-Z
--
3.8
--
4.0
ns
t
OEQ
Output Enable to Output Valid
--
3.2
--
3.4
ns
t
OELZ
(2,3)
Output Enable to Output Low-Z
0
--
0
--
ns
t
OEHZ
(2,3)
Output Disable to Output High-Z
--
3.5
--
3.5
ns
t
AS
Address Setup Time
1.5
--
1.5
--
ns
t
WS
Read/Write Setup Time
1.5
--
1.5
--
ns
t
CES
Chip Enable Setup Time
1.5
--
1.5
--
ns
t
SE
Clock Enable Setup Time
1.5
--
1.5
--
ns
t
ADVS
Address Advance Setup Time
1.5
--
1.5
--
ns
t
DS
Data Setup Time
1.5
--
1.5
--
ns
t
AH
Address Hold Time
0.5
--
0.5
--
ns
t
HE
Clock Enable Hold Time
0.5
--
0.5
--
ns
t
WH
Write Hold Time
0.5
--
0.5
--
ns
t
CEH
Chip Enable Hold Time
0.5
--
0.5
--
ns
t
ADVH
Address Advance Hold Time
0.5
--
0.5
--
ns
t
DH
Data Hold Time
0.5
--
0.5
--
ns
t
PDS
ZZ High to Power Down
--
2
--
2
cyc
t
PUS
ZZ Low to Power Down
--
2
--
2
cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
16
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
SLEEP MODE TIMING
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
I
SB
2
Current during SLEEP MODE
ZZ
V
IH
60
mA
t
PDS
ZZ active to input ignored
2
cycle
t
PUS
ZZ inactive to input sampled
2
cycle
t
ZZI
ZZ active to SLEEP current
2
cycle
t
RZZI
ZZ inactive to exit SLEEP current
0
ns
Don't Care
Deselect or Read Only
Deselect or Read Only
t
RZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
I
SB2
ZZ setup cycle
ZZ recovery cycle
Normal
operation
cycle
t
PDS
t
PUS
t
ZZI
High-Z
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Rev. B
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
READ CYCLE TIMING
CLK
ADV
Address
WRITE
CKE
CE
OE
Data Out
A1
A2
A3
t
KH
t
KL
t
KC
Don't Care
Undefined
NOTES:
WRITE
= L means
WE
= L and
BW
x = L
WE
= L and
BW
X = L
CE
= L means
CE
1 = L, CE2 = H and
CE
2 = L
CE
= H means
CE
1 = H, or
CE
1 = L and
CE
2 = H, or
CE
1 = L and CE2 = L
t
SE
t
HE
t
AS
t
AH
t
WS
t
WH
t
CES
t
CEH
t
ADVS
t
ADVH
t
KQX
Q3-3
Q3-4
Q3-2
Q3-1
Q2-4
Q2-3
Q2-2
Q2-1
t
OEHZ
t
KQHZ
t
KQ
t
OEQ
Q1-1
t
OEHZ
18
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
WRITE CYCLE TIMING
CLK
ADV
Address
WRITE
CKE
CE
OE
Data In
Data Out
A1
A2
A3
t
KH
t
KL
t
KC
t
SE
t
HE
Don't Care
Undefined
NOTES:
WRITE
= L means
WE
= L and
BW
x = L
WE
= L and
BW
X = L
CE
= L means
CE
1 = L, CE2 = H and
CE
2 = L
CE
= H means
CE
1 = H, or
CE
1 = L and
CE
2 = H, or
CE
1 = L and CE2 = L
Q0-4
t
DS
t
DH
D3-3
D3-4
D3-2
D3-1
D2-4
D2-3
D2-2
D2-1
D1-1
t
OEHZ
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Rev. B
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
SINGLE READ/WRITE CYCLE TIMING
CLK
CKE
Address
WRITE
CE
ADV
OE
Data Out
Data In
t
SE
t
HE
t
KH
t
KL
t
KC
Don't Care
Undefined
NOTES:
WRITE
= L means
WE
= L and
BW
x = L
CE
= L means
CE
1 = L, CE2 = H and
CE
2 = L
CE
= H means
CE
1 = H, or
CE
1 = L and
CE
2 = H, or
CE
1 = L and CE2 = L
A1 A2 A3
A4 A5 A6 A7
A8 A9
D5
D2
t
OELZ
t
OEQ
Q1 Q3 Q4
Q6
Q7
t
DS
t
DH
20
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Rev. B
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
CKE
CKE
CKE
CKE
CKE
OPERATION TIMING
A1 A2 A3
A4 A5
A6
Q1
CLK
CKE
Address
WRITE
CE
ADV
OE
Data Out
Data In
D2
t
SE
t
HE
t
KH
t
KL
t
KC
t
KQLZ
t
KQHZ
t
KQ
t
DH
t
DS
Don't Care
Undefined
NOTES:
WRITE
= L means
WE
= L and
BW
x = L
CE
= L means
CE
1 = L, CE2 = H and
CE
2 = L
CE
= H means
CE
1 = H, or
CE
1 = L and
CE
2 = H, or
CE
1 = L and CE2 = L
Q3
Q4
D5
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Rev. B
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
CE
CE
CE
CE
CE
OPERATION TIMING
Don't Care
Undefined
CLK
CKE
Address
WRITE
CE
ADV
OE
Data Out
Data In
t
SE
t
HE
t
KH
t
KL
t
KC
NOTES:
WRITE
= L means
WE
= L and
BW
x = L
CE
= L means
CE
1 = L, CE2 = H and
CE
2 = L
CE
= H means
CE
1 = H, or
CE
1 = L and
CE
2 = H, or
CE
1 = L and CE2 = L
A1 A2
A3
A4
A5
D5
D3
t
DH
t
DS
t
OELZ
t
OEQ
Q1 Q2
Q4
t
KQHZ
t
KQLZ
t
KQ
22
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08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61NLFX and IS61NVFX have a serial boundary scan
Test Access Port (TAP) in the PBGA package only. (Not
available in TQFP package.) This port operates in accor-
dance with IEEE Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
of the SRAM. The TAP controller operates in a manner that
does not conflict with the performance of other devices
using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature. To
disable the TAP controller, TCK must be tied LOW (V
SS
) to
prevent clocking of the device. TDI and TMS are internally
pulled up and may be disconnected. They may alternately
be connected to V
DD
through a pull-up resistor. TDO should
be left disconnected. On power-up, the device will start in a
reset state which will not interfere with the device operation.
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any
register. The register between TDI and TDO is chosen by
the instruction loaded into the TAP instruction register.
For information on instruction register loading, see the
TAP Controller State Diagram. TDI is internally pulled up
and can be disconnected if the TAP is unused in an
application. TDI is connected to the Most Significant Bit
(MSB) on any register.
31 30 29
. . .
2 1 0
2 1 0
0
x
. . . . .
2 1 0
Bypass Register
Instruction Register
Identification Register
Boundary Scan Register*
TAP CONTROLLER
Selection Circuitry
Selection Circuitry
TDO
TDI
TCK
TMS
TAP CONTROLLER BLOCK DIAGRAM
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IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB) of
any register.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (V
DD
) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on the
TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO pins. (See TAP Controller
Block Diagram) At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with
the IDCODE instruction if the controller is placed in a reset
state as previously described.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary "01" pattern
to allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register
is set LOW (V
SS
) when the BYPASS instruction is ex-
ecuted.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed
between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE
command is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
Scan Register Sizes
Register
Bit Size
Bit Size
Bit Size
Name
(x18)
(x36)
(x72)
Instruction
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary Scan
75
75
TBD
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field
Description
256K x 72
512K x 36
1M x 18
Revision Number (31:28)
Reserved for version number.
xxxx
xxxx
xxxx
Device Depth (27:23)
Defines depth of SRAM. 512K or 1M
00110
00111
01000
Device Width (22:18)
Defines Width of the SRAM. x72, x36 or x18
00101
00100
00011
ISSI Device ID (17:12)
Reserved for future use.
xxxx
xxxxx
xxxxx
ISSI JEDEC ID (11:1)
Allows unique identification of SRAM vendor.
0011010101
00011010101
00011010101
ID Register Presence (0)
Indicate the presence of an ID register.
1
1
1
24
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08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
TAP INSTRUCTION SET
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM is
not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output
buffers. The SRAM does not implement the 1149.1 com-
mands EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; instead it performs a capture of the
Inputs and Output ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed
between TDI and TDO. During this state, instructions are
shifted from the instruction register through the TDI and
TDO pins. To execute an instruction once it is shifted in,
the TAP controller must be moved into the Update-IR
state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When
an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is a difference between
the instructions, unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented, so the TAP controller is not fully 1149.1 compli-
ant. When the SAMPLE/PRELOAD instruction is loaded
to the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and
output pins is captured in the boundary scan register.
It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clock runs more than an order of magnitude faster.
Because of the clock frequency differences, it is possible
that during the Capture-DR state, an input or output will
under-go a transition. The TAP may attempt a signal
capture while in transition (metastable state). The device
will not be harmed, but there is no guarantee of the value
that will be captured or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be
stabilized long enough to meet the TAP controller's
capture set-up plus hold times (t
CS
and t
CH
). To insure that
the SRAM clock input is captured correctly, designs need
a way to stop (or slow) the clock during a SAMPLE/
PRELOAD instruction. If this is not an issue, it is possible
to capture all other signals and simply ignore the value of
the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Update-DR
state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
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Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
INSTRUCTION CODES
Code
Instruction
Description
000
EXTEST
Captures the Input/Output ring contents. Places the boundary scan register between
the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
001
IDCODE
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
010
SAMPLE-Z
Captures the Input/Output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
011
RESERVED
Do Not Use: This instruction is reserved for future use.
100
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation. This instruction does not implement
1149.1 preload function and is therefore not 1149.1 compliant.
101
RESERVED
Do Not Use: This instruction is reserved for future use.
110
RESERVED
Do Not Use: This instruction is reserved for future use.
111
BYPASS
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test/Idle
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
TAP CONTROLLER STATE DIAGRAM
26
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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
TAP Electrical Characteristics Over the Operating Range
(1,2)
Symbol
Parameter
Test Conditions
Min.
Max.
Units
V
OH1
Output HIGH Voltage
I
OH
= 2.0 mA
1.7
--
V
V
OH2
Output HIGH Voltage
I
OH
= 100
A
2.1
--
V
V
OL1
Output LOW Voltage
I
OL
= 2.0 mA
--
0.7
V
V
OL2
Output LOW Voltage
I
OL
= 100
A
--
0.2
V
V
IH
Input HIGH Voltage
1.7
V
DD
+0.3
V
V
IL
Input LOW Voltage
0.3
0.7
V
I
X
Input Leakage Current
V
SS
V I
V
DDQ
10
10
A
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: V
IH
(AC)
V
DD
+1.5V for t
t
TCYC
/2,
Undershoot: V
IL
(AC)
0.5V for t
t
TCYC
/2,
Power-up: V
IH
< 2.6V and V
DD
< 2.4V and V
DDQ
< 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS
(1,2)
(OVER OPERATING RANGE)
Symbol Parameter
Min.
Max.
Unit
t
TCYC
TCK Clock cycle time
100
--
ns
f
TF
TCK Clock frequency
--
10
MHz
t
TH
TCK Clock HIGH
40
--
ns
t
TL
TCK Clock LOW
40
--
ns
t
TMSS
TMS setup to TCK Clock Rise
10
--
ns
t
TDIS
TDI setup to TCK Clock Rise
10
--
ns
t
CS
Capture setup to TCK Rise
10
--
ns
t
TMSH
TMS hold after TCK Clock Rise
10
--
ns
t
TDIH
TDI Hold after Clock Rise
10
--
ns
t
CH
Capture hold after Clock Rise
10
--
ns
t
TDOV
TCK LOW to TDO valid
--
20
ns
t
TDOX
TCK LOW to TDO invalid
0
--
ns
Notes:
1. t
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
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Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
DON'T CARE
UNDEFINED
TCK
TMS
TDI
TDO
t
THTL
t
TLTH
t
THTH
t
MVTH
t
THMX
t
DVTH
t
THDX
1 2 3 4 5 6
t
TLOX
t
TLOV
TAP TIMING
20 pF
TDO
GND
50
Vtrig
Z
0
= 50
TAP Output Load Equivalent
TAP AC TEST CONDITIONS (2.5V/3.3V)
Input pulse levels
0 to 2.5V/0 to 3.0V
Input rise and fall times
1ns
Input timing reference levels
1.25V/1.5V
Output reference levels
1.25V/1.5V
Test load termination supply voltage
1.25V/1.5V
Vtrig
1.25V/1.5V
28
Integrated Silicon Solution, Inc. -- www.issi.com --
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Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
209 BOUNDARY SCAN ORDER (256K X 72)
T B D
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Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
165 PBGA BOUNDARY SCAN ORDER (x 36)
Signal Bump
Signal
Bump
Signal
Bump
Signal
Bump
Bit #
Name
ID
Bit #
Name
ID
Bit #
Name
ID
Bit #
Name
ID
1
MODE
1R
21
DQb
11G
41
NC
1A
61
DQd
1J
2
NC
6N
22
DQb
11F
42
CE
2
6A
62
DQd
1K
3
NC
11P
23
DQb
11E
43
BW
a
5B
63
DQd
1L
4
A
8P
24
DQb
11D
44
BW
b
5A
64
DQd
1M
5
A
8R
25
DQb
10G
45
BW
c
4A
65
DQd
2J
6
A
9R
26
DQb
10F
46
BW
d
4B
66
DQd
2K
7
A
9P
27
DQb
10E
47
CE2
3B
67
DQd
2L
8
A
10P
28
DQb
10D
48
CE
3A
68
DQd
2M
9
A
10R
29
DQb
11C
49
A
2A
69
DQd
1N
10
A
11R
30
NC
11A
50
A
2B
70
A
3P
11
ZZ
11H
31
A
10A
51
NC
1B
71
A
3R
12
DQa
11N
32
A
10B
52
DQc
1C
72
A
4R
13
DQa
11M
33
A
9A
53
DQc
1D
73
A
4P
14
DQa
11L
34
A
9B
54
DQc
1E
74
A1
6P
15
DQa
11K
35
ADV
8A
55
DQc
1F
75
A0
6R
16
DQa
11J
36
OE
8B
56
DQc
1G
17
DQa
10M
37
CKE
7A
57
DQc
2D
18
DQa
10L
38
WE
7B
58
DQc
2E
19
DQa
10K
39
CLK
6B
59
DQc
2F
20
DQa
10J
40
NC
11B
60
DQc
2G
30
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Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
165 PBGA BOUNDARY SCAN ORDER (x 18)
Signal Bump
Signal
Bump
Signal
Bump
Signal
Bump
Bit #
Name
ID
Bit #
Name
ID
Bit #
Name
ID
Bit #
Name
ID
1
MODE
1R
21
DQa
11G
41
NC
1A
61
DQb
1J
2
NC
6N
22
DQa
11F
42
CE
2
6A
62
DQb
1K
3
NC
11P
23
DQa
11E
43
BW
a
5B
63
DQb
1L
4
A
8P
24
DQa
11D
44
NC
5A
64
DQb
1M
5
A
8R
25
DQa
11C
45
BW
b
4A
65
DQb
1N
6
A
9R
26
NC
10F
46
NC
4B
66
NC
2K
7
A
9P
27
NC
10E
47
CE2
3B
67
NC
2L
8
A
10P
28
NC
10D
48
CE
3A
68
NC
2M
9
A
10R
29
NC
10G
49
A
2A
69
NC
2J
10
A
11R
30
A
11A
50
A
2B
70
A
3P
11
ZZ
11H
31
A
10A
51
NC
1B
71
A
3R
12
NC
11N
32
A
10B
52
NC
1C
72
A
4R
13
NC
11M
33
A
9A
53
NC
1D
73
A
4P
14
NC
11L
34
A
9B
54
NC
1E
74
A1
6P
15
NC
11K
35
ADV
8A
55
NC
1F
75
A0
6R
16
NC
11J
36
OE
8B
56
NC
1G
17
DQa
10M
37
CKE
7A
57
DQb
2D
18
DQa
10L
38
WE
7B
58
DQb
2E
19
DQa
10K
39
CLK
6B
59
DQb
2F
20
DQa
10J
40
NC
11B
60
DQb
2G
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Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
ORDERING INFORMATION (V
DD
= 3.3V/V
DDQ
= 2.5V- 3.3V)
Commercial Range: 0C to +70C
Access Time
Order Part Number
Package
512Kx36
6.5
IS61NLF51236-6.5TQ
100 TQFP
IS61NLF51236-6.5B3
165 PBGA
7.5
IS61NLF51236-7.5TQ
100 TQFP
IS61NLF51236-7.5B3
165 PBGA
1Mx18
6.5
IS61NLF102418-6.5TQ
100 TQFP
IS61NLF102418-6.5B3
165 PBGA
7.5
IS61NLF102418-7.5TQ
100 TQFP
IS61NLF102418-7.5B3
165 PBGA
Industrial Range: -40C to +85C
Access Time
Order Part Number
Package
256Kx72
6.5
IS61NLF25672-6.5B1I
209 PBGA
7.5
IS61NLF25672-7.5B1I
209 PBGA
512Kx36
6.5
IS61NLF51236-6.5TQI
100 TQFP
IS61NLF51236-6.5B3I
165 PBGA
7.5
IS61NLF51236-7.5TQI
100 TQFP
IS61NLF51236-7.5TQLI
100 TQFP, Lead-free
IS61NLF51236-7.5B3I
165 PBGA
1Mx18
6.5
IS61NLF102418-6.5TQI
100 TQFP
IS61NLF102418-6.5B3I
165 PBGA
7.5
IS61NLF102418-7.5TQI
100 TQFP
IS61NLF102418-7.5B3I
165 PBGA
32
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
08/26/05
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI
ORDERING INFORMATION (V
DD
= 2.5V /V
DDQ
= 2.5V)
Commercial Range: 0C to +70C
Access Time
Order Part Number
Package
512Kx36
6.5
IS61NVF51236-6.5TQ
100 TQFP
IS61NVF51236-6.5B3
165 PBGA
7.5
IS61NVF51236-7.5TQ
100 TQFP
IS61NVF51236-7.5B3
165 PBGA
1Mx18
6.5
IS61NVF102418-6.5TQ
100 TQFP
IS61NVF102418-6.5B3
165 PBGA
7.5
IS61NVF102418-7.5TQ
100 TQFP
IS61NVF102418-7.5B3
165 PBGA
Industrial Range: -40C to +85C
Access Time
Order Part Number
Package
256Kx72
6.5
IS61NVF25672-6.5B1I
209 PBGA
7.5
IS61NVF25672-7.5B1I
209 PBGA
512Kx36
6.5
IS61NVF51236-6.5TQI
100 TQFP
IS61NVF51236-6.5B3I
165 PBGA
7.5
IS61NVF51236-7.5TQI
100 TQFP
IS61NVF51236-7.5B3I
165 PBGA
1Mx18
6.5
IS61NVF102418-6.5TQI
100 TQFP
IS61NVF102418-6.5B3I
165 PBGA
7.5
IS61NVF102418-7.5TQI
100 TQFP
IS61NVF102418-7.5B3I
165 PBGA
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
08/22/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Mini Ball Grid Array - 209 Ball BGA
Package Code: B
(14 mm x 22mm Body, 1.0 mm Ball Pitch)
Notes:
1. Controlling dimensions are in millimeters.
11
10 9 8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8 9 10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
Y
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
Y
b (209X)
e
e
A1
A2
A3
SEATING PLANE
E
D D1
E1
A
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min.
Typ. Max.
N0.
Leads
209
A
--
--
1.95
--
--
0.077
A1
0.40 0.50 0.60
0.016 0.020 0.024
A2
--
0.54
--
--
0.021
--
A3
0.65
0.70
0.75
0.026 0.028 0.030
D
21.90 22.00 22.10
0.862 0.866 0.870
D1
18.00 BSC
0.709 BSC
E
13.90 14.00 14.10
0.547 0.551 0.555
E1
10.00 BSC
0.394 BSC
e
1.00BSC
0.039BSC
b
0.50
0.60
0.70
0.020 0.024 0.028
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
06/11/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
11 10 9 8 7 6 5 4 3 2 1
A1 CORNER
BOTTOM VIEW
D D1
e
e
E1
E
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER
TOP VIEW
A2
A
A1
b (165X)
Ball Grid Array
Package Code: B (165-pin)
Notes:
1. Controlling dimensions are in millimeters.
BGA - 13mm x 15mm
MILLIMETERS
INCHES
Sym.
Min.
Nom.
Max.
Min.
Nom.
Max.
N0.
Leads
165
165
A
--
--
1.20
--
--
0.047
A1
0.25
0.33
0.40
0.010
0.013
0.016
A2
--
0.79
--
--
0.031
--
D
14.90
15.00
15.10
0.587
0.591
0.594
D1
13.90
14.00
14.10
0.547
0.551
0.555
E
12.90
13.00
13.10
0.508
0.512
0.516
E1
9.90
10.00
10.10
0.390
0.394
0.398
e
--
1.00
--
--
0.039
--
b
0.40
0.45
0.50
0.016
0.018
0.020
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PACKAGING INFORMATION
ISSI
PK13197LQ Rev. D 05/08/03
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
Thin Quad Flat Pack (TQ)
Millimeters
Inches
Millimeters
Inches
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
100
128
A
--
1.60
--
0.063
--
1.60
--
0.063
A1
0.05
0.15
0.002
0.006
0.05
0.15
0.002
0.006
A2
1.35
1.45
0.053
0.057
1.35
1.45
0.053
0.057
b
0.22
0.38
0.009
0.015
0.17
0.27
0.007
0.011
D
21.90
22.10
0.862
0.870
21.80
22.20
0.858
0.874
D1
19.90
20.10
0.783
0.791
19.90
20.10
0.783
0.791
E
15.90
16.10
0.626
0.634
15.80
16.20
0.622
0.638
E1
13.90
14.10
0.547
0.555
13.90
14.10
0.547
0.555
e
0.65 BSC
0.026 BSC
0.50 BSC
0.020 BSC
L
0.45
0.75
0.018
0.030
0.45
0.75
0.018
0.030
L1
1.00 REF.
0.039 REF.
1.00 REF.
0.039 REF.
C
0
o
7
o
0
o
7
o
0
o
7
o
0
o
7
o
Notes:
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
3. Controlling dimension:
millimeters.
D
D1
E
E1
1
N
A2
A
A1
e
b
SEATING
PLANE
C
L1
L
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