Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

FEATURES

· 100 percent bus utilization

· No wait cycles between Read and Write

· Internal self-timed write cycle

· Individual Byte Write Control

· Single R/W (Read/Write) control pin

· Clock controlled, registered address,

data and control

· Interleaved or linear burst sequence control using

MODE input

· Three chip enables for simple depth expansion

and address pipelining

· Power Down mode

· Common data inputs and data outputs

CKE

pin to enable clock and suspend operation

· JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

· Power supply:

NVP: V

2.5V (± 5%), V

DDQ

2.5V (± 5%)

NLP: V

3.3V (± 5%), V

DDQ

3.3V/2.5V (± 5%)

· Industrial temperature available

· Lead-free available

DESCRIPTION

The 4 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 128K words by 32 bits, 128K words by 36 bits,
and 256K words by 18 bits, fabricated with

ISSI

's advanced

CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.

All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when

is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.

128K x 32, 128K x 36, and 256K x 18
4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

PRELIMINARY INFORMATION

SEPTEMBER 2005

FAST ACCESS TIME

Symbol

Parameter

-250

-200

Units

Clock Access Time

2.6

3.1

Cycle Time

Frequency

250

200

MHz

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

BLOCK DIAGRAM

ADV

}

BWY

(X=a,b,c,d or a,b)

CE2

CONTROL

LOGIC

128Kx32;
128Kx36;

256Kx18

MEMORY ARRAY

WRITE

ADDRESS

WRITE

ADDRESS

CONTROL

LOGIC

OUTPUT

BUFFER

ADDRESS

x 32/x 36: A [0:16] or
x 18: A [0:17]

CLK

CKE

A2-A16 or A2-A17

A0-A1

A'0-A'1

BURST

ADDRESS

COUNTER

MODE

DATA-IN

CONTROL

32, 36 or 18

DQx/DQPx

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

PIN CONFIGURATION -- 128K

36, 165-Ball PBGA (TOP VIEW)

CKE

ADV

CE2

CLK

DQPc

DDQ

DQPb

DQc

DDQ

DQb

DQc

DDQ

DQb

DQc

DDQ

DQb

DQc

DDQ

DQb

DQd

DDQ

DQa

DQd

DDQ

DQa

DQd

DDQ

DQa

DQd

DDQ

DQa

DQPd

DDQ

DQPa

A1*

MODE

A0*

Note:

A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

Pin Name

Address Inputs

A0, A1

Synchronous Burst Address Inputs

ADV

Synchronous Burst Address Advance/
Load

Synchronous Read/Write Control
Input

CLK

Synchronous Clock

CKE

Clock Enable

CE2

, CE2 Synchronous Chip Enable

x (x=a-d)

Synchronous Byte Write Inputs

Output Enable

Power Sleep Mode

MODE

Burst Sequence Selection

3.3V/2.5V Power Supply

No Connect

DQx

Data Inputs/Outputs

DQPx

Parity Data I/O

DDQ

Isolated output Power Supply
3.3V/2.5V

Ground

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

119-PIN PBGA PACKAGE CONFIGURATION 128K x 36 (TOP VIEW)

DQc

DQPc

Vss

DQc

Vss

DDQ

DQc

DDQ

DQd

DDQ

DQd

Vss

DQPd

CE2

MODE

Vss

DDQ

DQd

CKE

CLK

ADV

DQPa

DQa

DQb

DQPb

DDQ

DQa

DDQ

DQa

DDQ

DQb

DDQ

DQb

DDQ

Note:

A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

Pin Name

Address Inputs

A0, A1

Synchronous Burst Address Inputs

ADV

Synchronous Burst Address Advance/
Load

Synchronous Read/Write Control Input

CLK

Synchronous Clock

CKE

Clock Enable

Synchronous Chip Select

CE2

Synchronous Chip Select

x (x=a-d)

Synchronous Byte Write Inputs

Output Enable

Power Sleep Mode

MODE

Burst Sequence Selection

Power Supply

Ground

No Connect

DQa-DQd

Data Inputs/Outputs

DQPa-Pd

Parity Data I/O

DDQ

Output Power Supply

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

165-PIN PBGA PACKAGE CONFIGURATION 256K x 18 (TOP VIEW)

PIN DESCRIPTIONS

Symbol

Pin Name

Address Inputs

A0, A1

Synchronous Burst Address Inputs

ADV

Synchronous Burst Address Advance/
Load

Synchronous Read/Write Control
Input

CLK

Synchronous Clock

CKE

Clock Enable

CE2

, CE2 Synchronous Chip Enable

x (x=a,b)

Synchronous Byte Write Inputs

Output Enable

Power Sleep Mode

CKE

Vss

DQb

Vss

DQb

Vss

DQb

DDQ

DQb

DQa

DQb

Vss

DQb

Vss

DQPb

Vss

MODE

CE2

Vss

DDQ

Vss

CLK

Vss

ADV

DDQ

DQa

DQPa

Note:

A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

MODE

Burst Sequence Selection

3.3V/2.5V Power Supply

No Connect

DQx

Data Inputs/Outputs

DQPx

Parity Data I/O

DDQ

Isolated output Power Supply
3.3V/2.5V

Ground

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

119-PIN PBGA PACKAGE CONFIGURATION 256K x 18 (TOP VIEW)

PIN DESCRIPTIONS

Symbol

Pin Name

Address Inputs

A0, A1

Synchronous Burst Address Inputs

ADV

Synchronous Burst Address Advance/
Load

Synchronous Read/Write Control Input

CLK

Synchronous Clock

CKE

Clock Enable

Synchronous Chip Select

CE2

Synchronous Chip Select

x (x=a,b)

Synchronous Byte Write Inputs

Output Enable

Power Sleep Mode

MODE

Burst Sequence Selection

Power Supply

Ground

No Connect

DQa-DQb

Data Inputs/Outputs

DQPa-Pb

Parity Data I/O

DDQ

Output Power Supply

DQb

Vss

DQb

Vss

DDQ

DQb

DDQ

DQb

DDQ

DQb

Vss

DQPb

CE2

MODE

Vss

DDQ

CKE

CLK

ADV

DQPa

DQa

DDQ

DQa

DDQ

DQa

DDQ

Note:

A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

PIN CONFIGURATION

100-Pin TQFP

128K x 32

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DQPb

DQb

DDQ

Vss

DQb

Vss

DDQ

DQb

Vss

DQa

DDQ

Vss

DQa

Vss

DDQ

DQa

DQPa

DQPc

DQc

DDQ

Vss

DQc

Vss

DDQ

DQc

Vss

DQd

DDQ

Vss

DQd

Vss

DDQ

DQd

DQPd

CE2

BWd

BWc

BWb

BWa

CE2

Vss

CLK

CKE

MODE

Vss

128K x 36

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

Synchronous Address Inputs

CLK

Synchronous Clock

ADV

Synchronous Burst Address Advance

Synchronous Byte Write Enable

Write Enable

CKE

Clock Enable

Vss

Ground for Core

Not Connected

, CE2,

CE2

Synchronous Chip Enable

Output Enable

DQa-DQd

Synchronous Data Input/Output

DQPa-DQPd

Parity Data I/O

MODE

Burst Sequence Selection

+3.3V/2.5V Power Supply

Ground for output Buffer

DDQ

Isolated Output Buffer Supply: +3.3V/2.5V

Snooze Enable

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DQb

DDQ

Vss

DQb

Vss

DDQ

DQb

Vss

DQa

DDQ

Vss

DQa

Vss

DDQ

DQa

DQc

DDQ

Vss

DQc

Vss

DDQ

DQc

Vss

DQd

DDQ

Vss

DQd

Vss

DDQ

DQd

CE2

BWd

BWc

BWb

BWa

CE2

Vss

CLK

CKE

MODE

Vss

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

PIN CONFIGURATION

100-Pin TQFP

256K x 18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DDQ

Vss

DQPa

DQa

Vss

DDQ

DQa

Vss

DQa

DDQ

Vss

DQa

Vss

DDQ

Vss

DQb

Vss

DDQ

DQb

Vss

DQb

DDQ

Vss

DQb

DQPb

Vss

DDQ

CE2

Vss

CLK

CKE

ADV

MODE

Vss

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

Synchronous Address Inputs

CLK

Synchronous Clock

ADV

Synchronous Burst Address Advance

Synchronous Byte Write Enable

Write Enable

CKE

Clock Enable

Vss

Ground for Core

Not Connected

, CE2,

CE2

Synchronous Chip Enable

Output Enable

DQa-DQd

Synchronous Data Input/Output

DQPa-DQPd

Parity Data I/O

MODE

Burst Sequence Selection

+3.3V/2.5V Power Supply

Ground for output Buffer

DDQ

Isolated Output Buffer Supply: +3.3V/2.5V

Snooze Enable

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

SYNCHRONOUS TRUTH TABLE

(1)

Address

Operation

Used

CE2

ADV

CKE

CLK

Not Selected

N/A

Not Selected

N/A

Not Selected

N/A

Not Selected Continue

N/A

Begin Burst Read

External Address

Continue Burst Read

Next Address

NOP/Dummy Read

External Address

Dummy Read

Next Address

Begin Burst Write

External Address

Continue Burst Write

Next Address

NOP/Write Abort

N/A

Write Abort

Next Address

Ignore Clock

Current Address

Notes:

1. "X" means don't care.
2. The rising edge of clock is symbolized by

3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.

= L means Write operation in Write Truth Table.

= H means Read operation in Write Truth Table.

5. Operation finally depends on status of asynchronous pins (ZZ and

BURST

READ

DESELECT

BURST

WRITE

BEGIN

READ

BEGIN

WRITE

READ

WRITE

READ

WRITE

BURST

READ

WRITE

BURST

WRITE

READ

STATE DIAGRAM

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

ASYNCHRONOUS TRUTH TABLE

(1)

Operation

I/O STATUS

Sleep Mode

High-Z

Read

High-Z

Write

Din, High-Z

Deselected

High-Z

Notes:

1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with

, otherwise data bus

contention will occur.

3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.

WRITE TRUTH TABLE

(x18)

Operation

READ

WRITE BYTE a

WRITE BYTE b

WRITE ALL BYTEs

WRITE ABORT/NOP

Notes:

1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

INTERLEAVED BURST ADDRESS TABLE

(MODE = V

or NC)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1 A0

WRITE TRUTH TABLE

(x32/x36)

Operation

READ

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE ALL BYTEs

WRITE ABORT/NOP

Notes

1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

LINEAR BURST ADDRESS TABLE

(MODE = V

)

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

STG

Storage Temperature

65 to +150

°C

Power Dissipation

1.6

OUT

Output Current (per I/O)

100

, V

OUT

Voltage Relative to V

for I/O Pins

0.5 to V

DDQ

+ 0.5

Voltage Relative to V

for

0.5 to 4.6

for Address and Control Inputs

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however,

precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance
circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

0,0

1,0

0,1

A1', A0' = 1,1

OPERATING RANGE (IS61NLPx)

Range

Ambient Temperature

DDQ

Commercial

0°C to +70°C

3.3V ± 5%

3.3V / 2.5V ± 5%

Industrial

-40°C to +85°C

3.3V ± 5%

3.3V / 2.5V ± 5%

OPERATING RANGE (IS61NVPx)

Range

Ambient Temperature

DDQ

Commercial

0°C to +70°C

2.5V ± 5%

Industrial

-40°C to +85°C

2.5V ± 5%

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-250

-200

MAX

Symbol Parameter

Test Conditions

Temp. range

x18

x32/x36

x18

x32/x36

Unit

AC Operating

Device Selected,

Com.

225

200

Supply Current

= V

, ZZ

Ind.

250

210

All Inputs

0.2V or

0.2V,

Cycle Time

min.

Standby Current

Device Deselected,

Com.

TTL Input

= Max.,

Ind.

100

All Inputs

, f = Max.

SBI

Standby Current

Device Deselected,

Com.

CMOS Input

= Max.,

Ind.

+ 0.2V or

0.2V

typ.

(2)

f = 0

Sleep Mode

ZZ>V

Com.

Ind.

typ.

(2)

Note:
1. MODE pin has an internal pullup and should be tied to V

or V

. It exhibits ±100µA maximum leakage current when tied to

+ 0.2V or

0.2V.

2. Typical values are measured at V

= 3.3V, T

= 25

C and not 100% tested.

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

3.3V

2.5V

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

Output HIGH Voltage

= 4.0 mA (3.3V)

2.4

2.0

= 1.0 mA

(2.5V)

Output LOW Voltage

= 8.0 mA (3.3V)

0.4

= 1.0 mA (2.5V)

(1)

Input HIGH Voltage

2.0

+ 0.3

1.7

+ 0.3

(1)

Input LOW Voltage

0.3

0.8

0.3

0.7

Input Leakage Current

(1)

µA

Output Leakage Current

OUT

DDQ

= V

µA

Note:
1. Overshoot: V

(AC) < V

+ 2.0V (Pulse width less than t

/2). Undershoot: V

(AC) > -2V (Pulse width less than t

/2).

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

3.3V I/O AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

1.5 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

317

5 pF
Including
jig and
scope

351

OUTPUT

+3.3V

Figure 1

Figure 2

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25°C, f = 1 MHz, V

= 3.3V.

3.3V I/O OUTPUT LOAD EQUIVALENT

1.5V

OUTPUT

Zo= 50

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

READ/WRITE CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-250

-200

Symbol

Parameter

Min.

Max.

Min. Max.

Unit

fmax

Clock Frequency

250

200

MHz

Cycle Time

4.0

Clock High Time

1.7

Clock Low Time

1.7

Clock Access Time

2.6

3.1

KQX

(2)

Clock High to Output Invalid

0.8

1.5

KQLZ

(2,3)

Clock High to Output Low-Z

0.8

KQHZ

(2,3)

Clock High to Output High-Z

2.6

3.0

OEQ

Output Enable to Output Valid

2.8

3.1

OELZ

(2,3)

Output Enable to Output Low-Z

OEHZ

(2,3)

Output Disable to Output High-Z

2.6

3.0

Address Setup Time

1.2

1.4

Read/Write Setup Time

1.2

1.4

CES

Chip Enable Setup Time

1.2

1.4

Clock Enable Setup Time

1.2

1.4

ADVS

Address Advance Setup Time

1.2

1.4

Data Setup Time

1.2

1.4

Address Hold Time

0.3

0.4

Clock Enable Hold Time

0.3

0.4

Write Hold Time

0.3

0.4

CEH

Chip Enable Hold Time

0.3

0.4

ADVH

Address Advance Hold Time

0.3

0.4

Data Hold Time

0.3

0.4

PDS

ZZ High to Power Down

cyc

PUS

ZZ Low to Power Down

cyc

Notes:

1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

SLEEP MODE TIMING

SLEEP MODE ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Conditions

Min.

Max.

Unit

Current during SLEEP MODE

PDS

ZZ active to input ignored

cycle

PUS

ZZ inactive to input sampled

cycle

ZZI

ZZ active to SLEEP current

cycle

RZZI

ZZ inactive to exit SLEEP current

Don't Care

Deselect or Read Only

RZZI

CLK

Isupply

All Inputs

(except ZZ)

Outputs

(Q)

SB2

ZZ setup cycle

ZZ recovery cycle

Normal

operation

cycle

PDS

PUS

ZZI

High-Z

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

READ CYCLE TIMING

KQX

CLK

ADV

Address

WRITE

CKE

Data Out

Q3-3

Q3-4

Q3-2

Q3-1

Q2-4

Q2-3

Q2-2

Q2-1

Don't Care

Undefined

NOTES:

WRITE

= L means

= L and

x = L

= L and

X = L

= L means

1 = L, CE2 = H and

2 = L

= H means

1 = H, or

1 = L and

2 = H, or

1 = L and CE2 = L

OEHZ

CES

CEH

ADVS

ADVH

KQHZ

OEQ

OEHZ

Q1-1

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

ORDERING INFORMATION (V

= 3.3V/V

DDQ

= 2.5V/3.3V)

Commercial Range: 0°C to +70°C

Access Time

Order Part Number

Package

128Kx32

250

IS61NLP12832A-250TQ

100 TQFP

IS61NLP12832A-250B3

165 PBGA

IS61NLP12832A-250B2

119 PBGA

200

IS61NLP12832A-200TQ

100 TQFP

IS61NLP12832A-200B3

165 PBGA

IS61NLP12832A-200B2

119 PBGA

128Kx36

250

IS61NLP12836A-250TQ

100 TQFP

IS61NLP12836A-250B3

165 PBGA

IS61NLP12836A-250B2

119 PBGA

200

IS61NLP12836A-200TQ

100 TQFP

IS61NLP12836A-200B3

165 PBGA

IS61NLP12836A-200B2

119 PBGA

256Kx18

250

IS61NLP25618A-250TQ

100 TQFP

IS61NLP25618A-250B3

165 PBGA

IS61NLP25618A-250B2

119 PBGA

200

IS61NLP25618A-200TQ

100 TQFP

IS61NLP25618A-200B3

165 PBGA

IS61NLP25618A-200B2

119 PBGA

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C
09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

ORDERING INFORMATION (V

= 3.3V/V

DDQ

= 2.5V/3.3V)

Industrial Range: -40°C to +85°C

Access Time

Order Part Number

Package

128Kx32

250

IS61NLP12832A-250TQI

100 TQFP

IS61NLP12832A-250B3I

165 PBGA

IS61NLP12832A-250B2I

119 PBGA

200

IS61NLP12832A-200TQI

100 TQFP

IS61NLP12832A-200TQLI

100 TQFP, Lead-free

IS61NLP12832A-200B3I

165 PBGA

IS61NLP12832A-200B2I

119 PBGA

128Kx36

250

IS61NLP12836A-250TQI

100 TQFP

IS61NLP12836A-250B3I

165 PBGA

IS61NLP12836A-250B2I

119 PBGA

200

IS61NLP12836A-200TQI

100 TQFP

IS61NLP12836A-200TQLI

100 TQFP, Lead-free

IS61NLP12836A-200B3I

165 PBGA

IS61NLP12836A-200B2I

119 PBGA

256Kx18

250

IS61NLP25618A-250TQI

100 TQFP

IS61NLP25618A-250B3I

165 PBGA

IS61NLP25618A-250B2I

119 PBGA

200

IS61NLP25618A-200TQI

100 TQFP

IS61NLP25618A-200TQLI

100 TQFP, Lead-free

IS61NLP25618A-200B3I

165 PBGA

IS61NLP25618A-200B2I

119 PBGA

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. 00C

09/12/05

ISSI

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A

ORDERING INFORMATION (V

= 2.5V/V

DDQ

= 2.5V)

Commercial Range: 0°C to +70°C

Access Time

Order Part Number

Package

128Kx36

250

IS61NVP12836A-250TQ

100 TQFP

IS61NVP12836A-250B3

165 PBGA

IS61NVP12836A-250B2

119 PBGA

200

IS61NVP12836A-200TQ

100 TQFP

IS61NVP12836A-200B3

165 PBGA

IS61NVP12836A-200B2

119 PBGA

256Kx18

250

IS61NVP25618A-250TQ

100 TQFP

IS61NVP25618A-250B3

165 PBGA

IS61NVP25618A-250B2

119 PBGA

200

IS61NVP25618A-200TQ

100 TQFP

IS61NVP25618A-200B3

165 PBGA

IS61NVP25618A-200B2

119 PBGA

Industrial Range: -40°C to +85°C

Access Time

Order Part Number

Package

128Kx36

250

IS61NVP12836A-250TQI

100 TQFP

IS61NVP12836A-250B3I

165 PBGA

IS61NVP12836A-250B2I

119 PBGA

200

IS61NVP12836A-200TQI

100 TQFP

IS61NVP12836A-200B3I

165 PBGA

IS61NVP12836A-200B2I

119 PBGA

256Kx18

250

IS61NVP25618A-250TQI

100 TQFP

IS61NVP25618A-250B3I

165 PBGA

IS61NVP25618A-250B2I

119 PBGA

200

IS61NVP25618A-200TQI

100 TQFP

IS61NVP25618A-200B3I

165 PBGA

IS61NVP25618A-200B2I

119 PBGA

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. B
02/12/03

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Plastic Ball Grid Array
Package Code: B (119-pin)

Notes:

1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protrusion and
should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within

0.004 inches at the seating plane.

MILLIMETERS

INCHES

Sym.

Min.

Max.

Min.

Max.

N0.
Leads

119

2.41

0.095

0.50

0.70

0.020

0.028

0.80

1.00

0.032

0.039

1.30

1.70

0.051

0.067

0.56 BSC

0.022 BSC

0.60

0.90

0.024

0.035

21.80

22.20

0.858

0.874

20.32 BSC

0.800 BSC

19.40

19.60

0.764

0.772

13.80

14.20

0.543

0.559

7.62 BSC

0.300 BSC

11.90

12.10

0.469

0.476

1.27 BSC

0.050 BSC

SEATING PLANE

b (119X)

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

Rev. A
06/11/03

11 10 9 8 7 6 5 4 3 2 1

A1 CORNER

BOTTOM VIEW

D D1

1 2 3 4 5 6 7 8 9 10 11

A1 CORNER

TOP VIEW

b (165X)

Ball Grid Array
Package Code: B (165-pin)

Notes:
1. Controlling dimensions are in millimeters.

BGA - 13mm x 15mm

MILLIMETERS

INCHES

Sym.

Min.

Nom.

Max.

Min.

Nom.

Max.

N0.
Leads

165

1.20

0.047

0.25

0.33

0.40

0.010

0.013

0.016

0.79

0.031

14.90

15.00

15.10

0.587

0.591

0.594

13.90

14.00

14.10

0.547

0.551

0.555

12.90

13.00

13.10

0.508

0.512

0.516

9.90

10.00

10.10

0.390

0.394

0.398

1.00

0.039

0.40

0.45

0.50

0.016

0.018

0.020

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PACKAGING INFORMATION

ISSI

PK13197LQ Rev. D 05/08/03

TQFP (Thin Quad Flat Pack Package)
Package Code: TQ

Thin Quad Flat Pack (TQ)

Millimeters

Inches

Millimeters

Inches

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Ref. Std.

No. Leads (N)

100

128

1.60

0.063

1.60

0.063

0.05

0.15

0.002

0.006

0.05

0.15

0.002

0.006

1.35

1.45

0.053

0.057

1.35

1.45

0.053

0.057

0.22

0.38

0.009

0.015

0.17

0.27

0.007

0.011

21.90

22.10

0.862

0.870

21.80

22.20

0.858

0.874

19.90

20.10

0.783

0.791

19.90

20.10

0.783

0.791

15.90

16.10

0.626

0.634

15.80

16.20

0.622

0.638

13.90

14.10

0.547

0.555

13.90

14.10

0.547

0.555

0.65 BSC

0.026 BSC

0.50 BSC

0.020 BSC

0.45

0.75

0.018

0.030

0.45

0.75

0.018

0.030

1.00 REF.

0.039 REF.

1.00 REF.

0.039 REF.

Notes:
1. All dimensioning and

tolerancing conforms to
ANSI Y14.5M-1982.

2. Dimensions D1 and E1 do

not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.

3. Controlling dimension:

millimeters.

SEATING
PLANE

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61NVP12836A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61NVP12836A