Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
ADVANCE INFORMATION
Rev. 00B
09/25/01
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
IS61VPD51232 IS61VPD51236 IS61VPD10018
ISSI
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Linear burst sequence control using MODE input
Three chip enable option for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin TQFP and
119-pin PBGA package
Single +2.5V, 5% operation
Auto Power-down during deselect
Double cycle deselect
Snooze MODE for reduced-power standby
JTAG Boundary Scan for PBGA package
DESCRIPTION
The
ISSI
IS61VPD51232, IS61VPD51236, and
IS61VPD10018 are high-speed, low-power synchronous
static RAMs designed to provide burstable, high-performance
memory for communication and networking applications.
The IS61VPD51232 is organized as 524,288 words by 32 bits
and the IS61VPD51236 is organized as 524,288 words by
36 bits. The IS61VPD10018 is organized as 1,048,576
words by 18 bits. Fabricated with
ISSI
's advanced CMOS
technology, the device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit. All synchronous inputs
pass through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (
BWE
).input combined with one or more individual
byte write signals (
BWx
). In addition, Global Write (
GW
)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
512K x 32, 512K x 36, 1024K x 18
SYNCHRONOUS PIPELINED,
DOUBLE CYCLE DESELECT STATIC RAM
ADVANCE INFORMATION
SEPTEMBER 2001
FAST ACCESS TIME
Symbol
Parameter
-200
-166
Units
t
KQ
Clock Access Time
3.1
3.5
ns
t
KC
Cycle Time
5
6
ns
Frequency
200
166
MHz
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION
Rev. 00B
09/25/01
IS61VPD51232 IS61VPD51236 IS61VPD10018
ISSI
BLOCK DIAGRAM
19/20
BINARY
COUNTER
BWa
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
17/18
19/20
ADDRESS
REGISTER
CE
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BWd
CE
CE2
CE2
BWb
BWc
512Kx32; 512Kx36;
1024Kx18
MEMORY ARRAY
32, 36,
or 18
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
4
OE
DQa - DQd
32, 36,
or 18
32, 36,
or 18
A
(x32/x36)
(x32/x36/x18)
(x32/x36)
(x32/x36/x18)
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
ADVANCE INFORMATION
Rev. 00B
09/25/01
IS61VPD51232 IS61VPD51236 IS61VPD10018
ISSI
PIN CONFIGURATION
100-Pin TQFP
512K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE
, CE2,
CE2
Synchronous Chip Enable
CLK
Synchronous Clock
DQa-DQd
Synchronous Data Input/Output
GND
Ground
GW
Synchronous Global Write Enable
MODE
Burst Sequence Mode Selection
OE
Output Enable
V
CC
+2.5V Power Supply
V
CCQ
Isolated Output Buffer Supply:
+2.5V
ZZ
Snooze Enable
NC
DQb
DQb
VCCQ
GND
DQb
DQb
DQb
DQb
GND
VCCQ
DQb
DQb
GND
NC
VCC
ZZ
DQa
DQa
VCCQ
GND
DQa
DQa
DQa
DQa
GND
VCCQ
DQa
DQa
NC
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
DQc
DQc
VCCQ
GND
DQc
DQc
DQc
DQc
GND
VCCQ
DQc
DQc
NC
VCC
NC
GND
DQd
DQd
VCCQ
GND
DQd
DQd
DQd
DQd
GND
VCCQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
VCC
A
A
A
A
A
A
A
A
A
46 47 48 49 50
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION
Rev. 00B
09/25/01
IS61VPD51232 IS61VPD51236 IS61VPD10018
ISSI
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc
DQc
VCCQ
DQc
DQc
VCCQ
DQd
DQd
VCCQ
DQd
DQd
NC
NC
VCCQ
A
A
A
DQPc
DQc
DQc
DQc
DQc
VCC
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
A
A
A
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A
TDI
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
A
TCK
A
A
A
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A
TDO
A
A
A
DQPb
DQb
DQb
DQb
DQb
VCC
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
VCCQ
NC
NC
DQb
DQb
VCCQ
DQb
DQb
VCCQ
DQa
DQa
VCCQ
DQa
DQa
NC
ZZ
VCCQ
1
2
3
4
5
6
7
DQPb
DQb
DQb
VCCQ
GND
DQb
DQb
DQb
DQb
GND
VCCQ
DQb
DQb
GND
NC
VCC
ZZ
DQa
DQa
VCCQ
GND
DQa
DQa
DQa
DQa
GND
VCCQ
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
VCCQ
GND
DQc
DQc
DQc
DQc
GND
VCCQ
DQc
DQc
NC
VCC
NC
GND
DQd
DQd
VCCQ
GND
DQd
DQd
DQd
DQd
GND
VCCQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
VCC
A
A
A
A
A
A
A
A
A
46 47 48 49 50
512K x 36
119-pin PBGA (Top View)
100-Pin TQFP
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE
, CE2,
CE2
Synchronous Chip Enable
CLK
Synchronous Clock
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd
Parity Data Input/Output
GND
Ground
GW
Synchronous Global Write Enable
MODE
Burst Sequence Mode Selection
OE
Output Enable
TMS, TDI,
JTAG Boundary Scan Pins
TCK, TDO
V
CC
+2.5V Power Supply
V
CCQ
Isolated Output Buffer Supply:
+2.5V
ZZ
Snooze Enable
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
ADVANCE INFORMATION
Rev. 00B
09/25/01
IS61VPD51232 IS61VPD51236 IS61VPD10018
ISSI
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQb
NC
VCCQ
NC
DQb
VCCQ
NC
DQb
VCCQ
DQb
NC
NC
NC
VCCQ
A
A
A
NC
DQb
NC
DQb
NC
VCC
DQb
NC
DQb
NC
DQPb
A
A
TMS
A
A
A
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
MODE
A
TDI
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
TCK
A
A
A
GND
GND
GND
GND
GND
NC
GND
BWa
GND
GND
GND
NC
A
TDO
A
A
A
DQPa
NC
DQa
NC
DQa
VCC
NC
DQa
NC
DQa
NC
A
A
NC
VCCQ
NC
NC
NC
DQa
VCCQ
DQa
NC
VCCQ
DQa
NC
VCCQ
NC
DQa
NC
ZZ
VCCQ
1
2
3
4
5
6
7
1024K x 18
119-pin PBGA (Top View)
100-Pin TQFP
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE
, CE2,
CE2
Synchronous Chip Enable
CLK
Synchronous Clock
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPb
Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
GND
Ground
GW
Synchronous Global Write Enable
MODE
Burst Sequence Mode Selection
OE
Output Enable
TMS, TDI,
JTAG Boundary Scan Pins
TCK, TDO
V
CC
+2.5V Power Supply
V
CCQ
Isolated Output Buffer Supply:
+2.5V
ZZ
Snooze Enable
A
NC
NC
VCCQ
GND
NC
DQPa
DQa
DQa
GND
VCCQ
DQa
DQa
GND
NC
VCC
ZZ
DQa
DQa
VCCQ
GND
DQa
DQa
NC
NC
GND
VCCQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
VCCQ
GND
NC
NC
DQb
DQb
GND
VCCQ
DQb
DQb
NC
VCC
NC
GND
DQb
DQb
VCCQ
GND
DQb
DQb
DQPb
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
GND
VCC
A
A
A
A
A
A
A
A
A
46 47 48 49 50
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