Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

FEATURES

· Internal self-timed write cycle

· Individual Byte Write Control and Global Write

· Clock controlled, registered address, data and

control

· Linear burst sequence control using MODE input

· Three chip enable option for simple depth expansion

and address pipelining

· Common data inputs and data outputs

· JEDEC 100-Pin TQFP and

119-pin PBGA package

· Single +2.5V, ±5% operation

· Auto Power-down during deselect

· Single cycle deselect

· Snooze MODE for reduced-power standby

· JTAG Boundary Scan for PBGA package

DESCRIPTION

The

ISSI

IS61VPS51232, IS61VPS51236, and

IS61VPS10018 are high-speed, low-power synchronous
static RAMs designed to provide burstable, high-performance
memory for communication and networking applications.
The IS61VPS51232 is organized as 524,288 words by 32 bits
and the IS61VPS51236 is organized as 524,288 words by
36 bits. The IS61VPS10018 is organized as 1,048,576
words by 18 bits. Fabricated with

ISSI

's advanced CMOS

technology, the device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit. All synchronous inputs
pass through registers controlled by a positive-edge-
triggered single clock input.

Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (

BWE

).input combined with one or more individual

byte write signals (

BWx

). In addition, Global Write (

)

is available for writing all bytes at one time, regardless of
the byte write controls.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated
internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.

512K x 32, 512K x 36, 1024K x 18
SYNCHRONOUS PIPELINED,
SINGLE-CYCLE DESELECT STATIC RAM

ADVANCE INFORMATION

SEPTEMBER 2001

FAST ACCESS TIME

Symbol

Parameter

-200

-166

Units

Clock Access Time

3.1

3.5

Cycle Time

Frequency

200

166

MHz

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

PIN CONFIGURATION

100-Pin TQFP

512K x 32

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

Synchronous Address Inputs

ADSC

Synchronous Controller Address Status

ADSP

Synchronous Processor Address Status

ADV

Synchronous Burst Address Advance

BWa

BWd

Synchronous Byte Write Enable

BWE

Synchronous Byte Write Enable

, CE2,

CE2

Synchronous Chip Enable

CLK

Synchronous Clock

DQa-DQd

Synchronous Data Input/Output

GND

Ground

Synchronous Global Write Enable

MODE

Burst Sequence Mode Selection

Output Enable

+2.5V Power Supply

CCQ

Isolated Output Buffer Supply:
+2.5V

Snooze Enable

NC
DQb
DQb
VCCQ
GND
DQb
DQb
DQb
DQb
GND
VCCQ
DQb
DQb
GND
NC
VCC
ZZ
DQa
DQa
VCCQ
GND
DQa
DQa
DQa
DQa
GND
VCCQ
DQa
DQa
NC

CE2

BWd

BWc

BWb

BWa

CE2

VCC

GND

CLK

BWE

ADSC

ADSP

ADV

DQc
DQc

VCCQ

GND

DQc
DQc
DQc
DQc

GND

VCCQ

DQc
DQc

VCC

GND

DQd
DQd

VCCQ

GND

DQd
DQd
DQd
DQd

GND

VCCQ

DQd
DQd

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

GND

VCC

46 47 48 49 50

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

PIN CONFIGURATION

VCCQ

DQc

VCCQ

DQc

VCCQ

DQd

VCCQ

DQd

VCCQ

DQPc

DQc

VCC

DQd

DQPd

TMS

GND

BWc

GND

BWd

GND

MODE

TDI

ADSP

ADSC

VCC

ADV

VCC

CLK

BWE

VCC

TCK

GND

BWb

GND

BWa

GND

TDO

DQPb

DQb

VCC

DQa

DQPa

VCCQ

DQb

VCCQ

DQb

VCCQ

DQa

VCCQ

DQa

VCCQ

DQPb
DQb
DQb
VCCQ
GND
DQb
DQb
DQb
DQb
GND
VCCQ
DQb
DQb
GND
NC
VCC
ZZ
DQa
DQa
VCCQ
GND
DQa
DQa
DQa
DQa
GND
VCCQ
DQa
DQa
DQPa

CE2

BWd

BWc

BWb

BWa

CE2

VCC

GND

CLK

BWE

ADSC

ADSP

ADV

DQPc

DQc
DQc

VCCQ

GND

DQc
DQc
DQc
DQc

GND

VCCQ

DQc
DQc

VCC

GND

DQd
DQd

VCCQ

GND

DQd
DQd
DQd
DQd

GND

VCCQ

DQd
DQd

DQPd

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

GND

VCC

46 47 48 49 50

512K x 36

119-pin PBGA (Top View)

100-Pin TQFP

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

Synchronous Address Inputs

ADSC

Synchronous Controller Address Status

ADSP

Synchronous Processor Address Status

ADV

Synchronous Burst Address Advance

BWa

BWd

Synchronous Byte Write Enable

BWE

Synchronous Byte Write Enable

, CE2,

CE2

Synchronous Chip Enable

CLK

Synchronous Clock

DQa-DQd

Synchronous Data Input/Output

DQPa-DQPd

Parity Data Input/Output

GND

Ground

Synchronous Global Write Enable

MODE

Burst Sequence Mode Selection

Output Enable

TMS, TDI,

JTAG Boundary Scan Pins

TCK, TDO

+2.5V Power Supply

CCQ

Isolated Output Buffer Supply:
+2.5V

Snooze Enable

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

PIN CONFIGURATION

VCCQ

DQb

VCCQ

DQb

VCCQ

DQb

VCCQ

DQb

VCCQ

DQb

VCC

DQb

DQPb

TMS

GND

BWb

GND

MODE

TDI

ADSP

ADSC

VCC

ADV

VCC

CLK

BWE

VCC

TCK

GND

BWa

GND

TDO

DQPa

DQa

VCC

DQa

VCCQ

DQa

VCCQ

DQa

VCCQ

DQa

VCCQ

DQa

VCCQ

1024K x 18

119-pin PBGA (Top View)

100-Pin TQFP

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

Synchronous Address Inputs

ADSC

Synchronous Controller Address Status

ADSP

Synchronous Processor Address Status

ADV

Synchronous Burst Address Advance

BWa

BWd

Synchronous Byte Write Enable

BWE

Synchronous Byte Write Enable

, CE2,

CE2

Synchronous Chip Enable

CLK

Synchronous Clock

DQa-DQd

Synchronous Data Input/Output

DQPa-DQPb

Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8

GND

Ground

Synchronous Global Write Enable

MODE

Burst Sequence Mode Selection

Output Enable

TMS, TDI,

JTAG Boundary Scan Pins

TCK, TDO

+2.5V Power Supply

CCQ

Isolated Output Buffer Supply:
+2.5V

Snooze Enable

A
NC
NC
VCCQ
GND
NC
DQPa
DQa
DQa
GND
VCCQ
DQa
DQa
GND
NC
VCC
ZZ
DQa
DQa
VCCQ
GND
DQa
DQa
NC
NC
GND
VCCQ
NC
NC
NC

CE2

BWb

BWa

CE2

VCC

GND

CLK

BWE

ADSC

ADSP

ADV

NC
NC
NC

VCCQ

GND

NC
NC

DQb
DQb

GND

VCCQ

DQb
DQb

VCC

GND

DQb
DQb

VCCQ

GND

DQb
DQb

DQPb

GND

VCCQ

NC
NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

GND

VCC

46 47 48 49 50

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

TRUTH TABLE

(1-8)

(3CE option)

OPERATION

ADDRESS

CE2

ADSP ADSC

ADV WRITE

CLK

Deselect Cycle, Power-Down

None

L-H

High-Z

Deselect Cycle, Power-Down

None

L-H

High-Z

Deselect Cycle, Power-Down

None

L-H

High-Z

Deselect Cycle, Power-Down

None

L-H

High-Z

Deselect Cycle, Power-Down

None

L-H

High-Z

Snooze Mode, Power-Down

None

High-Z

Read Cycle, Begin Burst

External

L-H

Read Cycle, Begin Burst

External

L-H

High-Z

Write Cycle, Begin Burst

External

L-H

Read Cycle, Begin Burst

External

L-H

Read Cycle, Begin Burst

External

L-H

High-Z

Read Cycle, Continue Burst

L-H

Read Cycle, Continue Burst

L-H

High-Z

Read Cycle, Continue Burst

L-H

Read Cycle, Continue Burst

L-H

High-Z

Write Cycle, Continue Burst

L-H

Write Cycle, Continue Burst

L-H

Read Cycle, Suspend Burst

Current

L-H

Read Cycle, Suspend Burst

Current

L-H

High-Z

Read Cycle, Suspend Burst

Current

L-H

Read Cycle, Suspend Burst

Current

L-H

High-Z

Write Cycle, Suspend Burst

Current

L-H

Write Cycle, Suspend Burst

Current

L-H

NOTE:

1. X means "Don't Care." H means logic HIGH. L means logic LOW.
2. For

WRITE

, L means one or more byte write enable signals (

BWa

BWb

BWc

BWd

) and

BWE

are LOW or

is LOW.

WRITE

= H for all

BWx

BWE

HIGH.

BWa

enables WRITEs to DQa's and DQPa.

BWb

enables WRITEs to DQb's and DQPb.

BWc

enables WRITEs to DQc's and

DQPc.

BWd

enables WRITEs to DQd's and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and

DQPd are only available on the x36 version.

4. All inputs except

and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation,

must be HIGH before the input data setup time and held HIGH during the

input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.

ADSP

LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write

enable signals and

BWE

LOW or

LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

PARTIAL TRUTH TABLE

Function

BWE

BWa

BWb

BWc

BWd

Read

Write Byte 1

Write All Bytes

TRUTH TABLE

(1-8)

(1CE option)

NEXT CYCLE

ADDRESS

ADSP

ADSC

ADV

WRITE

Deselected

None

High-Z

Read, Begin

External

Read, Begin

External

High-Z

Write, Begin

External

Write

Read, Begin

External

Read

Read, Begin

External

Read

High-Z

Read, Burst

Read

Read, Burst

Read

High-Z

Read, Burst

Read

Read, Burst

Read

High-Z

Write, Burst

Write

Write, Burst

Write

Read, Suspend

Current

Read

Read, Suspend

Current

Read

High-Z

Read, Suspend

Current

Read

Read, Suspend

Current

Read

High-Z

Write, Suspend

Current

Write

Write, Suspend

Current

Write

NOTE:

1. X means "Don't Care." H means logic HIGH. L means logic LOW.
2. For

WRITE

, L means one or more byte write enable signals (

BWa

BWb

BWc

BWd

) and

BWE

are LOW or

is LOW.

WRITE

= H for all

BWx

BWE

HIGH.

BWa

enables WRITEs to DQa's and DQPa.

BWb

enables WRITEs to DQb's and DQPb.

BWc

enables WRITEs to DQc's and

DQPc.

BWd

enables WRITEs to DQd's and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and

DQPd are only available on the x36 version.

4. All inputs except

and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation,

must be HIGH before the input data setup time and held HIGH during the

input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.

ADSP

LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write

enable signals and

BWE

LOW or

LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

INTERLEAVED BURST ADDRESS TABLE (MODE = V

or No Connect)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1 A0

LINEAR BURST ADDRESS TABLE (MODE = GND)

0,0

1,0

0,1

A1', A0' = 1,1

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

BIAS

Temperature Under Bias

40 to +85

°C

STG

Storage Temperature

55 to +150

°C

Power Dissipation

1.6

OUT

Output Current (per I/O)

100

, V

OUT

Voltage Relative to GND for I/O Pins

0.5 to V

CCQ

+ 0.5

Voltage Relative to GND for

0.5 to V

+ 0.5

for Address and Control Inputs

Voltage on Vcc Supply Relatiive to GND

0.5 to 3.2

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages or

electric fields; however, precautions may be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

OPERATING RANGE

Range

Ambient Temperature

CCQ

Commercial

0°C to +70°C

2.3752.625V

Industrial

40°C to +85°C

2.3752.625V

DC ELECTRICAL CHARACTERISTICS

(1)

(Over Operating Range)

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= 2.0 mA, V

CCQ

= 2.5V

1.7

Output LOW Voltage

= 2.0 mA, V

CCQ

= 2.5V

0.7

Input HIGH Voltage

CCQ

= 2.5V

1.7

CCQ

+ 0.3

Input LOW Voltage

CCQ

= 2.5V

0.3

0.7

Input Leakage Current

GND

CCQ

(2)

Com.

µA

Ind.

Output Leakage Current

GND

OUT

CCQ

= V

Com.

µA

Ind.

POWER SUPPLY CHARACTERISTICS

(Over Operating Range)

-200

-166

Symbol

Parameter

Test Conditions

Max.

Unit

AC Operating

Device Selected,

Com.

300

275

Supply Current

All Inputs = V

or V

Ind.

325

300

= V

, Vcc = Max.

Cycle Time

min.

Standby Current

Device Deselected,

Com.

= Max.,

Ind.

All Inputs = V

or V

CLK Cycle Time

min.

Notes:

1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to V

2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V

Vcc 0.2V.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

READ/WRITE CYCLE SWITCHING CHARACTERISTICS

(Over Operating Range)

-200

-166

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

MAX

Clock Frequency

200

166

MHz

Cycle Time

Clock High Pulse Width

2.3

Clock Low Pulse Width

2.3

Clock Access Time

3.1

3.5

KQX

(1)

Clock High to Output Invalid

1.0

1.5

KQLZ

(1,2)

Clock High to Output Low-Z

KQHZ

(1,2)

Clock High to Output High-Z

3.1

3.5

OEQ

Output Enable to Output Valid

3.1

3.5

OELZ

(1,2)

Output Enable to Output Low-Z

OEHZ

(1,2)

Output Enable to Output High-Z

3.0

3.2

Address Setup Time

1.5

Address Status Setup Time

1.5

Write Setup Time

1.5

CES

Chip Enable Setup Time

1.5

AVS

Address Advance Setup Time

1.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

AVH

Address Advance Hold Time

0.5

Note:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS

(Over Operating Range)

-200

-166

Symbol Parameter

Min.

Max.

Min.

Max.

Unit

Cycle Time

Clock High Pulse Width

2.3

Clock Low Pulse Width

2.3

Address Setup Time

1.5

Address Status Setup Time

1.5

Write Setup Time

1.5

Data In Setup Time

1.5

CES

Chip Enable Setup Time

1.5

AVS

Address Advance Setup Time

1.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Data In Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

AVH

Address Advance Hold Time

0.5

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)

The IS61VPS51236 and IS61VPS10018 have a serial
boundary scan Test Access Port (TAP) in the PBGA
package only. (Not available in TQFP package or with the
IS61VPS51232.) This port operates in accordance with
IEEE Standard 1149.1-1900, but does not include all
functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because
they place added delay in the critical speed path of the
SRAM. The TAP controller operates in a manner that does
not conflict with the performance of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.

DISABLING THE JTAG FEATURE

The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(GND) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to V

through a pull-up resistor.

TDO should be left disconnected. On power-up, the
device will start in a reset state which will not interfere with
the device operation.

TEST ACCESS PORT (TAP) - TEST CLOCK

The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.

TEST MODE SELECT (TMS)

The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.

TEST DATA-IN (TDI)

The TDI pin is used to serially input information to the
registers and can be connected to the input of any
register. The register between TDI and TDO is chosen by
the instruction loaded into the TAP instruction register.
For information on instruction register loading, see the
TAP Controller State Diagram. TDI is internally pulled up
and can be disconnected if the TAP is unused in an
application. TDI is connected to the Most Significant Bit
(MSB) on any register.

31 30 29

. . .

2 1 0

. . . . .

2 1 0

Bypass Register

Instruction Register

Identification Register

Boundary Scan Register*

TAP CONTROLLER

Selection Circuitry

TDO

TDI

TCK

TMS

TAP CONTROLLER BLOCK DIAGRAM

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

TEST DATA OUT (TDO)

The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the
current state of the TAP state machine (see TAP Controller
State Diagram). The output changes on the falling edge of
TCK and TDO is connected to the Least Significant Bit
(LSB) of any register.

PERFORMING A TAP RESET

A Reset is performed by forcing TMS HIGH (V

) for five

rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.

TAP REGISTERS

Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM test
circuitry

Only one register can be selected at a time

through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on the
TDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO pins. (See TAP Controller
Block Diagram) At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with
the IDCODE instruction if the controller is placed in a reset
state as previously described.

When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary "01" pattern
to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register

is set LOW (GND) when the BYPASS instruction is
executed.

Boundary Scan Register

The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 70-bit-long
register and the x18 configuration has a 51-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed
between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE Z instructions can be used to capture the
contents of the Input and Output ring.

The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE
command is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.

Scan Register Sizes

Register Name

Bit Size (x18)

Bit Size (x36)

Instruction

Bypass

Boundary Scan

IDENTIFICATION REGISTER DEFINITIONS

Instruction Field

Description

512K x 36

1M x 18

Revision Number (31:28)

Reserved for version number.

xxxx

Device Depth (27:23)

Defines depth of SRAM. 512K or 1M

00111

01000

Device Width (22:18)

Defines with of the SRAM. x36 or x18

00100

00011

ISSI Device ID (17:12)

Reserved for future use.

xxxxx

ISSI JEDEC ID (11:1)

Allows unique identification of SRAM vendor.

00011010101

ID Register Presence (0)

Indicate the presence of an ID register.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

TAP INSTRUCTION SET

Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM is
not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output
buffers. The SRAM does not implement the 1149.1 com-
mands EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; instead it performs a capture of the
Inputs and Output ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed
between TDI and TDO. During this state, instructions are
shifted from the instruction register through the TDI and
TDO pins. To execute an instruction once it is shifted in,
the TAP controller must be moved into the Update-IR
state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When
an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is a difference between
the instructions, unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented, so the TAP controller is not fully 1149.1 compli-
ant. When the SAMPLE/PRELOAD instruction is loaded
to the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and
output pins is captured in the boundary scan register.

It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clock runs more than an order of magnitude faster.
Because of the clock frequency differences, it is possible
that during the Capture-DR state, an input or output will
under-go a transition. The TAP may attempt a signal
capture while in transition (metastable state). The device
will not be harmed, but there is no guarantee of the value
that will be captured or repeatable results.

To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be
stabilized long enough to meet the TAP controller's
capture set-up plus hold times (t

and t

). To insure that

the SRAM clock input is captured correctly, designs need
a way to stop (or slow) the clock during a SAMPLE/
PRELOAD instruction. If this is not an issue, it is possible
to capture all other signals and simply ignore the value of
the CLK and

CLK

captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.

Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Update-DR
state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.

RESERVED

These instructions are not implemented but are reserved
for future use. Do not use these instructions.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

INSTRUCTION CODES

Code

Instruction

Description

000

EXTEST

Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.

001

IDCODE

Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.

010

SAMPLE Z

Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.

011

RESERVED

Do Not Use: This instruction is reserved for future use.

100

SAMPLE/PRELOAD

Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.

101

RESERVED

Do Not Use: This instruction is reserved for future use.

110

RESERVED

Do Not Use: This instruction is reserved for future use.

111

BYPASS

Places the bypass register between TDI and TDO. This operation does not

affect SRAM operation.

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test/Idle

TAP CONTROLLER STATE DIAGRAM

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

TAP Electrical Characteristics

Over the Operating Range

(1,2)

Symbol

Parameter

Test Conditions

Min.

Max.

Units

OH1

Output HIGH Voltage

= 2.0 mA

1.7

OH2

Output HIGH Voltage

= 100 mA

2.1

OL1

Output LOW Voltage

= 2.0 mA

0.7

OL2

Output LOW Voltage

= 100 mA

0.2

Input HIGH Voltage

1.7

+0.3

Input LOW Voltage

OLT

= 2mA

0.3

0.7

Input Load Current

GND

V I

DDQ

Notes:

1. All Voltage referenced to Ground.
2. Overshoot: V

(AC)

+1.5V for t

TCYC

/2,

Undershoot:V

(AC)

0.5V for t

TCYC

/2,

Power-up: V

< 2.6V and V

< 2.4V and V

DDQ

< 1.4V for t < 200 ms.

TAP AC ELECTRICAL CHARACTERISTICS

(1)

(OVER OPERATING RANGE)

Symbol Parameter

Min.

Max.

Unit

TCYC

TCK Clock cycle time

100

TCK Clock frequency

MHz

TCK Clock HIGH

TCK Clock LOW

TMSS

TMS setup to TCK Clock Rise

TDIS

TDI setup to TCK Clock Rise

Capture setup to TCK Rise

TMSH

TMS hold after TCK Clock Rise

TDIH

TDI Hold after Clock Rise

Capture hold after Clock Rise

TDOV

TCK LOW to TDO valid

TDOX

TCK LOW to TDO invalid

Notes:

Notes:
7. t

and t

refer to the set-up and hold time requirements of latching data from the boundary scan register.

8. Test conditions are specified using the load in TAP AC test conditions. t

= 1 ns.

Integrated Silicon Solution, Inc. -- 1-800-379-4774

ADVANCE INFORMATION

Rev. 00B

09/25/01

IS61VPS51232 IS61VPS51236 IS61VPS10018

ISSI

BOUNDARY SCAN ORDER (512K X 36)

Signal Bump

Bit #

Name

Bit #

Name

Bit #

Name

Bit #

Name

DQb

BWa

DQd

DQb

BWb

DQd

DQb

BWc

DQd

DQb

BWd

DQd

DQb

DQd

DQb

DQd

DQb

DQd

DQa

DQb

DQd

DQa

DQc

DQd

DQa

DQc

MODE

DQa

ADV

DQc

DQa

ADSP

DQc

DQa

ADSC

DQc

DQa

DQc

DQa

BWE

DQc

DQa

DQc

CLK

DQc

DQb

BOUNDARY SCAN ORDER (1M X 18)

Signal Bump

Bit #

Name

Bit #

Name

Bit #

Name

Bit #

Name

DQa

CLK

DQb

DQa

DQb

DQa

BWa

DQb

DQa

BWb

DQb

MODE

DQa

ADV

DQa

ADSP

DQb

DQa

ADSC

DQb

DQa

DQb

BWE

DQb

DQa

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61VPS51236

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61VPS51236