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Электронный компонент: IS62C256AL-45TLI

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Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. A
03/17/06
ISSI
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
IS65C256AL
IS62C256AL
FEATURES
Access time: 25 ns, 45 ns
Low active power: 200 mW (typical)
Low standby power
-- 150 W (typical) CMOS standby
-- 15 mW (typical) operating
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V power supply
Lead-free available
Industrial and Automotive temperatures avail-
able
DESCRIPTION
The
ISSI
IS62C256AL/IS65C256AL is a low power,
32,768 word by 8-bit CMOS static RAM. It is fabricated
using
ISSI
's high-performance, low power CMOS tech-
nology.
When
CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 W (typical) at CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Select (
CE) input and an active LOW Output
Enable (
OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62C256AL/IS65C256AL is pin compatible with
other 32Kx8 SRAMs in plastic SOP or TSOP (Type I)
package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
32K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
32K x 8 LOW POWER CMOS STATIC RAM
MARCH 2006
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
PIN CONFIGURATION
28-Pin SOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VDD
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
0.5
W
I
OUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN CONFIGURATION
28-Pin TSOP
PIN DESCRIPTIONS
A0-A14
Address Inputs
CE
Chip Select Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
V
DD
Power
GND
Ground
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
I/O Operation
V
DD
Current
Not Selected
X
H
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
Output Disabled
H
L
H
High-Z
I
CC
1
, I
CC
2
Read
H
L
L
D
OUT
I
CC
1
, I
CC
2
Write
L
L
X
D
IN
I
CC
1
, I
CC
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
OPERATING RANGE
Part No.
Range
Ambient Temperature
V
DD
IS62C256AL
Commercial
0C to +70C
5V 10%
IS62C256AL
Industrial
40C to +85C
5V 10%
IS65C256AL
Automotive
40C to +125C
5V 10%
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
= 1.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 2.1 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
DD
+ 0.5
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
DD
Com.
1
1
A
Ind.
2
2
Auto.
10
10
I
LO
Output Leakage
GND
V
OUT
V
DD
,
Com.
1
1
A
Outputs Disabled
Ind.
2
2
Auto.
10
10
Note: 1. V
IL
= 3.0V for pulse width less than 10 ns.
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
8
pF
C
OUT
Output Capacitance
V
OUT
= 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, V
DD
= 5.0V.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-25 ns
-45 ns
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
I
CC
1
V
DD
Operating
V
DD
= Max.,
CE = V
IL
Com.
--
15
--
15
mA
Supply Current
I
OUT
= 0 mA, f = 0
Ind.
--
20
--
20
Auto.
--
25
--
25
I
CC
2
V
DD
Dynamic Operating
V
DD
= Max.,
CE = V
IL
Com.
--
25
--
20
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
30
--
25
Auto.
--
35
--
30
typ.
(2)
15
12
I
SB
1
TTL Standby Current
V
DD
= Max.,
Com.
--
100
--
100
A
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
--
120
--
120
CE
V
IH
, f = 0
Auto.
--
150
--
150
I
SB
2
CMOS Standby
V
DD
= Max.,
Com.
--
15
--
15
A
Current (CMOS Inputs)
CE
V
DD
0.2V,
Ind.
--
20
--
20
V
IN
V
DD
0.2V, or
Auto.
--
50
--
50
V
IN
0.2V, f = 0
typ.
(2)
5
5
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
= 5.0V, T
A
= 25
o
C and not 100% tested.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
Figure 1.
Figure 2.
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Levels
Output Load
See Figures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-25 ns
-45 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
25
--
45
--
ns
t
AA
Address Access Time
--
25
--
45
ns
t
OHA
Output Hold Time
2
--
2
--
ns
t
ACS
CE Access Time
--
25
--
45
ns
t
DOE
OE Access Time
--
13
--
25
ns
t
LZOE
(2)
OE to Low-Z Output
0
--
0
--
ns
t
HZOE
(2)
OE to High-Z Output
0
12
0
20
ns
t
LZCS
(2)
CE to Low-Z Output
3
--
3
--
ns
t
HZCS
(2)
CE to High-Z Output
0
12
0
20
ns
t
PU
(3)
CE to Power-Up
0
--
0
--
ns
t
PD
(3)
CE to Power-Down
--
20
--
30
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
480
100 pF
Including
jig and
scope
255
OUTPUT
5V
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
READ CYCLE NO. 2
(1,3)
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
Notes:
1.
WE is HIGH for a Read Cycle.
2. The device is continuously selected.
OE, CE = V
IL
.
3. Address is valid prior to or coincident with
CE LOW transitions.
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACS
t
LZCS
t
HZOE
HIGH-Z
DATA VALID
ADDRESS
OE
CE
D
OUT
t
HZCS
CS_RD2.eps
Integrated Silicon Solution, Inc. -- 1-800-379-4774
7
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-25 ns
-45 ns
Symbol
Parameter
Min.
Max.
Min. Max.
Unit
t
WC
Write Cycle Time
25
--
45
--
ns
t
SCS
CE to Write End
15
--
35
--
ns
t
AW
Address Setup Time to Write End
15
--
25
--
ns
t
HA
Address Hold from Write End
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
ns
t
PWE
1,
WE Pulse Width
15
--
25
--
ns
t
PWE
2
(4)
t
SD
Data Setup to Write End
12
--
20
--
ns
t
HD
Data Hold from Write End
0
--
0
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with
OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE Controlled, OE is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CS_WR1.eps
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
AC WAVEFORMS
WRITE CYCLE NO. 2
(
OE is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(
OE is LOW During Write Cycle)
(1)
Notes:
1. The internal write time is defined by the overlap of
CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if
OE = V
IH
.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CS_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CS_WR3.eps
Integrated Silicon Solution, Inc. -- 1-800-379-4774
9
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
DR
V
DD
for Data Retention
See Data Retention Waveform
2.0
5.5
V
I
DR
Data Retention Current
V
DD
= 2.0V,
CE
V
DD
0.2V
Com.
--
--
15
A
V
IN
V
DD
0.2V, or V
IN
V
SS
+ 0.2V
Ind.
--
--
20
Auto.
--
--
50
t
SDR
Data Retention Setup Time See Data Retention Waveform
0
--
ns
t
RDR
Recovery Time
See Data Retention Waveform
t
RC
--
ns
Note:
1. Typical Values are measured at V
DD
= 5V, T
A
= 25
o
C and not 100% tested.
DATA RETENTION WAVEFORM (
CE
CE
CE
CE
CE Controlled)
VDD
CE
VDD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
4.5V
2.2V
Data Retention Mode
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed
(ns)
Order Part No.
Package
45
IS62C256AL-45T
TSOP
IS62C256AL-45TL
TSOP, Lead-free
IS62C256AL-45U
Plastic SOP
IS62C256AL-45UL
Plastic SOP, Lead-free
ORDERING INFORMATION
Industrial Range: 40C to +85C
Speed
(ns)
Order Part No.
Package
25
IS62C256AL-25TI
TSOP
IS62C256AL-25UI
Plastic SOP
45
IS62C256AL-45TI
TSOP
IS62C256AL-45TLI
TSOP, Lead-free
IS62C256AL-45UI
Plastic SOP
IS62C256AL-45ULI
Plastic SOP, Lead-free
ORDERING INFORMATION
Automotive Range: 40C to +125C
Speed
(ns)
Order Part No.
Package
25
IS65C256AL-25TA3
TSOP
IS65C256AL-25TLA3
TSOP, Lead-free
IS65C256AL-25UA3
Plastic SOP
IS65C256AL-25ULA3
Plastic SOP, Lead-free
45
IS65C256AL-45TA3
TSOP
IS65C256AL-45TLA3
TSOP, Lead-free
IS65C256AL-45UA3
Plastic SOP
IS65C256AL-45ULA3
Plastic SOP, Lead-free
Integrated Silicon Solution, Inc.
ISSI
PACKAGING INFORMATION
D
SEATING PLANE
B
e
C
1
E
A1
A
S
H
L
N
Plastic TSOP - 28-pins
Package Code: T (Type I)
Plastic TSOP (T--Type I)
Millimeters
Inches
Symbol
Min
Max
Min
Max
Ref. Std.
No. Leads
28
A
1.00
1.20
0.037
0.047
A1
0.05
0.20
0.002
0.008
B
0.16
0.27
0.006
0.011
C
0.10
0.20
0.004
0.008
D
7.90
8.10
0.308
0.316
E
11.70
11.90
0.456
0.465
H
13.20
13.60
0.515
0.531
e
0.55 BSC
0.022 BSC
L
0.30
0.70
0.011
0.027
0
5
0
5
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
should be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
PK13197T28 Rev. B 01/31/97
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
02/26/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
330-mil Plastic SOP
Package Code: U (28-pin)
D
SEATING PLANE
B
e
C
1
N
E1
A1
A
E
L
S
h x 45
o
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
package.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
MILLIMETERS
INCHES
Sym.
Min.
Max.
Min.
Max.
No. Leads 28
28
A
--
2.84
--
0.112
A1
0.10
--
0.004
--
B
0.36
0.51
0.014
0.020
C
0.25
--
0.010
--
D
17.98
18.24
0.708
0.718
E
11.51
12.12
0.453
0.477
E1
8.28
8.53
0.326
0.336
e 1.27 BSC
0.050 BSC
h
0.30
0.51
0.012
0.020
L
0.71
1.14
0.028
0.045
0
o
8
o
0
o
8
o
S
0.58
1.19
0.023
0.047