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Электронный компонент: IS62WV25616CLL

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IS62WV25616CLL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. C
03/13/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
256K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC SRAM
FEATURES
High-speed access time: 55ns, 70ns
CMOS low power operation
1.5 W (typical) CMOS standby
TTL compatible interface levels
Single power supply
2.5V--3.6V V
DD
(62WV25616CLL)
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
2CS Option Available
DESCRIPTION
The
ISSI
IS62WV25616CLL are high-speed, low power, 4M
bit SRAMs organized as 256K words by 16 bits. It is
fabricated using
ISSI
's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
When
CS1
is HIGH (deselected) or when CS2 is LOW
(deselected) or when
CS1
is LOW, CS2 is HIGH and both
LB
and
UB
are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE)
controls both writing and reading of the memory. A
data byte allows Upper Byte
(UB)
and Lower Byte (
LB)
access.
The IS62WV25616CLL are packaged in the JEDEC standard
48-pin mini BGA (6mm x 8mm). 48-pin mini BGA is
available both in 1CS and 2CS options.
FUNCTIONAL BLOCK DIAGRAM
MARCH 2003
A0-A17
CS1
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
CS2
IS62WV25616CLL
ISSI
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
03/13/03
PIN CONFIGURATIONS
48- ball mini BGA (6mm x 8mm)
(Package Code B)
PIN DESCRIPTIONS
A0-A17
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CS1
, CS2
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
V
DD
Power
GND
Ground
48-ball mini BGA (6mm x 8mm)
2 CS Option (Package Code B2)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
NC
I/O
8
UB
A3
A4
CSI
I/O
0
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
GND
I/O
11
A17
A7
I/O
3
V
DD
V
DD
I/O
12
NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11
NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
CS2
I/O
8
UB
A3
A4
CS1
I/O
0
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
GND
I/O
11
A17
A7
I/O
3
V
DD
V
DD
I/O
12
NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11
NC
IS62WV25616CLL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. C
03/13/03
TRUTH TABLE
I/O PIN
Mode
WE
WE
WE
WE
WE
CS1
CS1
CS1
CS1
CS1
CS2
OE
OE
OE
OE
OE
LB
LB
LB
LB
LB
UB
UB
UB
UB
UB
I/O0-I/O7
I/O8-I/O15
V
DD
Current
Not Selected
X
H
X
X
X
X
High-Z
High-Z
I
SB
1
, I
SB
2
X
X
L
X
X
X
High-Z
High-Z
I
SB
1
, I
SB
2
X
X
X
X
H
H
High-Z
High-Z
I
SB
1
, I
SB
2
Output Disabled
H
L
H
H
L
X
High-Z
High-Z
I
CC
H
L
H
H
X
L
High-Z
High-Z
I
CC
Read
H
L
H
L
L
H
D
OUT
High-Z
I
CC
H
L
H
L
H
L
High-Z
D
OUT
H
L
H
L
L
L
D
OUT
D
OUT
Write
L
L
H
X
L
H
D
IN
High-Z
I
CC
L
L
H
X
H
L
High-Z
D
IN
L
L
H
X
L
L
D
IN
D
IN
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.3 to V
DD
+0.5
V
V
DD
V
DD
Related to GND
0.2 to +4.2
V
T
STG
Storage Temperature
55 to +125
C
P
T
Power Dissipation
0.6
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Operation Range (V
DD
)
Range
Ambient Temperature
V
DD
Commercial
0
o
C to +70
o
C
2.5V - 3.6V
Industrial
-40
o
C to +85
o
C
2.5V - 3.6V
IS62WV25616CLL
ISSI
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
03/13/03
IS62WV25616CLL, POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Test Conditions
Max.
Max.
Unit
55
70
I
CC
V
DD
Dynamic Operating
V
DD
= Max.,
Com.
50
45
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
55
50
I
CC
1
Operating Supply
V
DD
= Max.,
Com.
2
2
mA
Current
I
OUT
= 0 mA, f = 0
Ind.
3
3
I
SB
1
TTL Standby Current
V
DD
= Max.,
Com.
0.6
0.6
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
0.8
0.8
CS1
= V
IH
, CS2 = V
IL
,
f = 1 MH
Z
OR
ULB Control
V
DD
= Max., V
IN
= V
IH
or V
IL
CS1
= V
IL
, f = 0,
UB
= V
IH
,
LB
= V
IH
I
SB
2
CMOS Standby
V
DD
= Max.,
Com.
10
10
A
Current (CMOS Inputs)
CS1
V
DD
0.2V,
Ind.
10
10
CS2
0.2V,
typ
(1)
0.5
0.5
V
IN
V
DD
0.2V, or
V
IN
0.2V, f = 0
OR
ULB Control
V
DD
= Max.,
CS1
= V
IL
, CS2=V
IH
V
IN
0.2V, f = 0;
UB
/
LB
= V
DD
0.2V
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
V
DD
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= -1 mA
2.5-3.6V
2.2
--
V
V
OL
Output LOW Voltage
I
OL
= 2.1 mA
2.5-3.6V
--
0.4
V
V
IH
Input HIGH Voltage
2.5-3.6V
2.2
V
DD
+ 0.3
V
V
IL
(1)
Input LOW Voltage
2.5-3.6V
0.2
0.6
V
I
LI
Input Leakage
GND
V
IN
V
DD
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
DD
, Outputs Disabled
1
1
A
Notes:
1. V
IL
(min.) = 1.0V for pulse width less than 10 ns.
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
8
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
10
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Note:
1. Typical values are measured at V
DD
=3.0V, T
A
=25
o
C. Not 100% tested.
IS62WV25616CLL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. C
03/13/03
AC TEST CONDITIONS
IS62WV25616CLL
Parameter
(Unit)
Input Pulse Level
0.4 to V
DD
-0.3V
Input Rise and Fall Times
5ns
Input and Output Timing
V
REF
and Reference Level
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 1
Figure 2
2.5V - 3.6V
R1(
)
)
)
)
)
3070
R2(
)
)
)
)
)
3150
V
REF
1.5V
V
TM
2.8V
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
R1
30 pF
Including
jig and
scope
R2
OUTPUT
VTM
IS62WV25616CLL
ISSI
6
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
03/13/03
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
55 ns
70 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
55
--
70
--
ns
t
AA
Address Access Time
--
55
--
70
ns
t
OHA
Output Hold Time
10
--
10
--
ns
t
ACS1/
t
ACS2
CS1/
CS2 Access Time
--
55
--
70
ns
t
DOE
OE
Access Time
--
35
--
40
ns
t
HZOE
(2)
OE
to High-Z Output
--
20
--
25
ns
t
LZOE
(2)
OE
to Low-Z Output
5
--
5
--
ns
t
HZCS1/
t
HZCS2
(2)
CS1/
CS2 to High-Z Output
0
20
0
25
ns
t
LZCS1/
t
LZCS2
(2)
CS1/
CS2 to Low-Z Output
10
--
10
--
ns
t
BA
LB
,
UB
Access Time
--
55
--
70
ns
t
HZB
LB
,
UB
to High-Z Output
0
20
0
25
ns
t
LZB
LB
,
UB
to Low-Z Output
0
--
0
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4 to V
DD
-
0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
IS62WV25616CLL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
7
Rev. C
03/13/03
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (
CS1
=
OE
= V
IL
,
CS2
=
WE
= V
IH
,
UB
or
LB
= V
IL
)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z
DATA VALID
t
HZCS1/
t
HZCS2
ADDRESS
OE
CS1
CS2
DOUT
LB
,
UB
t
HZB
t
BA
t
LZB
READ CYCLE NO. 2
(1,3)
(
CS1
,
CS2, OE
, AND
UB
/
LB
Controlled)
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CS1
,
UB
, or
LB
= V
IL
. CS2=
WE
=V
IH
.
3. Address is valid prior to or coincident with
CS1
LOW transition.
IS62WV25616CLL
ISSI
8
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
03/13/03
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the
CS1
, CS2 and
WE
inputs and at
least one of the
LB
and
UB
inputs being in the LOW state.
2. WRITE = (
CS1
) [ (
LB
) = (
UB
) ] (
WE
).
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CS1
Controlled,
OE
= HIGH or LOW)
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
55 ns
70 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
55
--
70
--
ns
t
SCS1/
t
SCS2
CS1/
CS2 to Write End
45
--
60
--
ns
t
AW
Address Setup Time to Write End
45
--
60
--
ns
t
HA
Address Hold from Write End
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
ns
t
PWB
LB
,
UB
Valid to End of Write
45
--
60
--
ns
t
PWE
WE
Pulse Width
40
--
50
--
ns
t
SD
Data Setup to Write End
25
--
30
--
ns
t
HD
Data Hold from Write End
0
--
0
--
ns
t
HZWE
(3)
WE
LOW to High-Z Output
--
20
--
20
ns
t
LZWE
(3)
WE
HIGH to Low-Z Output
5
--
5
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to V
DD
-
0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CS1
LOW, CS2 HIGH and
UB
or
LB
, and
WE
LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
LB
,
UB
t
PWB
IS62WV25616CLL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
9
Rev. C
03/13/03
WRITE CYCLE NO. 2
(
WE
Controlled:
OE
is HIGH During Write Cycle)
WRITE CYCLE NO. 3
(
WE
Controlled:
OE
is LOW During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB
,
UB
DOUT
DIN
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB
,
UB
DOUT
DIN
IS62WV25616CLL
ISSI
10
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
03/13/03
WRITE CYCLE NO. 4
(
UB
/
LB
Controlled)
DATA UNDEFINED
t
WC
ADDRESS 1
ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
t
HD
t
SA
t
HZWE
ADDRESS
CS1
UB
,
LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
UB_CSWR4.eps
HIGH
CS2
IS62WV25616CLL
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
11
Rev. C
03/13/03
DATA RETENTION WAVEFORM
(
CS1
Controlled)
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Max.
Unit
V
DR
V
DD
for Data Retention
See Data Retention Waveform
1.5
3.6
V
I
DR
Data Retention Current
V
DD
= 1.5V,
CS1
V
DD
0.2V
--
10
A
t
SDR
Data Retention Setup Time
See Data Retention Waveform
0
--
ns
t
RDR
Recovery Time
See Data Retention Waveform
t
RC
--
ns
DATA RETENTION WAVEFORM
(CS2 Controlled)
V
DD
CS2
0.2V
t
SDR
t
RDR
V
DR
0.4V
CE2
GND
3.0
2.2V
Data Retention Mode
V
DD
CS1
V
DD
- 0.2V
tSDR
t
RDR
V
DR
CS1
GND
1.65V
1.4V
Data Retention Mode
IS62WV25616CLL
ISSI
12
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
03/13/03
ORDERING INFORMATION
IS62WV25616CLL (2.5V - 3.6V)
Commercial Range: 0C to +70C
Speed (ns)
Order Part No.
Package
55
IS62WV25616CLL-55B
mini BGA (6mm x 8mm)
IS62WV25616CLL-55B2
mini BGA (6mm x 8mm), 2 CS Option
Industrial Range: 40C to +85C
Speed (ns)
Order Part No.
Package
55
IS62WV25616CLL-55BI
mini BGA (6mm x 8mm)
IS62WV25616CLL-55B2I
mini BGA (6mm x 8mm), 2 CS Option
70
IS62WV25616CLL-70BI
mini BGA (6mm x 8mm)
IS62WV25616CLL-70B2I
mini BGA (6mm x 8mm), 2 CS Option
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
01/15/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Mini Ball Grid Array
Package Code: B (48-pin)
Notes:
1. Controlling dimensions are in millimeters.
mBGA - 6mm x 8mm
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
--
--
1.20
--
--
0.047
A1
0.24
--
0.30
0.009
--
0.012
A2
0.60
--
--
0.024
--
--
D
7.90
--
8.10
0.311
--
0.319
D1
5.25 BSC
0.207 BSC
E
5.90
--
6.10
0.232
--
0.240
E1
3.75 BSC
0.148 BSC
e
0.75 BSC
0.030 BSC
b
0.30
0.35
0.40
0.012 0.014 0.016
mBGA - 8mm x 10mm
MILLIMETER
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
--
--
1.20
--
--
0.047
A1
0.24
--
0.30
0.009
--
0.012
A2
0.60
--
--
0.024
--
--
D
9.90
--
10.10
0.390
--
0.398
D1
5.25 BSC
0.207 BSC
E
7.90
--
8.10
0.311
--
0.319
E1
3.75 BSC
0.148 BSC
e
0.75 BSC
0.030 BSC
b
0.30
0.35
0.40
0.012 0.014 0.016
SEATING PLANE
A
A1
A2
A
B
C
D
E
F
G
H
e
e
D1
E1
E
D
b (48x)
Top View
Bottom View
6 5 4 3 2 1
1 2 3 4 5 6
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