IT8705F
Simple Low Pin Count Input / Output (Simple LPC I/O)
Preliminary Specification V0.3
Copyright
1999 ITE, Inc.
This is Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous documentation issued for the related
products included herein. Please contact ITE, Inc. for the latest document(s).
All sales are subject to ITE' s Standard Terms and Conditions, a copy of which is included in the back of this
document.
ITE, IT8705F is a trademark of ITE, Inc.
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Microsoft is claimed as a trademark by Microsoft Corporation.
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is claimed as a trademark by the Infrared Data Association.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
ITE (USA) Inc.
Phone: (408) 530-8860
Marketing Department
Fax:
(408) 530-8861
1235 Midas Way,
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Phone: (512) 388-7880
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Revision History
Revision History
Note: Words in bold typeface in the revisions below indicate the changes.
Section
Revision
Page No.
1
The feature of Smart Card Reader was added.
The feature of " 48 General Purpose I/O Pins" was revised.
1
2
At the end of the second paragraph, the description "It also features a
PC/SC and ISO 7816 compliant Smart Card Reader." was added.
3
3
Block Diagram was revised.
5
4
Section 4 Pin Configuration was revised.
7
Pin 2 was revised to " RTS2#/JP6" .
Pin 11 was revised to " FD4/IRQIN0/GP14".
Pin 12 was revised to " FD5/IRQIN1/GP15".
Pin 13 was revised to " FD/IRQIN2/GP16" .
Pin 14 was revised to " FD/IRQIN3/GP17" .
Pin 16 was revised to " FA0/VID_I0/GP20".
Pin 17 was revised to " FA1/VID_I1/GP21".
Pin 18 was revised to " FA2/VID_I2/GP22".
Pin 19 was revised to " FA3/VID_I3/GP23".
Pin 20 was revised to " FA4/VID_I4/GP24".
Pin 21 was revised to " FA5/VID_O1/GP25".
Pin 22 was revised to " FA6/VID_O2/GP26".
Pin 23 was revised to " FA7/VID_O3/GP27".
Pin 24 was revised to " FA8/VID_O4/GP30".
Pin 25 was revised to " FA9/VID_O5/GP31".
Pin 47 was revised to " FCS#/SCIO/GP53" .
Pin 59 was revised to " MTRB#/SCRST".
Pin 61 was revised to " DRVB#/SCCLK" .
Pin 80 was revised to " FAN_CTL3/GP62/SCPFET#".
Pin 81 was revised to " PME#/GP63/SCPRES#".
8-9
5
The pin descriptions of the revised pins described above were revised.
11-19
Add the note "The GPIO registers of these pins are powered by VCC, not
VCCH." to the end of Table 5-4 and Table 5-5.
12-13
The pin descriptions of pins 69, 70, 71, 72 were revised.
17
6
Section 6 List of GPIO Pins was revised.
21-23
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IT8705F
Revision History (cont' d)
Section
Revision
Page No.
6
Add the note "The GPIO registers of these pins are powered by VCC, not
VCCH." to the end of Table 6-6.
23
7
Table 7-1. Power On Strapping Options was revised.
25
8
In Table 8-1, the register for index 22h was revised to " Configuration
Select and Chip Version".
28
In Table 8-4, two more Serial Port Configuration registers were added:
Serial Port 2 Special Configuration Register 3, and Serial Port 2 Special
Configuration Register 4.
29
In Table 8-7, two more GPIO Configuration registers were added: IRQ
Routing Input 0 and 1 Interrupt Level Select Register, and IRQ Routing
Input 2 and 3 Interrupt Level Select Register.
31
Several new registers were added from Index F6h through FFh at the end
of Table 8-7 GPIO Configuration Registers.
32
Section 8.3.5 Configuration Select and Chip Version Register was
revised.
In section 8.3.6 Software Suspend, the bits 7-6 was revised to
"SCRPRES# Select".
In section 8.3.7 Clock Selection and Flash ROM I/F Control Register, the
description of bit 5 was revised to Flash ROM Interface Address Segment
2 (FFEF0000h-FFEFFFFh, FFEE0000h-FFEEFFFFh) Enable.
35
The bit 2-0 description for section 8.6.6 Serial Port 2 Special Register 2
was revised. It added the " 100: Smart Card Reader (SCR).
44
The descriptions for Serial Port 2 Special Configuration Register 3 and
Serial Port 2 Special Configuration Register 4 were added in section 8.6.7
and 8.6.8 respectively.
45
The bit 0 of section 8.8.9 PME Control Register 1 was revised to
"Reserved" .
49
Added 2 new registers in section 8.9.8, and 8.9.9: IRQ Routing Input 0
and 1 Interrupt Level Select Register, and IRQ Routing Input 2 and 3
Interrupt Level Select Register.
51
Added the descriptions of several new registers from section 8.9.20
through 8.9.29.
54-56
The descriptions of bits 7-6, 5-4, 3 of Section 8.12.5 MIDI Port Special
Configuration Register were revised.
58
9
In Table 9-2. Environment Controller Registers, the Serial Bus Interface
Address Register was revised to " Reserved".
67
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Revision History
Revision History (cont' d)
Section
Revision
Page No.
9
In Table 9-2. Environment Controller Registers, the registers from Index
52h to 54h were revised to " Reserved" registers.
In Table 9-2. Environment Controller Registers, 4 new EC registers were
added from index 5Ch through 5Fh: 1) Special Control and Beep Event
Enable Register, 2) Beep Frequency Divisor of Fan Event Register, 3)
Beep Frequency Divisor of Voltage Event Register, and 4) Beep
Frequency Divisor of Temperature Event Register.
68
The bit 6 description in section 9.5.3.2.11 Fan Tachometer Divisor
Register was revised.
70
The R/W of section 9.5.3.2.13 Fan Tachometer 1-3 Limit Registers
(Index=10h-12H) was revised to " R/W".
Bit 7 description of section 9.5.3.2.14 Fan Controller Main Control
Register was revised.
Bits 7 & 6-4 descriptions of section 9.5.3.2.15 FAN_CTL Control Register
were revised.
71
Section 9.5.3.2.26 Serial Bus Interface Address Register (Index=48h) was
revised to " Reserved" register.
Section 9.5.3.2.28 bit no. 7 was revised to bit no. 7-6.
73
The registers from Index 54h-52h was changed to " Reserved" registers in
section 9.5.3.29.
74
In section 9.5.4.3 Voltage and Temperature Input, the formula for
Negative Voltage was revised to "Vs = (1+Rin/Rf) x Vin - (Rin/Rf) x
VREF" .
78
The descriptions of the 4 new EC registers described above were given
from section 9.5.3.2.32 through 9.5.3.2.35.
74-75
In section 9.7.2, the " DLAB=0" should be changed to " DLAB=1" in title (4)
Divisor Latches (DLL, DLM).
111
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