IT8710F
Low Pin Count Input/Output (LPC I/O)
Preliminary Specification V0.1
Copyright
2001 ITE, Inc.
This is Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous documentation issued for the related
products included herein. Please contact ITE, Inc. for the latest document(s).
All sales are subject to ITE's Standard Terms and Conditions, a copy of which i s included in the back of this
document.
ITE, IT8710F is a trademark of ITE, Inc.
Intel is claimed as a trademark by Intel Corp.
Microsoft and Windows are claimed as trademarks by Microsoft Corporation.
PCI
is claimed as a trademark by the PCI Special Interest Group.
IrDA is claimed as a trademark by the Infrared Data Association.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
ITE, Inc. Phone: (02) 2657-9896
Marketing Department Fax: (02) 2657-8561, 2657-8576
7F, No. 435, Nei Hu District, Jui Kuang Rd.,
Taipei 114, Taiwan, R.O.C.
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Marketing Department Fax: (408) 530-8861
1235 Midas Way
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U.S.A.
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896 Summit St., #105
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U.S.A.
If you have any marketing or sales questions, please contact:
Lawrence Liu, at ITE Taiwan: E-mail: lawrence.liu@ite.com.tw, Tel: 886-2-26579896 X6071,
Fax: 886-2-26578561
David Lin, at ITE U.S.A: E-mail: david.lin@iteusa.com, Tel: (408) 530-8860 X238,
Fax: (408) 530-8861
Don Gardenhire, at ITE Eastern USA Office: E-mail: don.gardenhire@iteusa.com,
Tel: (512) 388-7880, Fax: (512) 388-3108
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Contents
CONTENTS
1.
Features................................................................................................................................................................ 1
2.
General Description ............................................................................................................................................. 3
3.
Block Diagram ...................................................................................................................................................... 5
4.
Pin Configuration.................................................................................................................................................. 7
5.
IT8710F Pin Descriptions .................................................................................................................................... 9
6.
List of GPIO Pins................................................................................................................................................ 21
7.
Power On Strapping Options............................................................................................................................. 25
8.
Configuration ...................................................................................................................................................... 27
8.1
Configuring Sequence Description .................................................................................................... 27
8.2
Description of the Configuration Registers........................................................................................ 28
8.3
Global Configuration Registers (LDN: All)......................................................................................... 33
8.3.1
Configure Control (Index=02h) ................................................................................................. 33
8.3.2
Logical Device Number (LDN, Index=07h) .............................................................................. 33
8.3.3
Chip ID Byte 1 (Index=20h, Default=87h)................................................................................ 33
8.3.4
Chip ID Byte 2 (Index=21h, Default=10h)................................................................................ 33
8.3.5
Chip Version (Index=22h, Default=00h)................................................................................... 33
8.3.6
Software Suspend (Index=23h, Default=00h) ......................................................................... 33
8.3.7
Clock Selection and Flash ROM I/F Control Register (Index=24h, Default=ssss0000b) ..... 34
8.3.8
GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=3Fh, VCC) ........... 35
8.3.9
GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h, VCCH)......... 36
8.3.10
GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=FFh, VCCH) ........ 37
8.3.11
GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=FFh, VCCH) ........ 37
8.3.12
GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=FFh) ..................... 38
8.3.13
GPIO Set 6 Multi-Function Pin Selection Register (Index=2Ah, Default=FFh, VCCH) ........ 39
8.3.14
Test 1 Register (Index=2Eh, Default=00h) .............................................................................. 39
8.3.15
Test 2 Register (Index=2Fh, Default=00h) .............................................................................. 39
8.4
FDC Configuration Registers (LDN=00h).......................................................................................... 39
8.4.1
FDC Activate (Index=30h, Default=00h) .................................................................................. 39
8.4.2
FDC Base Address MSB Register (Index=60h, Default=03h) ............................................... 40
8.4.3
FDC Base Address LSB Register (Index=61h, Default=F0h) ................................................ 40
8.4.4
FDC Interrupt Level Select (Index=70h, Default=06h)............................................................ 40
8.4.5
FDC DMA Channel Select (Index=74h, Default=02h) ............................................................ 40
8.4.6
FDC Special Configuration Register 1 (Index=F0h, Default=00h)......................................... 40
8.4.7
FDC Special Configuration Register 2 (Index=F1h, Default=00h)......................................... 40
8.5
Serial Port 1 Configuration Registers (LDN=01h)............................................................................. 41
8.5.1
Serial Port 1 Activate (Index=30h, Default=00h)..................................................................... 41
8.5.2
Serial Port 1 Base Address MSB Register (Index=60h, Default=03h) .................................... 41
8.5.3
Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h) ................................... 41
8.5.4
Serial Port 1 Interrupt Level Select (Index=70h, Default=04h) .............................................. 41
8.5.5
Serial Port 1 Special Configuration Register (Index=F0h, Default=00h) ............................... 41
8.6
Serial Port 2 Configuration Registers (LDN=02h)............................................................................. 41
8.6.1
Serial Port 2 Activate (Index=30h, Default=00h)..................................................................... 41
8.6.2
Serial Port 2 Base Address MSB Register (Index=60h, Default=02h) .................................... 41
8.6.3
Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h)..................................... 42
8.6.4
Serial Port 2 Interrupt Level Select (Index=70h, Default=03h) .............................................. 42
8.6.5
Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h)............................ 42
8.6.6
Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h)............................ 42
8.6.7
Serial Port 2 Special Configuration Register 3 (Index=F2h, Default=00h)............................ 43
8.6.8
Serial Port 2 Special Configuration Register 4 (Index=F3h, Default=7Fh)............................ 43
8.7
Parallel Port Configuration Registers (LDN=03h)............................................................................. 43
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IT8710F
8.7.1
Parallel Port Activate (Index=30h, Default=00h) ..................................................................... 43
8.7.2
Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h) ...................... 43
8.7.3
Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h)...................... 44
8.7.4
Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h) ................. 44
8.7.5
Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h) ................ 44
8.7.6
POST Data Port Base Address MSB Register (Index=64h, Default=00h).............................. 44
8.7.7
POST Data Port Base Address LSB Register (Index=65h, Default=80h)............................. 44
8.7.8
Parallel Port Interrupt Level Select (Index =70h, Default=07h).............................................. 44
8.7.9
Parallel Port DMA Channel Select (Index=74h, Default=03h) ............................................... 44
8.7.10
Parallel Port Special Configuration Register (Index=F0h, Default=03h) ............................... 45
8.8
WC Configuration Registers (LDN=04h) ........................................................................................... 45
8.8.1
SWC Status Register 1 (SWC_STS1) (Index=E0h, Default=--)............................................. 45
8.8.2
SWC Status Register 2 (SWC_STS2) (Index=E1h, Default=--)............................................. 46
8.8.3
SWC_STS_1 to PME during VCC ON Enable Register (Index=E2h, Default=00h) ............ 47
8.8.4
SWC_STS_2 to PME during VCC ON Enable Register (Index=E3h, Default=00h) ............ 47
8.8.5
SWC_STS_1 to PME during VCC OFF Enable Register (Index=E4h, Default=00h)........... 48
8.8.6
SWC_STS_1 to SMI during VCC ON Enable Register (Index=E5h, Default=00h) .............. 48
8.8.7
SWC_STS_2 to SMI during VCC ON Enable Register (Index=E6h, Default=00h) .............. 49
8.8.8
SWC_STS_1 to SMI during VCC OFF Enable Register (Index=E7h, Default=00h) ............ 49
8.8.9
Reserved Register (Index=F0h, Default=00h)......................................................................... 49
8.8.10
Reserved Register (Index=F1h, Default=--, VCCH)................................................................ 49
8.8.11
Reserved Register (Index=F2h, Default=00h, VCCH)............................................................ 49
8.8.12
Reserved Register (Index=F4h, Default=00h, VCCH)............................................................ 49
8.8.13
SWC Special Code Index Register (SSC_IDX) (Index=F5h, Default=--, VCCH) ................. 50
8.8.14
SWC Special Code Data Register (SSC_DATA) (Index=F6h, Default=--, VPP) .................. 50
8.9
GPIO Configuration Registers (LDN=07h)........................................................................................ 50
8.9.1
Panel Button De-bounce Interrupt Level Select (Index=70h, Default=0Ch) ............................. 50
8.9.2
GPIO Set 1, 2, 3, 4, 5, and 6 Pin Polarity Registers (Index=B0h, B1h, B2h, B3h, B4h, and
B5h, Default=00h)...................................................................................................................... 50
8.9.3
GPIO Set 1, 2, 3, 4, 5, and 6 Pin Internal Pull-up Enable Registers (Index=B8h, B9h, BAh,
BBh, BCh, and BDh, Default=00h)........................................................................................... 50
8.9.4
GPIO Set 1, 2, 3, 4, 5, and 6 Function Select Registers (Index=C0h, C1h, C2h, C3h, C4h,
and C5h, Default=00h) .............................................................................................................. 50
8.9.5
Simple I/O Set 1, 2, 3, 4, 5, and 6 Input/Output Selection Registers (Index=C8h, C9h, CAh,
CBh, CCh, and CDh, Default=00h) .......................................................................................... 51
8.9.6
Panel Button De-bounce Control Register (Index=D0h, Default=00h).................................. 51
8.9.7
Panel Button De-bounce Set 1, 2, 3, 4, 5, and 6 Enable Registers (Index=D1h, D2h, D3h,
D4h, D5h, and D6h, Default=00h) ............................................................................................ 51
8.9.8
Panel Button De-bounce Set 1, 2, 3, 4, 5, and 6 Status Registers (Index=D7h, D8h, D9h,
DAh, DBh, and DCh, Default=--) .............................................................................................. 51
8.9.9
Simple I/O Set 1, 2, 3, 4, 5, and 6 Data Registers (Index=F0h, F1h, F2h, F3h, F4h, and
F5h, Default=00h)...................................................................................................................... 52
8.9.10
SMI# Pin Mapping Registers .................................................................................................... 52
8.9.11
SMI# Pin Mapping Registers (Index=F6h, Default=00h) ........................................................ 52
8.9.12
GP LED Blinking 1 Pin Mapping Registers (Index=F7h, Default=00h) ................................. 52
8.9.13
GP LED Blinking 1 Control Register (Index=F8h, Default=00h) ............................................ 52
8.9.14
GP LED Blinking 2 Pin Mapping Registers (Index=F9h, Default=00h) ................................. 52
8.9.15
GP LED Blinking 2 Control Register (Index=FAh, Default=00h)............................................ 53
8.9.16
VID Input Register (Index=FBh, Default=--) ............................................................................ 53
8.9.17
VID Output and Control Register (Index=FCh, Default=00h)................................................. 53
8.10
Game Port Configuration Registers (LDN=08h) ............................................................................... 53
8.10.1
Game Port Activate (Index=30h, Default=00h) ....................................................................... 53
8.10.2
Game Port Base Address MSB Register (Index=60h, Default=02h)....................................... 53
8.10.3
Game Port Base Address LSB Register (Index=61h, Default=01h)........................................ 54
8.11
Consumer IR Configuration Registers (LDN=09h) ........................................................................... 54
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Contents
8.11.1
Consumer IR Activate (Index=30h, Default= 00h) .................................................................. 54
8.11.2
Consumer IR Base Address MSB Register (Index=60h, Default=03h)................................... 54
8.11.3
Consumer IR Base Address LSB Register (Index=61h, Default=10h).................................... 54
8.11.4
Consumer IR Interrupt Level Select (Index=70h, Default=0Bh)............................................. 54
8.11.5
Consumer IR Special Configuration Register (Index=F0h, Default=00h) ............................. 54
8.12
MIDI Port Configuration Registers (LDN=0Ah) ................................................................................. 54
8.12.1
MIDI Port Activate (Index=30h, Default= 00h)......................................................................... 54
8.12.2
MIDI Port Base Address MSB Register (Index=60h, Default=03h) ......................................... 55
8.12.3
MIDI Port Base Address LSB Register (Index=61h, Default=10h) .......................................... 55
8.12.4
MIDI Port Interrupt Level Select (Index=70h, Default=0Ah)................................................... 55
8.12.5
MIDI Port Special Configuration Register (Index=F0h, Default=00h).................................... 55
9.
Functional Description ....................................................................................................................................... 57
9.1
LPC Interface ...................................................................................................................................... 57
9.1.1
LPC Transactions ...................................................................................................................... 57
9.1.2
LDRQ# Encoding....................................................................................................................... 57
9.2
Serialized IRQ ..................................................................................................................................... 57
9.2.1
Continuous Mode....................................................................................................................... 57
9.2.2
Quiet Mode................................................................................................................................. 58
9.2.3
Waveform Samples of SERIRQ Sequence ............................................................................. 58
9.2.4
SERIRQ Sampling Slot ............................................................................................................. 59
9.3
General Purpose I/O ........................................................................................................................... 60
9.4
System Wake-up Control (SWC) and ACPI ...................................................................................... 61
9.4.1
SWC General Description......................................................................................................... 61
9.5
Floppy Disk Controller (FDC) ............................................................................................................. 62
9.5.1
Introduction ................................................................................................................................ 62
9.5.2
Reset .......................................................................................................................................... 62
9.5.3
Hardware Reset (LRESET# Pin) .............................................................................................. 62
9.5.4
Software Reset (DOR Reset and DSR Reset) ........................................................................ 63
9.5.5
Digital Data Separator ............................................................................................................... 63
9.5.6
Write Precompensation............................................................................................................. 63
9.5.7
Data Rate Selection................................................................................................................... 63
9.5.8
Status, Data and Control Registers.......................................................................................... 63
9.5.8.1
Digital Output Register (DOR, FDC Base Address + 02h)........................................ 63
9.5.8.2
Tape Drive Register (TDR, FDC Base Address + 03h)............................................. 64
9.5.8.3
Main Status Register (MSR, FDC Base Address + 04h)........................................... 64
9.5.8.4
Data Rate Select Register (DSR, FDC Base Address + 04h) .................................. 65
9.5.8.5
Data Register (FIFO, FDC Base Address + 05h) ...................................................... 66
9.5.8.6
Digital Input Register (DIR, FDC Base Address + 07h)............................................. 66
9.5.8.7
Diskette Control Register (DCR, FDC Base Address + 07h) .................................... 66
9.5.9
Controller Phases ...................................................................................................................... 66
9.5.9.1
Command Phase.......................................................................................................... 67
9.5.9.2
Execution Phase .......................................................................................................... 67
9.5.9.3
Result Phase ................................................................................................................ 67
9.5.9.4
Result Phase Status Registers.................................................................................... 67
9.5.10
Command Set ............................................................................................................................ 69
9.5.11
Data Transfer Commands......................................................................................................... 80
9.5.11.1
READ DATA ................................................................................................................. 80
9.5.11.2
READ DELETED DATA............................................................................................... 81
9.5.11.3
READ A TRACK ........................................................................................................... 81
9.5.11.4
WRITE DATA................................................................................................................ 81
9.5.11.5
WRITE DELETED DATA ............................................................................................. 81
9.5.11.6
FORMAT A TRACK ..................................................................................................... 81
9.5.11.7
SCAN ............................................................................................................................ 82
9.5.11.8
VERIFY ......................................................................................................................... 82
9.5.12
Control Commands.................................................................................................................... 83
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