Features

Live Insertion and Removal Power Manager

Adjustable Power-on slew rate

Autodetect of Load Open Circuit or -VIN

Disconnection

Controlled Time-Delay

Operates from 9 V to External MOSFET Voltage

Limit

Fault Indication Output (microprocessor reset).

Board Insertion/Removal Detector Input

Protection During Turn-On

Low frequency Power Active Filter

Adjustable Electronic Circuit Breaker

undervoltage with GSNSin input

Applications

Arcless card insertion and removal

Central Office Switching Hardware

Circuit Boards From -48 V Distributed Power

Supplies

Circuit Board Power Manager and Noise Filter

Circuit Board Hot Swap Protector and Manager

Electronic Circuit Breaker

Wireless Local Loop Antennas

Cable TV Antenna

1:0321

1:0351

Negative Voltage Hot Swap Controller

with Active Power Filter

Typical Application with Auto-Disconnect Detector

CAUTION: These devices are
sensitvie to electrostatic discharge;
take caution when handling and
assembling this component.

Description

The IXHQ100 is a live insertion and removal hot swap
controller with a built-in power noise filter. It incorpo-
rates all the active circuitry necessary to protect circuit
boards during live insertion or removal (insertion or
removal when the system power is active). Additionally,
the IXHQ100 incorporates two unique features: power
active filter for powerline noise suppression and power
auto-disconnect detector which eliminates the need of
additional staggered pins.

The IXHQ100 shunt regulator ensures a wide operating
voltage range (with the external MOSFET breakdown
voltage as limit). The active power filter reduces power
source output impedance, producing "clean" load
power. The IXHQ100 allows continuous load current
rise adjustments, presettable maximum current limits,
and user selectable fault indication turn off times for
resetting

Ps and other synchronous board level sys-

tems. For added flexibility, GSNSin pin is available to
implement either circuit board insertion/removal detec-
tion or ground detection.

US Patents Pending.

www.ixys.com

98716 (08/14/00)

IXYS reserves the right to change limits, test conditions and dimensions.

Figure 1

Symbol

Definition

Max. Rating

-V

AGND

Voltage applied V

CCin

to AGND Shunt Off: -0.3 V to 16 V

Shunt On: -0.3 V to 14 V
Shunt On for 10 seconds 14V to 16 V
All other pins except V

-0.3 V to V

CCin

+ 0.3 V

VDD

Load Current

60 mA

Maximum Junction Temperature

125

Operating Temperature Range

-40

C to 85

stg

Storage Temperature Range

-40

C to 150

Supply Current with Shunt On

25 mA

Symbol

Parameter

Test Conditions

Min

Typ

Max

Max Units

Units

Supply current

=12 V, V

SHUNToff

= V

all outputs unloaded.

CCSHUNT

shunt regulation

forced to 10 mA

13.8

voltage

when shunt is off

THSHUNToff

SHUNToff input

= 15 V, monitor RST

OUT

1.5

threshold voltage

SHUNToff

SHUNToff input

-1

bias current

THINV

INV input

= 12 V, monitor RST

OUT

threshold voltage

INV

INV input

130

180

resistance

THGSNS

GSNS sense input

= 12 V, monitor RST

OUT

4.5

5.8

threshold voltage

GSNSin

GSNSin input

-2.6

-2.3

-2

bias current

CAPin

CAPin input bias current

-1

VDROP

Active filter offset voltage

0.7

0.9

1.1

VDROP

DROP

input resistance

SLOPE

SLOPE capacitor

OFFTM

= 5 V, V

GSOURCE

= 0 V

110

charging current

CAPin

= 5 V

SLOPEDCHG

SLOPE capacitor

DROP

= 5 V, IVT = V

200

discharge resistance

SOURCE

= 0 V, V

CAPin

= 5 V

OFFTM

OFFTM capacitor

DROP

= 5 V, V

SOURCE

= 0 V

100

120

charging current

CAPin

= 5 V

OFFTMCHG

OFFTM capacitor

111

200

discharge resistance

THOFFTM

OFFTM input threshold

OFFTM input voltage when SLOPE

3.8

4.5

5.5

voltage

input voltage starts its ramp

Overcurrent threshold bias voltage

125

150

Pin Description

Unless otherwise noted, T

= 25

C; -V

= 48 V, AGND connected to -V

, V

SHUNToff

= 5 V, V

= 12 V, V

GSNSin

= 12 V. All voltage measurements

with respect to AGND. IXHQ100 configured as described in

Test Conditions.

Electrical Characteristics

Absolute Maximum Ratings

IXHQ 100PI

IXHQ 100SI

Electrical Characteristics

Electrical Characteristics (continued)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Max Units

Units

VCL

VCL bias resistance

Overcurrent detection

CAPin

= 0 V; V

OUTsns

= 5 V

to GATE output delay

SOURCE

input is a step at t = 0s

from 0 V to 200 mV

GATE

/dt

GATE output slew rate

SLOPE

= 100 nF

0.5

0.8

1.1

V/ms

GATE

Maximum GATE

CAPin

= 0 V; R

load

= 10 K

13.8

output voltage

OUTsns

= 5 V

GATE

GATE pull-up current

Gate drive on, V

GATE

= 0 V

-15

-10

GATE

GATE pull-down

Gate drive off

current

GATE

= 10 V

regulator output

3.3K Resistive load

5.75

6.5

Voltage

between V

output and AGND

RSTout

RSTout drive current

Force V

RSTout

=1 V during fault condition

2.4

3.6

RST

RST pulse width

200

500

1000

Auto-Detect threshold

Gate drive on; ramp V

OUTsns

; monitor

-10

RST until it pulses.

Note 1: Operating the device beyond parameters with listed "absolute maximum ratings" may cause permanent damage to the
device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific
performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
Note2: All voltages are relative to ground unless otherwise specified.

Typical Performance Characteristics

IXHQ 100PI

IXHQ 100SI

Graph 1: Icc vs. Temperature

Temperature (oC)

-60

-40

-20

100

Icc (mA)

1.96

1.98

2.00

2.02

2.04

2.06

2.08

2.10

2.12

2.14

2.16

2.18

Temperature (oC)

-60 -40 -20

20 40

60 80 100

Reg

l
a

t
o

r
Ou

t
put

Vol

t
a

ge (

)

5.4

5.5

5.6

5.7

5.8

5.9

6.0

Graph 2: Regulator Output Voltage vs. Temperature

IXHQ 100PI

IXHQ 100SI

Graph 3: SLOPE Pin current vs. Temperature

Graph 4: OFFTM Threshold Voltage vs. Temperature

Graph 5: Vcc Shunt Voltage vs. Temperature

Graph 6: Overcurrent Threshold Voltage vs. Temperature

Graph 8: Vdrop Voltage vs. Temperature

Graph 7: Supply Current vs. Shunt Voltage

Vshunt (V)

Supply

Cur

r
e

t
(

)

Temperature (oC)

-60 -40 -20

80 100

Vdr

op Vol

t
ag

e (

)

0.84

0.86

0.88

0.90

0.92

0.94

0.96

0.98

1.00

Temperature (oC)

-60

-40

-20

100

Vcc

hunt Volt

e (

)

13.2

13.4

13.6

13.8

14.0

14.2

14.4

Temperature (oC)

-60

-40

-20

100

Slope Cur

r
ent

(

Temperature (oC)

-60

-40

-20

100

Vcl Volt

e (

)

118

120

122

124

126

128

130

132

134

136

Temperature (oC)

-60

-40

-20

100

FFT

r
e

shold Volt

e (

)

ICC = 1mA

Frequency (Hz)

1e+1 1e+2 1e+3 1e+4 1e+5 1e+6

Att

nuati

on (

-70

-60

-50

-40

-30

-20

-10

Pin Descriptions

IXHQ 100PI

IXHQ 100SI

Supply Voltage (V)

100

120

l
t
a

)

Graph 9: Gate Voltage vs. Supply Voltage

Graph 10: Typical Noise Attenuation

PIN #

SYMBOL

FUNCTION

DESCRIPTION

INV

Invert

Input

The invert input controls GSNSin's polarity. When
invert input is high compared to AGND, then GSNSin
low indicates an insertion/removal event. When invert
input is low, then GSNSin high indicates an
insertion/removal event.

15 GSNSin

Ground Sense

Input

The INV pin controls the polarity sense of this input.
A 3uA internal pull-up current source causes logic
high when there is no connection at this pin. With INV
low or connected to AGND, a GSNSin low (or
connected to AGND) will keep RSTout and GATE
low, and the external power switch, Q1, off. A
disconnected GSNSin pin or when Vcc is applied to it
will allow normal operation

VCCin

Supply Voltage Positive power-supply voltage input.

3 SHNToff Shunt

Off

This pin serves to control the enabling of the shunt
circuit. When the pin is high compared to AGND, then
the shunt regulator is in off position. A low level at
this pin activates the shunt regulator.

4 CAPin

Active low-

pass filter

capacitor input

The output of the power active filter tracks this pin.
Adding an external RC network matching the input
noise with respect to the 3db point of the filter could
reduce the noise to a minimum.

5 VDROP

Active filter

offset voltage

This pin sets the drop out MOSFET voltage across the
active filter.

6 SLOPE Slope

input

This input controls the current slope during power up
and controls inrush currents. Adding external
capacitors to this pin allow regulation and adjustment
of the rate of the current slope.

7 OFFTM Off-time

The OFFTM pin sets the delay time between power-
down and restart of IXHQ100. Delay time can be
increased by adding external capacitors to this pin.

AGND

Ground

The IXHQ100 system zero reference pin.

IXHQ100 Logic Dia

IXHQ100 Logic Diagram

gram

Pin Descriptions

Pin Descriptions (continued)

IXHQ 100PI

IXHQ 100SI

Figure 2

PIN #

SYMBOL

FUNCTION

DESCRIPTION

9 VDDout

Regulator

output voltage

Regulator output voltage provides current to drive the
external circuits with respect to AGND.

10 VCL

Overcurrent

threshold bias

voltage

Sets the overcurrent threshold bias voltage.

11 SOURCE

Current input

sensor

Input for sensing current through power device with
respect to AGND.

GATE

Output

Control voltage for driving external MOSFET.

13 OUTsns

Out sensor

signal

This signal senses the output voltage of the circuit.

14 RSTout Output

Reset

A low at this pin indicates detection of an
insert/removal event or overcurrent detection.

16 NC

N/A Not

Connected

the external load, V

load

, is zero. As V

SLOPE

rises,

its rate of increase determined by the value of
the external capacitor, C8 (figure1), and the
value of the internal current source, I5. V

GATE

rate of increase follows V

SLOPE.

As soon as V

GATE

exceeds V

thQ1

(figure 1) of the external power

MOSFET, drain current I

dQ1

starts to flow. The

rate of increase of I

dQ1

is proportional to the rate

of increase of V

SLOPE

, and is independent of the

size of C5 , the total filter capacitance of the
load. Note that this rate, which is directly
proportional to C7 and inversely proportional to
C8, could be adjusted . Similarly the Toff-delay
can be adjusted and is directly proportional to
the size of C7.

DEVICE OPERA

DEVICE OPERATION*

TION*

A hot swap operation involves removal and
reinsertion of a device while the system using
it remains in operation. Such an operation
could cause external capacitors to draw cur-
rents high enough to disturb system operations
or even cause permanent damage to both the
device and the system.

The IXHQ100 is designed to prevent any distur-
bances or damage during such occurrences,
allowing the circuit board to be safely inserted
and removed from a live backplane. Capable of
operating under three modes, the chip also acts
as a power active noise filter and an auto-detect
circuit.

Once power is applied, the IXHQ100 starts up
but does not immediately apply power to the
output load. The internal Power Up Reset logic
(see in Figure 2) turns on for 10

s prior to any

other logic. This pulse goes through two NOR
gates and resets SRFF1 Flip Flop. Once SRFF1
is reset, the current source, I6, charges the
OFFTM pin at a rate proportional to the size of
the external capacitor, C7 (fig 1). During the time
the OFFTM pin is ramping from 0V to Vrf (~5V),
which is the T

off-delay

, COMP1 keeps N3 ON so

SLOPE

stays at 0V. After T

off-delay

,,
,,
, V

OFFTM

ecomes

greater than Vrf, and COMP1 goes low, driving
N3 to off state. I5 now starts to charge C1,
ramping +ve i/p of OA4. OA4 buffers V

SLOPE

and

sets the GATE output ramp.

It is assumed that when the circuit board is first
inserted into the backplane, the voltage across

Inser

Insertion Pr

tion Pr

tion Process

ocess

As the circuit board is inserted into the
backplane, physical connections should be
made to ground to discharge any electrostatic
voltage. The insertion process begins when
power and ground are supplied to the board
through pins on the blackplane.

IXHQ 100PI

IXHQ 100SI

Normal Operation

Flip-flop setting and resetting

*Unless otherwise stated, all symbol and device references are referred to the logic diagram (Fig 2) on page 6

The flip-flop, SRFF1 (fig 2), used in the IXHQ100,
is reset dominant. Hence when both S and R
inputs are driven high, the SRFF1 remains
reset. Under normal operation, S input becomes
high whenever OR1 output is high and R input
is low. In turn, OR1 goes high if any one of the
outputs of EXOR1, or COMP2, or COMP3
goes high.

EXOR1 output goes high if it detects the loss of
either Gnd or -Vin. If INV input is connected to

With continuous V

applied, the IXHQ100

acts as an active power filter by modulating the
voltage drop across the external Power
MOSFET V

so that any noise on V

cancelled by V

The direct connection of IXHQ 100's AGND pin
to V

allows the V

drop

(internally set to ~750mV)

to set the ~90% of the maximum peak noise
voltage reject by the IXHQ100. The internal
V

drop

setting of ~750 mV allows 1.35 Vpp of

noise rejection. Graph on page 5 illustrates the
level of ripple attenuation during normal
conditions. Notice that the noise rejection is very
high (~60db) between 400Hz to 40KHz, which is
optimal for most hot swap applications.

Fault Operation

ault Operation

When the output load current is such that the
voltage drop across the current sense resistor
between the SOURCE pin and the AGND
exceeds VCL (internally set to ~120 mv), the
GATE output is driven low to turn off the external
Power MOSFET connected between the load
and -V

. An external capacitor connected

between OFFTM pin and AGND pin determines
the off time T

off-delay.

IXHQ100 will restart the turn

on sequence of the external Power MOSFET
with a load voltage slope determined by the
size of the external capacitor that is connected
to the SLOPE pin.

Shor

Short Cir

t Cir

t Circuit Pre

cuit Pre

cuit Prevention

vention

Restar

Restart Operation

t Operation

IXHQ 100PI

IXHQ 100SI

Vcc, then GSNSin pin can be used to detect
the presence or absence of -Vin. If INV is
connected to AGND, then GSNSin pin can be
used to detect the presence or absence of
Gnd.

COMP2 output goes high whenever an
overcurrent or a short circuit condition is
detected. The inverting input to COMP2 is
connected to the VCL output pin which is
internally set at approximately 120mV. As
shown in Figure 1, one side of R4 is in series
with the source of Q1, the drain output of which
drives the load connected to J8. The return
side of R4 is connected to -Vin through J1. For
R4 = 0.02

, Q1 source currents greater than

6A will turn on COMP2 and will be considered
either an overcurrent or short circuit event.

COMP3 goes high whenever the voltage at
OUTsns with respect to AGND becomes less
than 0.1*VCL(approximately 12mV). This can
only occur if either the current drawn by the driven
load is less than 600mA (12mV/.02) or -V

disconnected. This Auto-Disconnect technique
automatically detects load disconnections
without needing additional sensors.

Thus the SRFF1 will reset when one of the
following events occur:

1. Loss of AGND or -Vin.
2. Overcurrent or short circuit.
3. Auto-Disconnection

A valid S input into SRFF1 will immediately
drive its output, Q1, to high and will turn on both
N5 and N4. N5, an open drain output, will result
in RSTout being driven low. A current limiting
resistor, R1, in series with a 4N35 LED
connected to V

(fig 1) can be used to

generate an isolated reset pulse. Turning on
N4 will discharge C7 and the internal 10pF
capacitor (fig 2). As soon as V

OFFTM

drops below

DROP

=~0.9V, COMP4 in Figure 2 will turn on

through NOR1 and NOR2, and resets SRFF1

with a high applied to its R input. This act will
then turn off both N5 and N4 and allow OFFTM
pin to initiate its positive ramp as a result of I6
charging the capacitors C7 (Figure 1) and C2
(Figure 2) connected to the OFFTM pin.

The IXHQ100 will automatically attempt to
restart once a disconnection and reconnection
is detected. Either PUR or COMP4 going high
will reset SRFF1 during normal operation of
the IXHQ100 (fig 2). Resetting SRFF1 turns off
N4 and N5, and the OFFTM pin ramps up in
response. During this ramp, as long as V

OFFTM

is less than Vrf=~4.5V, COMP1 will keep N3 on
and C1 (Figure 2) and C8 (Figure 1) discharged.
After T

off-delay,

OFFTM

is at Vrf, COMP1 output

then goes low, turning off N3. Now the SLOPE
pin is free to ramp up as a result of I5 charging
C1 (Figure 2) and C8 (Figure 1). The two unity-
gain buffers, OA4 and OA5, reflect V

SLOPE

at the

GATE output pin during this positive ramp. As
soon as V

GATE

overcomes the V

Q1th

, normal

operation is resumed.

When the IXHQ100 detects a short in the load,
a restart is automatically initiated. The GOUT
drops to zero and waits one T

off-delay

before

SLOPE ramps up. As before, normal operation
is resumed.

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