Document Outline
- Features
- Description
- VTERM
- Terminal Voltage with Respect to VSS
- 0.5 to +4.6
- 0.5 to +4.6
- 0.5 to +4.6
- V
- TBIAS
- Temperature Under Bias
- 55 to +125
- 65 to +135
- 65 to +145
- C
- TSTG
- Storage Temperature
- 55 to +125
- 65 to +150
- 65 to +150
- C
- PT
- Power Dissipation
- 900
- 900
- 900
- mW
- IOUT
- DC Output Current
- 50
- 50
- 50
- mA
- Tj
- Maximum Junction Temperature (2)
- 125
- 125
- 125
- C
- VCC
- Supply Voltage
- 3.0
- 3.3
- 3.6
- V
- VSS
- Supply Voltage
- 0
- 0
- 0
- V
- Industrial
- Ambient Temperature
- 40
- 25
- 85
- C
- Commercial
- Ambient Temperature
- 0
- 25
- 70
- C
- ILI
- Input Leakage Current
- VCC = Max., VIN = VSS to VCC
- Coml/
- Ind.
- 5
- 5
- A
- ILO
- Output Leakage Current
- VCC = Max.,
- CE = VIH, VOUT = VSS to VCC
- Coml/
- Ind.
- 5
- 5
- A
- VIL
- Input Low Voltage
- 0.3(1)
- 0.8
- V
- VIH
- Input High Voltage
- 2.2
- Vcc+0.3
- V
- VOL
- Output Low Voltage
- IOL = 8 mA, VCC = Min.
-
- 0.4
- V
- VOH
- Output High Voltage
- IOH = 4 mA, VCC = Min.
- 2.4
-
- V
- ICC
- Operating Current
- CE = VIL
- 125
- 115
- 110
- 115
- 100
- 105
- 110
- 90
- 95
- 110
- mA
- f = fMAX = 1/tRC
- VCC = Max.
- IOUT = 0 mA
- ISB
- Standby Current
- CE = VIH
- 20
- 20
- 20
- 20
- 20
- 20
- 30
- 20
- 20
- 30
- mA
- f = fMAX = 1/tRC
- VCC = Max.
- ISB1
- Full Standby Current
- CE VCC 0.2V
- 5
- 5
- 5
- 5
- 5
- 5
- 10
- 5
- 5
- 10
- mA
- f = 0
- VCC = Max.,
- VIN VCC 0.2V or 0.2V
- Functional Block Diagram
- CIN
- Input Capacitance
- 8
- pF
- COUT
- Output Capacitance
- 8
- pF
- Input pulse levels
- VSS to 3.0V
- Input rise and fall times
- 2.5 ns
- Input timing reference levels
- 1.5V
- Output reference levels
- 1.5V
- Output load
- See Figures 1 and 2
- Pin Configuration
- SOJ
- L
- L
- H
- DOUT
- Read
- L
- X
- L
- DIN
- Write
- L
- H
- H
- Hi-Z
- Output Disable
- H
- X
- X
- Hi-Z
- Standby
- A16-A0
- Address Inputs
- I/O7-I/O0
- Data Inputs/Outputs
- OE
- Output Enable Input
- WE
- Write Enable Input
- CE
- Chip Enable Input
- NC
- No Connect
- VCC
- Power (+3.3V)
- VSS
- Ground
- READ cycle time
- tRC
- 9
- 10
- 12
- 15
- 20
- ns
- Address access time
- tAA
- 9
- 10
- 12
- 15
- 20
- ns
- Chip enable access time
- tACE
- 9
- 10
- 12
- 15
- 20
- ns
- Output hold from address change
- tOH
- 3
- 3
- 3
- 3
- 3
- ns
- Chip enable to output in low Z(1,3)
- tLZCE
- 3
- 3
- 3
- 3
- 3
- ns
- Chip disable to output in high Z(1,2,3)
- tHZCE
- 5
- 6
- 7
- 8
- 9
- ns
- Chip enable to power up time(3)
- tPU
- 0
- 0
- 0
- 0
- 0
- ns
- Chip disable to power down time(3)
- tPD
- 9
- 10
- 12
- 15
- 20
- ns
- Output enable access time
- tAOE
- 5
- 6
- 7
- 8
- 9
- ns
- Output Enable to output in low Z (1,3)
- tLZOE
- 0
- 0
- 0
- 0
- 0
- ns
- Output disable to output in high Z(1,3)
- tHZOE
- 5
- 6
- 7
- 8
- 9
- ns
- WRITE cycle time
- tWC
- 9
- 10
- 12
- 15
- 20
- ns
- Chip enable active time
- tCW
- 8
- 9
- 10
- 11
- 12
- ns
- Address valid to end of write
- tAW
- 8
- 9
- 10
- 11
- 12
- ns
- Address setup time
- tAS
- 0
- 0
- 0
- 0
- 0
- ns
- Address hold from end of write
- tAH
- 0
- 0
- 0
- 0
- 0
- ns
- Write pulse width
- tWP
- 7
- 8
- 9
- 10
- 11
- ns
- Data setup time
- tDS
- 5
- 6
- 7
- 8
- 9
- ns
- Data hold time
- tDH
- 0
- 0
- 0
- 0
- 0
- ns
- Write disable to output in low Z(1,3)
- tLZWE
- 0
- 0
- 0
- 0
- 0
- ns
- Write enable to output in high Z(1,3)
- tHZWE
- 6
- 7
- 7
- 8
- 9
- ns
- PDM31034
- 1 Megabit 3.3V Static RAM
- 128K x 8-Bit
- Revolutionary Pinout
Rev. 1.3
1
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
1 Megabit 3.3V Static RAM
128K x 8-Bit
Revolutionary Pinout
Features
n
High-speed access times
Com'l: 9, 10, 12, 15 and 20 ns
Ind'l.: 12, 15 and 20 ns
Automotive: 15 and 20 ns
n
Low power operation (typical)
- PDM31034SA
Active: 200 mW
Standby: 15 mW
n
Single +3.3V (
0.3V) power supply
n
TTL-compatible inputs and outputs
n
Packages
Plastic SOJ (400 mil) - SO
Plastic SOJ (300 mil) - TSO
Plastic TSOP (II) - T
Description
The PDM31034 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. Writing is
accomplished when the write enable (WE) and the
chip enable (CE) inputs are both LOW. Reading is
accomplished when WE remains HIGH and CE and
OE are both LOW.
The PDM31034 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31034 is available in a 32-pin 400 mil plas-
tic SOJ and 300 mil plastic SOJ, and a 32-pin plastic
TSOP (II) package in revolutionary pinout.
PDM31034
A16
I/O0
I/O7
CE
WE
Addresses
Row
Address
Buffer
Memory
Array
512 x 256 x 8
(1,048,576)
Input
Data
Control
OE
Control
Column Address
Buffer
A9
Column I/O
A8
A0
Row
Decoder
Column Decoder
Functional Block Diagram
PRELIMINARY
PDM31034
2
Rev. 1.3
Absolute Maximum Ratings
(1)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-
culation should be of the form
: T
j
= T
a
+ P *
ja
where T
a
is the ambient temperature, P
is average operating power and
ja
the thermal resistance of the package. For this
product, use the following
ja
values:
SOJ: 72
o
C/W
TSOP: 95
o
C/W
Symbol
Rating
Com'l.
Ind.
Auto.
Unit
V
TERM
Terminal Voltage with Respect to V
SS
0.5 to +4.6
0.5 to +4.6
0.5 to +4.6
V
T
BIAS
Temperature Under Bias
55 to +125
65 to +135
65 to +145
C
T
STG
Storage Temperature
55 to +125
65 to +150
65 to +150
C
P
T
Power Dissipation
900
900
900
mW
I
OUT
DC Output Current
50
50
50
mA
T
j
Maximum Junction Temperature
(2)
125
125
125
C
A3
A2
A1
A0
CE
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE
A16
A15
A14
A13
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A4
A5
A6
A7
OE
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A8
A9
A10
A11
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
21
22
23
24
A3
A2
A1
A0
CE
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE
A16
A15
A14
A13
A4
A5
A6
A7
OE
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A8
A9
A10
A11
A12
13
14
25
26
27
28
29
30
31
32
Truth Table
(1)
NOTE: 1. H = V
IH
, L = V
IL
, X = DON'T CARE
CE
OE
WE
I/O
MODE
L
L
H
D
OUT
Read
L
X
L
D
IN
Write
L
H
H
Hi-Z
Output Disable
H
X
X
Hi-Z
Standby
Pin Description
Name
Description
A16-A0
Address Inputs
I/O7-I/O0
Data Inputs/Outputs
OE
Output Enable Input
WE
Write Enable Input
CE
Chip Enable Input
NC
No Connect
V
CC
Power (+3.3V)
V
SS
Ground
Pin Configuration
SOJ
TSOP
PRELIMINARY
PDM31034
Rev. 1.3
3
1
2
3
4
5
6
7
8
9
10
11
12
Recommended DC Operating Conditions
DC Electrical Characteristics
(V
CC
= 3.3V
0.3V)
NOTE:1.V
IL
(min) = 3.0V for pulse width less than 20 ns
Power Supply Characteristics
NOTES: All values are maximum guaranteed values.
1. V
CC
= 3.3V + 5%
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
V
SS
Supply Voltage
0
0
0
V
Industrial
Ambient Temperature
40
25
85
C
Commercial
Ambient Temperature
0
25
70
C
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
LI
Input Leakage Current
V
CC
= Max., V
IN
= V
SS
to V
CC
Com'l/
Ind.
5
5
A
I
LO
Output Leakage Current
V
CC
= Max.,
CE = V
IH
, V
OUT
= V
SS
to V
CC
Com'l/
Ind.
5
5
A
V
IL
Input Low Voltage
0.3
(1)
0.8
V
V
IH
Input High Voltage
2.2
Vcc+0.3
V
V
OL
Output Low Voltage
I
OL
= 8 mA, V
CC
= Min.
--
0.4
V
V
OH
Output High Voltage
I
OH
= 4 mA, V
CC
= Min.
2.4
--
V
-9
(1)
-10
(1)
-12
-15
-20
Symbol Parameter
Com'l.
Com'l.
Com'l
Ind.
Com'l
Ind.
Auto. Com'l
Ind.
Auto.
Unit
I
CC
Operating Current
CE = V
IL
125
115
110
115
100
105
110
90
95
110
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
20
20
20
20
20
20
30
20
20
30
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
V
CC
0.2V
5
5
5
5
5
5
10
5
5
10
mA
f = 0
V
CC
= Max.,
V
IN
V
CC
0.2V or
0.2V
PRELIMINARY
PDM31034
4
Rev. 1.3
Capacitance
(1)
(T
A
= +25
C, f = 1.0 MHz)
NOTE:1. This parameter is determined by device characterization but is not production tested.
AC Test Conditions
Symbol
Parameter
Max.
Unit
C
IN
Input Capacitance
8
pF
C
OUT
Output Capacitance
8
pF
Input pulse levels
V
SS
to 3.0V
Input rise and fall times
2.5 ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
,
t
HZOE
)
+3.3V
+3.3V
317
317
351
351
D
OUT
D
OUT
30 pF
5 pF
PRELIMINARY
PDM31034
Rev. 1.3
5
1
2
3
4
5
6
7
8
9
10
11
12
Read Cycle No. 1
(4, 5)
Read Cycle No. 2
(2, 4, 6)
AC Electrical Characteristics
Description
-9
-10
-12
-15
-20
READ Cycle
Sym
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
READ cycle time
t
RC
9
10
12
15
20
ns
Address access time
t
AA
9
10
12
15
20
ns
Chip enable access time
t
ACE
9
10
12
15
20
ns
Output hold from address change
t
OH
3
3
3
3
3
ns
Chip enable to output in low Z
(1,3)
t
LZCE
3
3
3
3
3
ns
Chip disable to output in high Z
(1,2,3)
t
HZCE
5
6
7
8
9
ns
Chip enable to power up time
(3)
t
PU
0
0
0
0
0
ns
Chip disable to power down time
(3)
t
PD
9
10
12
15
20
ns
Output enable access time
t
AOE
5
6
7
8
9
ns
Output Enable to output in low Z
(1,3)
t
LZOE
0
0
0
0
0
ns
Output disable to output in high Z
(1,3)
t
HZOE
5
6
7
8
9
ns
t
RC
t
AA
t
OH
PREVIOUS DATA VALID
DOUT
ADDR
DATA VALID
t
RC
t
ACE
t
AA
t
LZCE
t
HZCE
t
LZOE
t
HZOE
t
AOE
ADDR
CE1
CE2
OE
D
OUT
DATA VALID
PDF 
ZIP