Document Outline
- Pin Configuration
- VTERM
- Terminal Voltage with Respect to VSS
- 0.5 to +4.6
- 0.5 to +4.6
- V
- TBIAS
- Temperature Under Bias
- 55 to +125
- 65 to +135
- C
- TSTG
- Storage Temperature
- 55 to +125
- 65 to +150
- C
- PT
- Power Dissipation
- 1.5
- 1.5
- W
- IOUT
- DC Output Current
- 50
- 50
- mA
- Tj
- Maximum Junction Temperature (2)
- 125
- 145
- C
- VCC
- Supply Voltage
- 3.0
- 3.3
- 3.6
- V
- VSS
- Supply Voltage
- 0
- 0
- 0
- V
- Industrial
- Ambient Temperature
- 40
- 25
- 85
- C
- Commercial
- Ambient Temperature
- 0
- 25
- 70
- C
- ICC
- Operating Current
- CE = VIL
- 220
- 210
- 200
- 210
- 190
- 200
- 185
- 195
- mA
- f = fMAX = 1/tRC
- VCC = Max.
- IOUT = 0 mA
- ISB
- Standby Current
- CE = VIH
- 50
- 45
- 40
- 45
- 35
- 40
- 30
- 35
- mA
- f = fMAX = 1/tRC
- VCC = Max.
- ISB1
- Full Standby Current
- CE VCC 0.2V
- 10
- 10
- 10
- 15
- 10
- 15
- 10
- 15
- mA
- f = 0
- VCC = Max.,
- VIN VCC 0.2V or 0.2V
- Features
- n High-speed access times - Coml: 8, 10, 12, 15, ...
- n Low power operation (typical) - PDM31564SA Activ...
- n High-density 256K x 16 architecture
- n 3.3V (0.3V) power supply
- n Fully static operation
- n TTL-compatible inputs and outputs
- n Output buffer controls: OE
- n Data byte controls: LB, UB
- n Packages:
- Plastic SOJ (400 mil) - SO Plastic TSOP (II) - T
- SOJ
- Read
- L
- L
- H
- L
- L
- Output
- Output
- ICC
- H
- L
- High Impedance
- Output
- ICC
- L
- H
- Output
- High Impedance
- ICC
- Write
- L
- X
- L
- L
- L
- Input
- Input
- ICC
- H
- L
- High Impedance
- Input
- ICC
- L
- H
- Input
- High Impedance
- ICC
- Output Disable
- L
- H
- H
- X
- x
- High Impedance
- High Impedance
- ICC
- L
- X
- X
- H
- H
- High Impedance
- High Impedance
- ICC
- Standby
- H
- X
- X
- X
- X
- High Impedance
- High Impedance
- ISB
- WRITE cycle time
- tWC
- 8
-
- 10
-
- 12
-
- 15
-
- 20
-
- ns
- Chip enable to end of write
- tCW
- 7
-
- 8
-
- 10
-
- 11
-
- 13
-
- ns
- Address valid to end of write
- tAW
- 7
-
- 8
-
- 10
-
- 11
-
- 13
-
- ns
- Byte pulse width
- tBW
- 7
-
- 8
-
- 10
-
- 12
-
- 13
-
- ns
- Address setup time
- tAS
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Address hold from end of write
- tAH
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Write pulse width
- tWP
- 7
-
- 8
-
- 8
-
- 9
-
- 10
-
- ns
- Data setup time
- tDS
- 5
-
- 6
-
- 7
-
- 8
-
- 9
-
- ns
- Data hold time
- tDH
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Byte disable to output in low Z(1, 3, 4)
- tLZBE
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Byte enable to output in high Z(1, 3, 4)
- tHZBE
-
- 6
-
- 6
-
- 7
-
- 8
-
- 9
- ns
- Output disable to output in low Z(1, 3, 4)
- tLZOE
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Output enable to output in high Z(1, 3, 4)
- tHZOE
-
- 6
-
- 6
-
- 7
-
- 7
-
- 8
- ns
- Write disable to output in low Z(1,3, 4)
- tLZWE
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Write enable to output in high Z(1, 3, 4)
- tHZWE
-
- 6
- 6
-
-
- 7
-
- 7
-
- 9
- ns
- Ordering Information
- READ cycle time
- tRC
- 8
-
- 10
-
- 12
-
- 15
-
- 20
-
- ns
- Address access time
- tAA
-
- 8
-
- 10
-
- 12
-
- 15
-
- 20
- ns
- Chip enable access time
- tACE
-
- 8
-
- 10
-
- 12
-
- 15
-
- 20
- ns
- Byte access time
- tBA
-
- 5
-
- 6
-
- 7
-
- 8
-
- 9
- ns
- Output hold from address change
- tOH
- 4
-
- 4
-
- 4
-
- 4
-
- 4
-
- ns
- Byte disable to output in low-Z(1)
- tLZBE
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Byte enable to output in high-Z(1)
- tHZBE
-
- 4
-
- 5
-
- 8
-
- 9
-
- 9
- ns
- Chip enable to output in low-Z(1)
- tLZCE
- 3
-
- 3
-
- 4
-
- 4
-
- 5
-
- ns
- Chip disable to output high-Z(1, 2)
- tHZCE
-
- 4
-
- 5
-
- 6
-
- 7
-
- 8
- ns
- Output enable access time
- tAOE
-
- 4
-
- 5
-
- 6
-
- 7
-
- 10
- ns
- Output enable to output in low-Z(1)
- tLZOE
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Output disable to output in high-Z(1, 2)
- tHZOE
-
- 4
-
- 5
-
- 5
-
- 6
-
- 6
- ns
- ILI
- Input Leakage Current
- VCC = Max., VIN = Vss to VCC
- Coml/
- Ind.
- 5
- 5
- mA
- ILO
- Output Leakage Current
- VCC= Max.,
- CE = VIH, VOUT = Vss to VCC
- Coml/
- Ind.
- 5
- 5
- mA
- VIL
- Input Low Voltage
- 0.3(1)
- 0.8
- V
- VIH
- Input High Voltage
- 2.2
- Vcc + 0.3
- V
- VOL
- Output Low Voltage
- IOL = 8 mA, VCC = Min.
-
- 0.4
- V
- VOH
- Output High Voltage
- IOH = 4 mA, VCC = Min.
- 2.4
-
- V
- CIN
- Input Capacitance
- VIN = VSS
- 6
- pF
- CI/O
- Output Capacitance
- VI/O = VSS
- 8
- pF
- A17-A0
- Address Inputs
- I/O15-I/O0
- Data Inputs
- CE
- Chip Enable Input
- WE
- Write Enable Input
- OE
- Output Enable Input
- LB, UB
- Data Byte Control Inputs
- NC
- No Connect
- Vss
- Ground
- VCC
- Power (+3.3V)
- TSOP (II)
- Write Cycle 1 Timing Diagram (WE Controlled)
- Write Cycle 2 Timing Diagram (CE Controlled)
- Input pulse levels
- VSS to 3.0V
- Input rise and fall times
- 2.5 NS
- Input timing reference levels
- 1.5V
- Output reference levels
- 1.5V
- Output load
- See Figures 1 and 2
- Write Cycle 3 Timing Diagram (UB, LB Controlled)
- PDM31564
- 256K x 16 CMOS
- 3.3V Static RAM
- Read Timing Diagram
Rev. 1.2 - 3/31/98
1
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
PDM31564
Description
The PDM31564 is a high-performance CMOS static
RAM organized as 262,144 x 16 bits. The PDM31564
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM31564 operates from a single 3.3V power
supply and all inputs and outputs are fully TTL-
compatible.
The PDM31564 is available in a 44-pin 400-mil plas-
tic SOJ and a plastic TSOP package for high-density
surface assembly and is suitable for use in high-
speed applications requiring high-speed storage.
PDM31564
256K x 16 CMOS
3.3V Static RAM
A7-A0
Memory
Cell
Array
256 x 128 x 32
Row Address
Buffer
Control
Logic
Sense Amp
Column
Decoder
Column
Address
Buffer
Row Decoder
Clock
Generator
A15-A8
CE
LB
UB
OE
WE
Data
Input/
Output
Buffer
Vcc
Vss
I/O15-I/O0
Features
n
High-speed access times
- Com'l: 8, 10, 12, 15, and 20 ns
- Ind: 12, 15, and 20 ns
n
Low power operation (typical)
- PDM31564SA
Active: 300 mW
Standby: 25mW
n
High-density 256K x 16 architecture
n
3.3V (
0.3V) power supply
n
Fully static operation
n
TTL-compatible inputs and outputs
n
Output buffer controls: OE
n
Data byte controls: LB, UB
n
Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
512 x 256 x 32
A8 - A0
A17 - A9
PDM31564
2
Rev. 1.2 - 3/31/98
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
15
16
29
30
31
32
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
13
14
33
34
35
36
37
38
39
40
41
42
43
44
19
20
21
22
17
18
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
15
16
29
30
31
32
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
13
14
33
34
35
36
37
38
39
40
41
42
43
44
19
20
21
22
17
18
23
24
25
26
27
28
Pin Configuration
SOJ
Capacitance
(T
A
= +25
C, f = 1.0 MHz)
NOTE: This parameter is determined by device characterization, but is not production tested.
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= V
SS
6
pF
C
I/O
Output Capacitance
V
I/O
= V
SS
8
pF
Pin Description
Name
Description
A17-A0
Address Inputs
I/O15-I/O0
Data Inputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
LB, UB
Data Byte Control Inputs
NC
No Connect
V
ss
Ground
V
CC
Power (+3.3V)
TSOP (II)
PDM31564
Rev. 1.2 - 3/31/98
3
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
Operating Mode
NOTE: H = V
IH
, L = V
IL
, X = DON'T CARE
Mode
CE
OE
WE
LB
UB
I/O7-I/O0
I/O15-I/O8
Power
Read
L
L
H
L
L
Output
Output
I
CC
H
L
High Impedance
Output
I
CC
L
H
Output
High Impedance
I
CC
Write
L
X
L
L
L
Input
Input
I
CC
H
L
High Impedance
Input
I
CC
L
H
Input
High Impedance
I
CC
Output Disable
L
H
H
X
x
High Impedance
High Impedance
I
CC
L
X
X
H
H
High Impedance
High Impedance
I
CC
Standby
H
X
X
X
X
High Impedance
High Impedance
I
SB
Absolute Maximum Ratings
(1)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form
: T
j
= T
a
+ P *
ja
where T
a
is the ambient tempera-
ture, P is average operating power and
ja
the thermal resistance of the package. For
this product, use the following
ja
values:
SOJ: 59
o
C/W
TSOP: 87
o
C/W
Recommended DC Operating Conditions
Symbol
Rating
Com'l.
Ind.
Unit
V
TERM
Terminal Voltage with Respect to V
SS
0.5 to +4.6
0.5 to +4.6
V
T
BIAS
Temperature Under Bias
55 to +125
65 to +135
C
T
STG
Storage Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
1.5
1.5
W
I
OUT
DC Output Current
50
50
mA
T
j
Maximum Junction Temperature
(2)
125
145
C
Symbol
Description
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
V
SS
Supply Voltage
0
0
0
V
Industrial
Ambient Temperature
40
25
85
C
Commercial
Ambient Temperature
0
25
70
C
PDM31564
4
Rev. 1.2 - 3/31/98
PRELIMINARY
Power Supply Characteristics
NOTES: All values are maximum guaranteed values.
-8
-10
-12
-15
-20
Symbol Parameter
Com'l Com'l Com'l
Ind.
Com'l
Ind.
Com'l
Ind.
Unit
I
CC
Operating Current
CE = V
IL
220
210
200
210
190
200
185
195
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
50
45
40
45
35
40
30
35
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
V
CC
0.2V
10
10
10
15
10
15
10
15
mA
f = 0
V
CC
= Max.,
V
IN
V
CC
0.2V or
0.2V
DC Electrical Characteristics
(V
CC
= 3.3V
0.3V)
NOTE: 1. V
IL
(min) = 3.0V for pulse width less than 20 ns.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
LI
Input Leakage Current
V
CC
= Max., V
IN
= Vss to V
CC
Com'l/
Ind.
5
5
A
I
LO
Output Leakage Current
V
CC
= Max.,
CE = V
IH
, V
OUT
= Vss to V
CC
Com'l/
Ind.
5
5
A
V
IL
Input Low Voltage
0.3
(1)
0.8
V
V
IH
Input High Voltage
2.2
Vcc +
0.3
V
V
OL
Output Low Voltage
I
OL
= 8 mA, V
CC
= Min.
--
0.4
V
V
OH
Output High Voltage
I
OH
= 4 mA, V
CC
= Min.
2.4
--
V
PDM31564
Rev. 1.2 - 3/31/98
5
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
+3.3V
317
351
D
OUT
30 pF
Figure 1. Output Load
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE,
t
LZBE
, t
HZBE
, t
LZOE
, t
HZOE
)
+3.3V
317
351
D
OUT
5 pF
AC Test Conditions
Input pulse levels
V
SS
to 3.0V
Input rise and fall times
2.5 NS
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
PDM31564
6
Rev. 1.2 - 3/31/98
PRELIMINARY
t
AA
t
RC
UB, LB
OE
CE
ADDRESSES
t
OH
t
AOE
t
BA
D
OUT
Output Data Valid
t
LZBE(1)
t
LZOE(1)
t
LZCE(1)
t
ACE
t
HZCE(1)
t
HZOE(1)
t
HZBE(1)
Read Timing Diagram
AC Electrical Characteristics
* V
CC
= 3.3V +5%
Description
-8*
-10*
12
15
20
READ Cycle
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
READ cycle time
t
RC
8
10
12
--
15
--
20
--
ns
Address access time
t
AA
8
10
--
12
--
15
--
20
ns
Chip enable access time
t
ACE
8
10
--
12
--
15
--
20
ns
Byte access time
t
BA
5
6
--
7
--
8
--
9
ns
Output hold from address change
t
OH
4
4
4
--
4
--
4
--
ns
Byte disable to output in low-Z
(1)
t
LZBE
0
0
0
--
0
--
0
--
ns
Byte enable to output in high-Z
(1)
t
HZBE
4
5
--
8
--
9
--
9
ns
Chip enable to output in low-Z
(1)
t
LZCE
3
3
4
--
4
--
5
--
ns
Chip disable to output high-Z
(1, 2)
t
HZCE
4
5
--
6
--
7
--
8
ns
Output enable access time
t
AOE
4
5
--
6
--
7
--
10
ns
Output enable to output in low-Z
(1)
t
LZOE
0
0
0
--
0
--
0
--
ns
Output disable to output in high-Z
(1, 2)
t
HZOE
4
5
--
5
--
6
--
6
ns
PDM31564
Rev. 1.2 - 3/31/98
7
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
Write Cycle 1 Timing Diagram
(WE Controlled)
t
AW
tAS
t
WC
UB, LB
CE
WE
ADDRESSES
t
WP
t
LZWE(1)
t
CW
t
BW
High Impedance
t
HZWE(1)
t
AH
t
DH
t
DS
Data Stable
(3)
(4)
D
OUT
D
IN
Write Cycle 2 Timing Diagram
(CE Controlled)
t
AW
tAS
t
WC
UB, LB
CE
WE
ADDRESSES
t
WP
t
CW
High Impedance
t
DH
t
DS
Data Stable
D
OUT
D
IN
t
AH
t
BW
t
LZBE(1)
t
LZCE(1)
t
HZWE(1)
PDM31564
8
Rev. 1.2 - 3/31/98
PRELIMINARY
AC Electrical Characteristics
* V
CC
= 3.3v +5%
Description
-8*
-10*
-12
-15
-20
WRITE Cycle
Sym
Min. Max Min. Max Min. Max. Min. Max. Min. Max. Unit
WRITE cycle time
t
WC
8
--
10
--
12
--
15
--
20
--
ns
Chip enable to end of write
t
CW
7
--
8
--
10
--
11
--
13
--
ns
Address valid to end of write
t
AW
7
--
8
--
10
--
11
--
13
--
ns
Byte pulse width
t
BW
7
--
8
--
10
--
12
--
13
--
ns
Address setup time
t
AS
0
--
0
--
0
--
0
--
0
--
ns
Address hold from end of write
t
AH
0
--
0
--
0
--
0
--
0
--
ns
Write pulse width
t
WP
7
--
8
--
8
--
9
--
10
--
ns
Data setup time
t
DS
5
--
6
--
7
--
8
--
9
--
ns
Data hold time
t
DH
0
--
0
--
0
--
0
--
0
--
ns
Byte disable to output in low Z
(1, 3, 4)
t
LZBE
0
--
0
--
0
--
0
--
0
--
ns
Byte enable to output in high Z
(1, 3, 4)
t
HZBE
--
6
--
6
--
7
--
8
--
9
ns
Output disable to output in low Z
(1, 3, 4)
t
LZOE
0
--
0
--
0
--
0
--
0
--
ns
Output enable to output in high Z
(1, 3, 4)
t
HZOE
--
6
--
6
--
7
--
7
--
8
ns
Write disable to output in low Z
(1,3, 4)
t
LZWE
0
--
0
--
0
--
0
--
0
--
ns
Write enable to output in high Z
(1, 3, 4)
t
HZWE
--
6
6
--
--
7
--
7
--
9
ns
Write Cycle 3 Timing Diagram
(UB, LB Controlled)
t
AW
tAS
t
WC
UB, LB
CE
WE
ADDRESSES
t
WP
t
CW
High Impedance
t
DH
t
DS
Data Stable
D
OUT
D
IN
t
AH
t
BW
t
LZBE(1)
t
LZCE(1)
t
HZWE(1)
PDM31564
Rev. 1.2 - 3/31/98
9
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
Device Type
Power
Speed
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Commercial (0
to +70
C)
Industrial (40
C to +85
C)
8
Commercial Only
10
Commercial Only
12
15
20
SA
Standard Power
Blank
I
A
Automotive ( 40
C to +105
C)
Blank Tubes
TR Tape & Reel
TY Tray
PDM31564 - (256Kx16) Static RAM
XXXXX
X
XX
X
X
X
SO
44-pin 400-mil Plastic SOJ
T
44-pin Plastic TSOP (II)
NOTES:
1. Parameter is determined by device characterization and is not production tested. See Figure 2 for load conditions.
2. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high imped-
ance state.
3. If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high imped-
ance state.
4. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period.
Ordering Information
Faster Memories for a FasterWorld
TM
PDF 
ZIP