Rev 1.0 - 5/01/98
1
1
2
3
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6
7
8
9
10
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12
3.3V 32K x 32 Fast CMOS
Synchronous Static RAM
with Burst Counter
and Output Register
Features
n
Interfaces directly with the x86, PentiumTM, 680X0
and PowerPCTM processors
(100, 80, 66, 60, 50 MHz)
n
Single 3.3V power supply
n
Mode selectable for interleaved or linear burst:
Interleaved for x86 and Pentium
Linear for 680x0 and PowerPC
n
High-speed clock cycle times:
10, 12.5, 15, 16.7 and 20 ns
n
High-density 32K x 32 architecture with burst
address counter and output register
n
Fully registered inputs and outputs for pipelined
operation
n
High-output drive: 30 pF at rated T
A
n
Asynchronous output enable
n
Self-timed write cycle
n
Separate byte write enables and one global write
enable
n
Internal burst read/write address counter
n
Internal registers for address, data, controls
n
Output data register
n
Burst mode selectable
n
Sleep mode
n
Packages:
100-pin QFP - (Q)
100-pin TQFP - (TQ)
Description
The PDM34078 is a 1,048,576 bit synchronous
random access memory organized as 32,768 x 32
bits. This device designed with burst mode
capability and interface controls to provide high-
performance in second level cache designs for x86,
Pentium, 680x0, and PowerPC microprocessors.
Addresses, write data and all control signals except
output enable are controlled through positive edge-
triggered registers. Write cycles are self-timed and
are also initiated by the rising edge of the clock.
Controls are provided to allow burst reads and
writes of up to four words in length. A 2-bit burst
address counter controls the two least-significant
bits of the address during burst reads and writes.
The burst address counter selectively uses the 2-bit
counting scheme required by the x86 and Pentium
or 680x0 and PowerPC microprocessors as con-
trolled by the mode pin. Individual write strobes
provide byte write for the four 8-bit bytes of data.
An asynchronous output enable simplifies interface
to high-speed buses.
PDM34078
TM
i486, Pentium are trademarks of Intel Corp. PowerPC is a trademark of the International Business Machines Corporation.
PDM34078
2
Rev 1.0 - 5/01/98
Functional Block Diagram
OUTPUT
REGISTERS
32K x 32
MEMORY
ARRAY
INPUT
REGISTERS
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
BYTE 4
WRITE DRIVER
BYTE 3
WRITE DRIVER
BYTE 2
WRITE DRIVER
BYTE 1
WRITE DRIVER
BYTE 1
WRITE REGISTER
BYTE 2
WRITE REGISTER
BYTE 3
WRITE REGISTER
BYTE 4
WRITE REGISTER
ENABLE
REGISTER
CLR
Q1
Q0
A14-A0
MODE
ADV
CLK
BW1
BW2
BW3
BW4
BWE
CE
CE2
CE2
OE
GW
ADSP
ADSC
15
8
8
DQ32-DQ1
15
13
15
8
8
8
8
8
32
32
8
A1,A0
A0'
A1'
OUTPUT
BUFFER
PDM34078
Rev 1.0 - 5/01/98
3
1
2
3
4
5
6
7
8
9
10
11
12
NC
DQ16
DQ15
V
CCQ
V
SSQ
DQ14
DQ13
DQ12
DQ11
V
SSQ
V
CCQ
DQ10
DQ9
V
SS
NC
V
CC
ZZ
DQ8
DQ7
V
CCQ
V
SSQ
DQ6
DQ5
DQ4
DQ3
V
SSQ
V
CCQ
DQ2
DQ1
NC
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
V
CC
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
DQ17
DQ18
V
CCQ
V
SSQ
DQ19
DQ20
DQ21
DQ22
V
SSQ
V
CCQ
DQ23
DQ24
FT
V
CC
NC
V
SS
DQ25
DQ26
V
CCQ
V
SSQ
DQ27
DQ28
DQ29
DQ30
V
SSQ
V
CCQ
DQ31
DQ32
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
CC
NC
NC
A10
A11
A12
A13
A14
NC
NC
46 47 48 49 50
PDM34078 Pinout
PDM34078
4
Rev 1.0 - 5/01/98
Pinout
NOTE:
1.MODE and
FT
are DC operated pins. Do not alter input state while device is operating.
Name
I/O
Description
Name
I/O
Description
A14-A2
I
Address Inputs A14-A2
CE
, CE2,
CE2
I
Chip Enables
A1, A0
I
Address Inputs A1 & A0
BWE
I
Byte Write Enable
DQ1-DQ32
I/O
Read/Write Data
BW1
-
BW4
I
Byte Write Enables
NC
--
No Connect
OE
I
Output Enable
MODE
(1)
I
Burst Sequence Select
CLK
I
Clock
ADV
I
Burst Counter Advance
ZZ
I
Sleep Mode
ADSC
I
Controller Address Status
V
CC
--
Power Supply (+3.3V)
ADSP
I
Processor Address Status
V
CCQ
--
Output Power for DQ's (+3.3V
5%)
GW
I
Global Write
V
SS
--
Array Ground
FT
(1)
I
Must be tied HIGH for
proper operation
V
SSQ
--
Output Ground for DQ's
Burst Sequence Table
Burst Sequence
Interleaved
(1)
Mode = NC or
V
CC
Linear
(2)
Mode = V
SS
External Address
A14-A2, A1, A0
A14-A2,0,0
A14-A2,0,1
A14-A2,1,0
A14-A2,1,1
1st Burst Address
A14-A2, A1, A0
A14-A2,0,1
A14-A2,1,0
A14-A2,1,1
A14-A2,0,0
2nd Burst Address
A14-A2, A1, A0
A14-A2,1,0
A14-A2,1,1
A14-A2,0,0
A14-A2,0,1
3rd Burst Address
A14-A2, A1, A0
A14-A2,1,1
A14-A2,0,0
A14-A2,0,1
A14-A2,1,0
Asynchronous Truth Table
NOTE: 1. L = Low, H = High, X = Don't Care.
2. For a write operation following a read operation,
OE must be high before the input data required
setup time and held high through the input data
hold time.
3. This device contains circuitry that will ensure
the outputs will be in high-Z during powerup.
Operation
ZZ
OE I/O
Status
Read
L
L
Data Out
Read
L
H
High-Z
Write
L
X
High-Z: Write Data In
Deselected
L
X
High-Z
Sleep
H
X
High-Z
Partial Truth Table for Writes
NOTE: 1. L = Low, H = High, X = Don't Care.
2. Using BWE and BW1 through BW4, any one or
more bytes may be written.
GW
BWE
BW1
BW2
BW3
BW4
Function
H
H
X
X
X
X
READ
H
L
H
H
H
H
READ
H
L
L
H
H
H
WRITE Byte 1
H
L
L
L
L
L
WRITE All Bytes
L
X
X
X
X
X
WRITE All Bytes
Note:
1. Interleaved = x86 and Pentium.
2. Linear = 680x0 and Power PC compatible.
PDM34078
Rev 1.0 - 5/01/98
5
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3
4
5
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8
9
10
11
12
Synchronous Truth Table
(See Notes 1 through 3)
NOTES:
1.
X = Don't Care, H = logic High, L = logic Low, BWx = any one or more byte write enable signals (BW1, BW2, BW3, BW4)
and BWE are low, or GW is low.
2. BW1 enables BWx to Byte 1 (DQ1-DQ8). BW2 enables BWx to Byte 2 (DQ9-DQ16).
BW3 enables BWx to Byte 3 (DQ17-DQ24), BW4 enables BWx to Byte 4 (DQ25-DQ32).
3. ADV must always be high at the rising edge of the first clock after an ADSP cycle is initiated if a write cycle is desired (to
ensure use of correct address).
CE
CE2
CE2
ADSP
ADSC
ADV
BWx
CLK Address
Operation
H
X
X
X
L
X
X
N/A
Deselected
L
X
L
L
X
X
X
N/A
Deselected
L
H
X
L
X
X
X
N/A
Deselected
L
X
L
H
L
X
X
N/A
Deselected
L
H
X
H
L
X
X
N/A
Deselected
L
L
H
L
X
X
X
External
Read Cycle, Begin Burst
L
L
H
H
L
X
X
External
Read Cycle, Begin Burst
X
X
X
H
H
L
H
Next
Read Cycle, Continue Burst
H
X
X
X
H
L
H
Next
Read Cycle, Continue Burst
X
X
X
H
H
H
H
Current
Read Cycle, Suspend Burst
H
X
X
X
H
H
H
Current
Read Cycle, Suspend Burst
L
L
H
H
L
X
L
External
Write Cycle, Begin Burst
X
X
X
H
H
L
L
Next
Write Cycle, Continue Burst
H
X
X
X
H
L
L
Next
Write Cycle, Continue Burst
X
X
X
H
H
H
L
Current
Write Cycle, Suspend Burst
H
X
X
H
H
H
L
Current
Write Cycle, Suspend Burst
PDM34078
6
Rev 1.0 - 5/01/98
Burst Mode Operation
This is a synchronous part. All activities are initiated by the positive, low-to-high edge of the clock (CLK). This part can
perform burst reads and writes with burst lengths of up to four words. The four-word burst is created by using a burst
counter to drive the two least-significant bits of the internal RAM address. The burst counter is loaded at the start of the
burst and is incremented for each word of the burst. The sequence is given in the Burst Sequence Table.
Burst transfers are initiated by the ADSC or ADSP signals. When the ADSP and CE signals are sampled low, a read cycle
is started (independent of BW1, BW2, BW3, or BW4; BWE, GW and ADSC), and prior burst activity is terminated. ADSP
is gated by CE, so both must be active for ADSP to load the address register and to initiate a read cycle. The address and
the chip enable input (CE) are sampled by the same edge that samples ADSP. Read data is valid at the output after the
specified delay from the clock edge.
When ADSC is sampled low and ADSP is sampled high, a read or write cycle is started depending on the state of BW1,
BW2, BW3 or BW4; BWE, and GW. If BW1, BW2, BW3, BW4, BWE, and GW are all sampled high, a read cycle is started,
as described above. If BW1, BW2, BW3, or BW4; BWE, and GW is sampled low, a write cycle is begun. The address,
write data, and the chip enable inputs (CE, CE2 and CE2) are sampled by the same edge that samples ADSC and BW1
BW4, BWE and GW. The ADV line is held high for this clock edge to maintain the correct address for the internal write
operation which will follow this second clock edge.
After the first cycle of the write burst, the state of BW1BW4, BWE and GW determines whether the next cycle is a read
or write cycle, and ADV controls the advance of the address counter. The ADV signal advances the address counter.
This increments the address to the next available RAM address. You write the next word in the burst by taking ADV low
and presenting the write data at the positive edge of the clock. If ADV is sampled low, the burst counter advances and
the write data (which is sampled by the same clock) is written into the internal RAM during the time following the clock
edge.
Absolute Maximum Ratings
(1)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXI-
MUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all
cases and specifically for those where the chosen package
has a large thermal resistance (e.g., TSOP). The calculation
should be of the form
: T
j
= T
a
+ P *
ja
where T
a
is the ambient
temperature, P is average operating power and
ja
the ther-
mal resistance of the package. For this product, use the
following
ja
values:
TQFP: 50
o
C/W
QFP: 50
o
C/W
Symbol
Rating
Com'l.
Ind.
Unit
V
TERM
Terminal Voltage with Respect to V
SS
0.5 to +4.6
0.5 to +4.6
V
T
BIAS
Temperature Under Bias
55 to +125
65 to +135
C
T
STG
Storage Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
1.0
1.0
W
I
OUT
DC Output Current
50
50
mA
T
j
Maximum Junction Temperature
(2)
125
125
C
PDM34078
Rev 1.0 - 5/01/98
7
1
2
3
4
5
6
7
8
9
10
11
12
DC Electrical Characteristics
(V
CC
= 3.3V
0.3V, All Temperature Ranges)
NOTES:
1. Undershoots to 2.0 for 10 ns are allowed once per cycle.
2. MODE, FT and ZZ pins have an internal pullup and exhibit an input leakage current of
400
A.
Power Supply Characteristics
Symbol
Description
Test Conditions
Min.
Max.
Unit
|I
LI
|
Input Leakage Current
V
IN
= 0V to V
CC
2
2
A
|I
LO
|
Output Leakage Current
Outputs Disabled, V
I/O
= 0V to V
CC
2
2
A
V
OL
Output Low Voltage
V
CC
= Min., I
OL
= 8 mA
--
0.4
V
V
OH
Output High Voltage
V
CC
= Min., I
OH
= 5 mA
2.4
--
V
V
IH
Input HIGH Voltage
2.0
Vcc+0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
Symbol
Description
Test Conditions
-6 ns
-7 ns
-8 ns
-10 ns
-12 ns
Unit
I
CC
Active Supply Current
Device Deselected
V
IN
V
IL
or
V
IH,
I
I/O
= 0
350
300
250
230
210
mA
I
SB
Standby Current:
Device Deselected
V
IN
V
IL
or
V
IH,
0 MHz
All inputs static
20
20
20
20
20
mA
I
SB1
Standby Current:
Device Deselected
V
IN
0.2V or
V
CC
0.2V
All inputs static, 0 MHz
3
3
3
3
3
mA
I
SB2
Standby Current:
Device Deselected
V
IN
V
IL
or
V
IH,
All inputs static
60
55
50
45
40
mA
I
SB3
Sleep Mode
Standby Current:
Device Deselected
ZZ
V
CCQ
0.2V
3
3
3
3
3
mA
Recommended DC Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
V
CCQ
Supply voltage
3.0
3.3
3.6
V
V
SS
Supply Voltage
0
0
0
V
Commercial
Ambient Temperature
0
25
70
C
PDM34078
8
Rev 1.0 - 5/01/98
Capacitance
(T
A
= +25
C, f = 1.0 MHz)
NOTES: 1. Characterized values, not currently tested.
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
pF
AC Test Conditions
Input pulse levels
V
SS
to 3.0V
Input rise and fall times
1.5 ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
50
Z
OUT
= 50
V
L
= 1.5V
I/O
30 pF
351
317
5 pF*
+3.3V
DATA
OUT
Figure 1. Output Load
Figure 2. Output Load
t
CQ
, t
OLZ
, t
OHZ
, t
CZ
PDM34078
Rev 1.0 - 5/01/98
9
1
2
3
4
5
6
7
8
9
10
11
12
AC Electrical Characteristics
Parameter
Symbol
-6 ns
-7 ns
-8 ns
-10 ns
-12 ns
Type
Units
Cycle time
t
CYC
10
12.5
15
16.7
20
Min.
ns
Clock access time (0 pF load)
t
CQ0
5
6
7
9
11
Max.
ns
Clock to output valid (Std. load)
t
CQ
6
7
8
10
12
Max.
ns
Clock to output invalid
t
CQX
2
2
2
2
2
Min.
ns
Clock to output high-Z
t
CHZ
2
2
2
2
2
Min.
ns
10
12.5
15
16.7
20
Max.
Clock pulse width high
t
CH
4
5
5
6
6
Min.
ns
Clock pulse width low
t
CL
4
5
5
6
6
Min.
ns
OE to output valid
t
OE
5
5
5
6
6
Min.
ns
OE to output low-Z
t
OLZ
0
0
0
0
0
Min.
ns
OE to output high-Z
t
OHZ
5
5
5
6
6
Max.
ns
ZZ standby time
t
ZZS
100
100
100
100
100
Max.
ns
ZZ recovery time
t
ZZREC
100
100
100
100
100
Min.
ns
SETUP TIMES
Address t
AS
2.5
2.5
2.5
2.5
3
Min.
ns
Address status (ADSC, ADSP)
t
AAS
2.5
2.5
2.5
2.5
3
Min.
ns
Address advance setup (ADV)
t
AAS
2.5
2.5
2.5
2.5
3
Min.
ns
Write signals (BWx, GW)
t
WS
2.5
2.5
2.5
2.5
3
Min.
ns
Data in
t
DS
2.5
2.5
2.5
2.5
3
Min.
ns
Chip enables (CE, CE2, CE2)
t
CES
2.5
2.5
2.5
2.5
3
Min.
ns
HOLD TIMES
Address t
AH
0.5
0.5
0.5
0.5
0.5
Min.
ns
Address status (ADSC, DSP)
t
ADSH
0.5
0.5
0.5
0.5
0.5
Min.
ns
Address advance (ADV)
t
AAH
0.5
0.5
0.5
0.5
0.5
Min.
ns
Write eignals (BWx, GW)
t
WH
0.5
0.5
0.5
0.5
0.5
Min.
ns
Data in
t
DH
0.5
0.5
0.5
0.5
0.5
Min.
ns
Chip enables (CE, CE2, CE2)
t
CEH
0.5
0.5
0.5
0.5
0.5
Min.
ns
PDM34078
10
Rev 1.0 - 5/01/98
Read Timing Diagram
NOTES: 1. Qn(A2) refers to output from address A2. Q14 refers to outputs according to burst sequence.
2. CE2 and CE2 have timing identical to CE. In this diagram, when CE is low, CE2 is low and CE2 is high. When CE is high,
CE2 is high and CE2 is low.
CLK
tCH
tCYC
tCL
ADSP
tADSS
tADSH
ADSC
ADV
tAS
tAH
tAAS
tAAH
tWS
tWH
ADDRESS
GW
,
BWE
BW4
-
BW1
tCES
tCEH
tCZ
tOE
tOLZ
tCQX
tCQ
tOHZ
CE
OE
DATA
OUT
tCZ
A2
A1
Q1
A1
Q1
A2
Q2
A2
Q3
A3
Q3
A2
Q4
A2
Q2
A2
A3
PDM34078
Rev 1.0 - 5/01/98
11
1
2
3
4
5
6
7
8
9
10
11
12
Write Timing Diagram
NOTES: 1. CE2 and CE2 have timing identical to CE. On this diagram, when CE is low, CE2 is low and CE2 is high. When CE is
high, CE2 is high and CE2 is low.
2. Full width write can be initiated by GW low or GW high and BWE, BW1-BW4 low.
3
BWE is low when any one or more byte write enables (BW1-BW4) are low in this diagram.
CLK
tCH
tCYC
tCL
ADSP
tADSS
tADSH
ADSC
ADV
tAS
tAH
tAAS
tAAH
tWH
ADDRESS
BWE
(3)
BW4
-
BW1
GW
(2)
tCES
tCEH
tOHZ
CE
OE
DATA
IN
DATA
OUT
tWS
tWS
tWH
tDH
tDS
A1
A2
A3
D1
A1
D1
A2
D2
A2
D2
A2
D3
A2
D4
A2
D1
A3
D2
A3
D3
A3
D1
A1
PDM34078
12
Rev 1.0 - 5/01/98
Read/Write Timing Diagram
NOTES: 1. CE2 and CE2 have timing identical to CE. On this diagram, when CE is low, CE2 is low and CE2 is high. When CE is
high, CE2 is high and CE2 is low.
2. GW is high.
CLK
tCH
tCYC
tCL
ADSP
tADSS
tADSH
ADSC
ADV
tAS
tAH
ADDRESS
BWE
BW4
-
BW1
tCES
tCEH
CE
OE
DATA
IN
DATA
OUT
tDS
tCQX
tOHZ
tCQ
tDH
A1
A2
A3
D1
A2
Q1
A2
Q1
A1
Q2
A2
Q3
A3
tOLZ
PDM34078
Rev 1.0 - 5/01/98
13
1
2
3
4
5
6
7
8
9
10
11
12
Sleep Mode Timing Diagram
NOTES: 1. Data retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 100 ns after leaving ZZ state.
CLK
SNOOZE
ADSP
ADSC
ZZ
tZZS
tZZREC
Sequential Non-burst Read and Write Timing Diagram
NOTES:
1. ADSP = high, ADSC = low, ADV = high, CE1 = low.
2. H
V
IH
, L
V
IL
.
CLK
ADSP
ADSC
ADV
ADDR
CE1
OE
WE
DQ
A
B
C
READS
WRITES
Q(A)
Q(B)
Q(C)
Q(D)
E
F
G
D
H
Q(E)
Q(F)
Q(G)
Q(H)
PDM34078
14
Rev 1.0 - 5/01/98
Ordering Information
Device Type
Power
Speed
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Commercial (0
to +70
C)
Industrial (40
C to +85
C)
6
Commercial Only
7
Commercial Only
8
10
12
SA /S Standard Power
Blank
I
A
Automotive ( 40
C to +105
C)
Blank Tubes
TR Tape & Reel
TY Tray
PDM34078 - (32Kx32) Sync. Static RAM
XXXXX
X
XX
X
X
X
Q
100-pin QFP
TQ
100-pin TQFP
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