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Электронный компонент: PDM41028LA-10

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Rev. 2.2 - 4/29/98
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Features
n
High speed access times
Com'l: 10, 12 and 15 ns
Ind'l: 12 and 15 ns
n
Low power operation (typical)
- PDM41028SA
Active: 400 mW
Standby: 150 mW
- PDM41028LA
Active: 350 mW
Standby: 100 mW
n
Single +5V (
10%) power supply
n
TTL-compatible inputs and outputs
n
Packages
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
Description
The PDM41028 is a high-performance CMOS static
RAM organized as 262,144 x 4 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
The PDM41028 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41028 comes in two versions,
the standard power version PDM41028SA and a low
power version the PDM41028LA. The two versions
are functionally the same and only differ in their
power consumption.
The PDM41028 is available in a 28-pin 300-mil SOJ,
and a 28-pin 400-mil SOJ for surface mount
applications.
A




A
0
17
I/O
I/O
I/O
I/O
0
1
2
3
CE
Addresses
Decoder
Memory
Matrix
Input
Data
Control
Column I/O
OE
WE
Functional Block Diagram
PDM41028
1 Megabit Static RAM
256K x 4-Bit
PDM41028
2
Rev. 2.2 - 4/29/98
Absolute Maximum Ratings
(1)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-
culation should be of the form
: T
j
= T
a
+ P *
ja
where T
a
is the ambient temperature, P
is average operating power and
ja
the thermal resistance of the package. For this
product, use the following
ja
values:
SOJ: 76
o
C/W
TSOP: 100
o
C/W
Symbol
Rating
Com'l.
Ind.
Unit
V
TERM
Terminal Voltage with Respect to V
SS
0.5 to +7.0
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
55 to +125
65 to +135
C
T
STG
Storage Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
1.0
1.0
W
I
OUT
DC Output Current
50
50
mA
T
j
Maximum Junction Temperature
(2)
125
145
C
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
21
22
23
24
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE
OE
Vss
Vcc
A6
A5
A4
A3
A2
A1
A0
NC
I/O3
I/O2
I/O1
I/O0
WE
13
14
25
26
27
28
Pin Description
Name
Description
A17-A0
Address Inputs
I/O3-I/O0
Data Inputs/Outputs
OE
Output Enable Input
WE
Write Enable Input
CE
Chip Enable Input
NC
No Connect
V
CC
Power (+5V)
V
SS
Ground
Truth Table
(1)
NOTE: 1. H = V
IH
, L = V
IL
, X = DON'T CARE
OE
WE
CE
I/O
MODE
X
X
H
Hi-Z
Standby
L
H
L
D
OUT
Read
X
L
L
D
IN
Write
H
H
L
Hi-Z
Output Disable
SOJ
PDM41028
Rev. 2.2 - 4/29/98
3
1
2
3
4
5
6
7
8
9
10
11
12
Recommended DC Operating Conditions
DC Electrical Characteristics
(V
CC
= 5.0V
10%)
NOTE:
1. V
IL
(min) = 3.0V for pulse width less than 20 ns
Power Supply Characteristics
SHADED AREA = PRELIMINARY DATA
NOTES: All values are maximum guaranteed values.
V
LC
0.2V, V
HC
V
CC
0.2V
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
V
SS
Supply Voltage
0
0
0
V
Industrial
Ambient Temperature
40
25
85
C
Commercial
Ambient Temperature
0
25
70
C
PDM41028SA
PDM41028LA
Unit
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
I
LI
Input Leakage Current
V
CC
= MAX., V
IN
= V
SS
to V
CC
Com'l/
Ind.
5
5
5
5
A
I
LO
Output Leakage Current
V
CC
= MAX.,
CE = V
IH
, V
OUT
= V
SS
to V
CC
Com'l/
Ind.
5
5
5
5
A
V
IL
Input Low Voltage
0.5
(1)
0.8
0.5
(1)
0.8
V
V
IH
Input High Voltage
2.2
6.0
2.2
6.0
V
V
OL
Output Low Voltage
I
OL
= 8 mA, V
CC
= Min.
I
OL
= 10 mA, V
CC
= Min.
--
--
0.4
0.5
--
--
0.4
0.5
V
V
V
OH
Output High Voltage
I
OH
= 4 mA, V
CC
= Min.
2.4
--
2.4
--
V
-10
-12
-15
Symbol Parameter
Power Com'l. Com'l
Ind.
Com'l
Ind.
Unit
I
CC
Operating Current
CE = V
IL
,
SA
250
230
240
185
195
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
LA
230
210
220
165
175
mA
I
SB
Standby Current
CE = V
IH
SA
80
70
70
55
55
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
LA
75
65
65
50
50
mA
I
SB1
Full Standby Current
CE
V
HC
SA
20
15
25
10
15
mA
f = 0
V
CC
= Max.,
V
IN
V
CC
0.2V or
0.2V
LA
10
10
10
5
10
mA
PDM41028
4
Rev. 2.2 - 4/29/98
Capacitance
(1)
(T
A
= +25
C, f = 1.0 MHz)
NOTE:1. This parameter is determined by device characterization but is not production tested.
AC Test Conditions
Symbol
Parameter
Max.
Unit
C
IN
Input Capacitance
8
pF
C
OUT
Output Capacitance
8
pF
Input pulse levels
V
SS
to 3.0V
Input rise and fall times
3 ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
,
t
HZOE
)
+5V
480
255
D
OUT
5 pf
+5V
480
255
D
OUT
30 pF
Figure 4.
5
4
3
2
1
0
0
30
60
90
120
Typical Delta tAA vs Capacitive Loading
Additional Lumped Capacitive Loading (pF)
Delta t
AA
- ns
PDM41028
Rev. 2.2 - 4/29/98
5
1
2
3
4
5
6
7
8
9
10
11
12
Read Cycle No. 1
(4, 5)
Read Cycle No. 2
(2, 4, 6)
AC Electrical Characteristics
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table.
Description
-10
(7)
-12
(7)
-15
READ Cycle
Sym
Min. Max. Min. Max. Min. Max. Units
READ cycle time
t
RC
10
12
15
ns
Address access time
t
AA
10
12
15
ns
Chip enable access time
t
ACE
10
12
15
ns
Output hold from address change
t
OH
3
3
3
ns
Chip enable to output in low Z
(1,3)
t
LZCE
5
5
5
ns
Chip disable to output in high Z
(1,2,3)
t
HZCE
6
6
7
ns
Chip enable to power up time
(3)
t
PU
0
0
0
ns
Chip disable to power down time
(3)
t
PD
10
12
15
ns
Output enable access time
t
AOE
6
6
6
ns
Output enable to output in low Z
(1,3)
t
LZOE
0
0
0
ns
Output disable to output in high Z
(1,3)
t
HZOE
6
6
6
ns
t
RC
t
AA
t
OH
PREVIOUS DATA VALID
DOUT
ADDR
DATA VALID
t
RC
t
ACE
t
AA
t
LZCE
t
HZCE
t
LZOE
t
HZOE
t
AOE
ADDR
CE
OE
D
OUT
DATA VALID
PDM41028
6
Rev. 2.2 - 4/29/98
Write Cycle No. 1 (Write Enable Controlled)
Write Cycle No. 2 (Write Enable Controlled)
Write Cycle No. 3 (Chip Enable Controlled)
t
WC
t
AW
t
CW
t
WP2
t
AS
t
AH
t
DS
t
DH
t
LZWE
t
HZWE
ADDR
CE
WE
D
OUT
HIGH-Z
HIGH-Z
D
IN
DATA VALID
NOTE: Output Enable (OE) is inactive (high)
t
WC
t
AW
t
WP1
t
CW
t
AH
t
AS
t
DH
t
DS
ADDR
CE
WE
D
OUT
HIGH-Z
D
IN
DATA VALID
t
WC
t
AW
t
AS
t
WP1
t
CW
t
DS
t
DH
t
AH
ADDR
CE
WE
D
OUT
HIGH-Z
D
IN
DATA VALID
PDM41028
Rev. 2.2 - 4/29/98
7
1
2
3
4
5
6
7
8
9
10
11
12
AC Electrical Characteristics
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table
Low V
CC
Data Retention Waveform
Data Retention Electrical Characteristics (LA Version Only)
NOTES: (For three previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured
200 mV from steady state voltage.
2. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
.
3. This parameter is sampled.
4. WE is high for a READ cycle.
5. The device is continuously selected. Chip Enable is held in its active state.
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
7. Vcc = 5V
5%.
Description
-10
(7)
-12
(7)
-15
WRITE Cycle
Sym
Min.
Max.
Min.
Max.
Min.
Max.
Units
WRITE Cycle time
t
WC
10
12
15
ns
Chip enable active time
t
CW
10
10
11
ns
Address Valid to end of write
t
AW
10
10
11
ns
Address setup time
t
AS
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
ns
Write pulse width
t
WP1
9
10
11
ns
Write pulse width
t
WP2
10
11
12
ns
Data setup time
t
DS
7
7
7
ns
Data hold time
t
DH
0
0
0
ns
Write disable to output in low Z
(1,3)
t
LZWE
0
0
0
ns
Write enable to output in high Z
(1,3)
t
HZWE
7
7
7
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DR
VCC for Retention Data
2
--
--
V
I
CCDR
Data Retention Current
CE
V
CC
0.2V
V
IN
V
CC
0.2V
or
0.2V
V
CC
= 2V
--
--
500
A
V
CC
= 3V
--
--
750
A
t
CDR
Chip Deselect to Data Retention Time
0
--
--
ns
t
R
(3)
Operation Recovery Time
t
RC
--
--
ns
DON'T CARE
VCC
V
V
IH
IL
t
CDR
V
t
R
4.5V
4.5V
Data Retention Mode
CE
DR
VDR
PDM41028
8
Rev. 2.2 - 4/29/98
Ordering Information
Device Type
Power
Speed
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Commercial (0
to +70
C)
Industrial (40
C to +85
C)
10
12
15
SA
Standard Power
LA
Low Power
Blank
I
A
Automotive ( 40
C to +105
C)
Blank Tubes
TR Tape & Reel
TY Tray
PDM41028 - (256Kx4) Static RAM
XXXXX
X
XX
X
X
X
TSO 28-pin 300-mil Plastic SOJ
SO
28-pin
400-mil Plastic SOJ
Commercial Only
(Use 15ns for slower designs.)
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