Kentron Technologies, Inc.
155 West Street
Wilmington, MA 01887
Phone: (978) 988-9100
Fax (978) 988-5550
www.kentrontech.com
16M X 72 LOW PROFILE REGISTERED SDRAM DIMM
SDRAM MODULE
128 MByte (16M x 72) SDRAM Low Profile
Registered 168 Pin DIMM
General Description:
This memory module is a high performance 128 Megabyte Registered synchronous dynamic
RAM module organized in one Bank as 16M x 72 in a 168 pin Low Dual In-Line Memory Module
(DIMM) package. The module utilizes eighteen (18) 4Mx4X4 SDRAM (64ms Refresh) devices
in a TSOP II 400 mil package. A 256 Byte Serial EEPROM contains the module configuration
information. The EEPROM can be configured to Jedec specifications.
These modules offer substantial advances in DRAM operating performance, including the ability
to synchronously burst data at a high rate with automatic column-address generation, interleave
between internal banks in order to hide precharge time, and the capability to randomly change
column address on each clock cycle during burst.
Features:
High density: 128 MB (16M x 72)
Cycle time: 7.5ns (133 MHz)
10ns (100 MHz)
JEDEC Standard 168 Pin Registered SDRAM DIMM
PC-100/133 Compliant
Single power supply of 3.3V 10%
Serial Presence Detect
LVTTL Compatible I/O and Clock
Registered Control & Address Lines
On-board PLL Clock Driver
Refresh Rate 15.6usec
Auto Precharge and Auto Refresh Modes handled by SDRAM Devices
Programmable Burst Type, Burst Length and CAS Latency of SDRAM devices
Internal Pipeline Operation
Fully Synchronous all signals registered on positive edge of system clock
Package Height: 1.20 inches
Kentron Technologies, Inc. (978) 988-9100 Page 2
Rev. 1.0 (6/00)
16M X 72 LOW PROFILE REGISTERED SDRAM DIMM
Operating Features:
The SDRAM DIMM utilizes a clock input for the synchronization. Each operation of the SDRAM
is determined by commands and all operations are referenced to a positive clock edge. CAS
Latency defines the delay from when a Read Command is registered on a rising clock edge to
when the data from the Read Command becomes available at the outputs. The CAS latency is
expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock cycles.
The burst mode is a very high-speed access mode utilizing an internal column address
generator. Once a column address for the first access is set, following addresses are
automatically generated by the internal column address counter.
All control and address signals are registered on-board and hence delayed by one cycle in
arriving at the SDRAMs. The clock signal is distributed to all SDRAMs via a zero delay PLL
driver. Note that the PLL must be given enough clock cycles to stabilize before any operation
can be given (minimum stabilization time equal to 1 ms).
Absolute Maximum Ratings*:
Item
Symbol
Rating
Unit
Supply voltage (V
CC
Relative to V
SS
)
V
CC
-1.0 to +4.6
V
Input/Output Voltage
V
I/O
-1.0 to +4.6
V
Operating temperature
T
opr
0 to +70
C
Storage temperature
T
stg
-55 to +125
C
Short circuit output current
I
out
50
mA
* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions:
(Voltage referenced to V
CC
. T
A
= 0 to 70 C)
Item
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
V
CC
3.0
3.3
3.6
V
Input high voltage
V
IH
2.0
-
V
CC
+0.3
V
Input low voltage
V
IL
-0.3
-
0.8
V
Operating Temperature
T
A
0
+25
+70
C
Kentron Technologies, Inc. (978) 988-9100 Page 3
Rev. 1.0 (6/00)
16M X 72 LOW PROFILE REGISTERED SDRAM DIMM
Capacitance:
(TA=25C, Vcc=3.3V0.3V)
Parameter
1
Symbol
Typ.
Unit
Input capacitance (Address/ WE, CKE0, /CAS)
C
IN
5.5
pF
Input capacitance (/DQMBs, /CS0~/CS3)
C
IN
5.5
pF
Input capacitance (CK0)
2
C
IN
3.5
pF
Input capacitance (/RAS)
C
IN
5.5
pF
Input/Output capacitance (DQ0~DQ63, CB0~CB7)
3
C
I/O
5.0
pF
DC Characteristics:
(V
CC
= 3.3V.3V, V
SS
=0V, T
A
=0 to + 70C)
Parameter
4
Symbol
133MHz
Max.
100MHz
Max.
Unit
Operating current
(No Burst, T
CK
=min. T
RC
=min.)
I
CC1
2500
2450
mA
Precharge Standby Current
(CKE=V
IL
, T
CK
= min. Bank idle)
(CKE=V
IH
, T
CK
= min. Bank idle)
I
CC2
38
546
38
546
mA
Active Standby Current
(CKE=V
IL
, T
CK
= min. )
(CKE=V
IH
, T
CK
= min. )
I
CC3
36
360
36
360
mA
Burst Mode Current (t
CK
=min.)
I
CC4
2460
2360
mA
Refresh Current (per DIMM)
(t
CK
=min., t
RC
=min., t
RRD
=min., Auto Refresh)
I
CC5
3700
3700
mA
Self Refresh Current (CKE=V
IL
)
I
CC6
36
36
mA
Pin Names:
CK0-CK3
Clock Inputs
DQ0-DQ63
Data Inputs/Outputs
CKE0
Clock Enables
CB0-CB7
ECC Data Input/Output
/RAS
Row Address Strobe
DQMB0-DQMB7
Data Mask Enables
/CAS
Column Address Strobe
V
CC
Power supply
/WE
Write Enable
V
SS
Ground
/CS0-/CS3
Chip Select
SCL
Serial Clock
A0-A11
Address Inputs
SDA
Serial Data Input/Output
BA0, BA1
SDRAM Bank Select
SA0-SA2
Decode Input
REGE
Register Enable
WP
Write Protect for SPD
NC or DU
No Connect
REGE is the Register Enable pin which permits the DIMM to operate in buffered mode (inputs re-driven asynchronously) and "registered" mode (signals
re-driven to SDRAMs when clock rises, and held valid until next rising clock). To conform to this specification, motherboards must pull this pin to a high
state ("registered mode").
1
Based on Pericom ALVC16334 Register unless otherwise stated
2
Pericom PI6C2510-133 PLL
3
Capacitance varies with by DRAM vendor
4
Typical Actual values run lower than Max Spec'ed Values.
Kentron Technologies, Inc. (978) 988-9100 Page 4
Rev. 1.0 (6/00)
16M X 72 LOW PROFILE REGISTERED SDRAM DIMM
SDRAM DIMM Pinout:
No.
Designation
No.
Designation
No.
Designation
No.
Designation
1
V
SS
43
V
SS
85
Vss
127
Vss
2
DQ0
44
DU
86
DQ32
128
CKE0
3
DQ1
45
CS2
87
DQ33
129
CS3*
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
V
CC
48
DU
90
Vcc
132
A13
7
DQ4
49
V
CC
91
DQ36
133
Vcc
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
V
SS
54
Vss
96
Vss
138
Vss
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
Vcc
101
DQ45
143
Vcc
18
V
CC
60
DQ20
102
Vcc
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
CKE1
105
CB4
147
REGE
22
CB1
64
Vss
106
CB5
148
Vss
23
V
SS
65
DQ21
107
Vss
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
V
CC
68
Vss
110
Vcc
152
Vss
27
WE*
69
DQ24
111
CAS*
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
S0*
72
DQ27
114
CS1*
156
DQ59
31
DU
73
Vcc
115
RAS*
157
Vcc
32
V
SS
74
DQ28
116
Vss
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
Vss
120
A7
162
Vss
37
A8
79
CK2
121
A9
163
CK3
38
A10/AP
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
V
CC
82
SDA
124
Vcc
166
SA1
41
V
CC
83
SCL
125
CK1
167
SA2
42
CK0
84
Vcc
126
A12
168
Vcc
Kentron Technologies, Inc. (978) 988-9100 Page 5
Rev. 1.0 (6/00)
16M X 72 LOW PROFILE REGISTERED SDRAM DIMM
AC Electrical Characteristics:
(TA=0C to +70C, V
CC
=3.3V0.3V, V
SS
=0V)
Parameter
Symbol 133MHz
Min.
133MHz
Max.
100MHz
Min.
100MHz
Max.
Unit
Row to row active delay
t
RRD
15
20
ns
RAS to CAS delay
t
RCD
20
20
ns
Row precharge time
t
RP
20
20
ns
Row active time
t
RAS
45
120K
50
120K
ns
Row cycle time
t
RC
67.5
70
ns
Last data in to row precharge
t
RDL
8
10
ns
Last data in to new Col. Address delay
t
CDL
1
1
clk
Last data in to burst stop
t
BDL
1
1
clk
Column address to column address
delay
t
CCD
1
1
clk
Number of valid output data
(CL=3)
(CL=2)
2
-
2
1
Ea
Clock Cycle Time
(CL=3)
(CL=2)
t
CC
7.5
-
10
10
5
ns
Clock to Valid Output Delay
(CL=3)
(CL=2)
t
AC
5.4
-
6
6
ns
Output Data Hold Time
(CL=3)
(CL=2)
t
OH
2.7
-
3
3
ns
Clock High Pulse Width
t
CH
2.5
3
ns
Clock Low Pulse Width
t
CL
2.5
3
ns
Input Setup Time
t
SI
1.5
2
ns
Input Hold Time
t
SH
0.8
1
ns
Clock to Output in Low-Z
T
SLZ
1
1
ns
Clock to Output in High-Z
t
SHZ
5.4
6
ns
5
Available for select SDRAM devices/part numbers.
PDF 
ZIP