King Billion Electronics Co., Ltd
HE84G770
HE80004H SERIES
October 31, 2003
1
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
- Table of Contents -
1.
General Description ___________________________________________________________________3
2.
Features _____________________________________________________________________________3
3.
Functional Block Diagram______________________________________________________________4
4.
Pin Description _______________________________________________________________________4
5.
ROM Map Configurations______________________________________________________________7
6.
External RAM/Flash Memory__________________________________________________________10
7.
LCD Display RAM Map ______________________________________________________________11
8.
LCD driver configurations_____________________________________________________________12
8.1.
16 Gray Scale LCD Display RAM Map ________________________________________________13
8.2.
4 Gray Scale LCD Display RAM Map _________________________________________________19
8.3.
Black and White LCD Display RAM Map______________________________________________22
9.
LCD Power Supply___________________________________________________________________25
10.
Oscillators ________________________________________________________________________28
11.
General Purpose I/O _______________________________________________________________29
12.
Key Scan Circuit___________________________________________________________________31
13.
Timer1 ___________________________________________________________________________33
14.
Timer2 ___________________________________________________________________________34
15.
Time Base ________________________________________________________________________35
16.
Watch Dog Timer __________________________________________________________________35
17.
Voice Output ______________________________________________________________________37
18.
Low Voltage Detection/Reset _________________________________________________________42
19.
Infrared output____________________________________________________________________43
20.
Universal Asynchronous Receiver/Transmitter__________________________________________44
20.1.
Interface Registers _________________________________________________________________45
20.2.
Baud Rate Configuration Register ____________________________________________________45
20.3.
Interrupt Enable, Identification Register ______________________________________________46
20.4.
Line Control Register_______________________________________________________________47
King Billion Electronics Co., Ltd
HE84G770
HE80004H SERIES
October 31, 2003
2
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
20.5.
Line Status Register ________________________________________________________________48
21.
Extension Register Access ___________________________________________________________49
22.
Summary of Registers and Mask Options ______________________________________________49
23.
Absolute Maximum Rating __________________________________________________________53
24.
Recommended Operating Conditions _________________________________________________53
25.
AC/DC Characteristics _____________________________________________________________53
26.
Application Circuit_________________________________________________________________55
27.
Important Note ____________________________________________________________________57
28.
Updated History ___________________________________________________________________57
King Billion Electronics Co., Ltd
HE84G770
HE80004H SERIES
October 31, 2003
3
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
1. General Description
HE84G770 is a member of 8-bit Micro-controller series developed by King Billion Electronics. External
address and data buses are provided to access external memory. This chip has 6400 pixel, 16 gray-scale
LCD driver built-in with 4 different configurations, and up to 36-bit general purpose I/O ports. The
built-in OP comparator can be used with light, voice, temperature and humility sensor or used to detect
the battery low. The 8-bit current-type D/A converter and PWM driver output provides the complete
speech output solutions. The 1M bytes ROM and 6K bytes RAM can be used for the storage of large
speech data, image and text, etc. An UART is included to provide the serial communication capability. IR
output makes it suitable for remote control applications.
The instruction sets of HE80004H series is easy to learn and simple to use. There are only thirty-two
instructions and four addressing modes. Most of instructions take only 3 oscillator clocks to complete.
The performance and low power consumption make it suitable for battery-powered applications such as
translator, data bank, educational toy, digital voice recorder, etc.
2. Features
Operation Voltage:
2.4V ~ 3.6V
Dual Clock System:
Fast clock:
32768 Hz ~ 8 MHz
Slow clock: 32768 Hz
Four Operation Modes: Fast, Slow, Idle, Sleep modes.
Internal ROM:
1M Bytes (512K Byte Program ROM, 512K Byte Data ROM)
Internal RAM:
6K Bytes (Shared with LCD RAM).
6 ~ 36 bit Bi-directional general purpose I/O port with push-pull or open-Drain output type
selectable for each I/O pin by mask option.
Up to 6400 pixels with 16, 4 gray-scale or Black/White LCD driver.
Segment extender interface with KDGS80.
4 LCD configurations: [32 128], [48 112], [64 96], [80 80].
Built-in LCD power supply with input power regulator, voltage multiplier circuit and bias
generating circuit.
PWM output.
8-bit current-type DAC output.
Built-in OP comparator.
Built-in UART for serial communication.
IR output.
Low voltage reset: 2.2V
Low voltage detection: 2.4V, 2.6V, 2.8V and 3.0V
Built-in keyboard auto scan hardware for up to 420 key matrix (shared with LCD SEG pins)
not only reduces the hardware cost, but also reduces the firmware effort.
Watchdog timer.
Two 16-bit timers and one time-base timer.
Two external interrupts, three internal timer interrupts and one internal UART interrupt.
Instruction set: 32 instructions, 4 addressing modes.
King Billion Electronics Co., Ltd
HE84G770
HE80004H SERIES
October 31, 2003
4
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
3. Functional Block Diagram
SEG
FXI, FXO
COM
LCD
Driver
8 Bit CPU
Fast Clock
OSC.
LCAP?A, LCAP?B, VR12
1 MB ROM
SXI, SXO
LVL[5..1], LGS1, LVREG
LCD Power
Supply
Slow Clock
OSC
6 KB RAM
OLFR, OCCK
PWM
Segment Ext.
Interface
TC1
PWM
SEGD, SEGA
TC2
VO, DAO
Ext. Memory
Interface
DAC
TB
PRTC, PRTD
OPO, OPIN, OPIP
PRT14, PRT15, PRT17
I/O Port
WDT
OP Amp
SIN, SOUT
LVR
IRO
UART
LVD
IR
4. Pin Description
U14
HE84G770
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29 30
31 32
33 34
35 36
37 38
39 40 41
42 43
44 45
46 47
48 49
50 51
52 53
54 55
56 57
58 59
60 61
62 63
64 65
66 67
68 69 70
71 72
73 74
78
79 80
81
77
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
76
75
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100 101
102 103
104 105
106 107
108 109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
CO
M
4
CO
M
3
CO
M
2
CO
M
1
CO
M
0
LC
AP2
B
LC
AP1
B
LC
AP5
A
LC
AP4
A
LC
AP3
A
LC
AP2
A
LC
AP1
A
LV
L5
LV
L4
LV
L3
LV
L2
LV
L1
LG
S1
LV
R
E
G
VR
12
GN
D
VO
DA
O
OP
I
N
OP
I
P
OP
O
RS
T
P
_
N
FX
O
FX
I
TS
TP
_
P
SX
O
SX
I
VX
OL
F
R
O
CCK
VD
D
P
R
TD
[7
]/IN
T2
/
/WK
UP
[5
]
P
R
TD
[6
]/IN
T1
/
W
K
U
P
[
4
]
P
R
TD
[5
]/W
K
U
P
[
3
]
P
R
TD
[4
]/W
K
U
P
[
2
]
P
R
TD
[3
]/W
K
U
P
[
1
]
P
R
TD
[2
]/W
K
U
P
[
0
]
P
R
TD
[1
]/S
IN
P
R
TD
[0
]/S
O
U
T
G
ND_
P
W
M
PW
M
IR
O
P
R
TC
[7
]/S
CNI
[3
]
P
R
TC
[6
]/S
CNI
[2
]
P
R
TC
[5
]/S
CNI
[1
]
P
R
TC
[4
]/S
CNI
[0
]
VD
D
_
R
A
M
SEG79/D[7]
SEG78/D[6]
SE
G
7
7
/
D
[
5]
SE
G
7
6
/
D
[
4]
SE
G
7
5
/
D
[
3]
SE
G
7
4
/
D
[
2]
SE
G
7
3
/
D
[
1]
SE
G
7
2
/
D
[
0]
SE
G71
/
A[
23
]
SE
G70
/
A[
22
]
SE
G69
/
A[
21
]
SE
G68
/
A[
20
]
SE
G67
/
A[
19
]
SE
G66
/
A[
18
]
SE
G65
/
A[
17
]
SE
G64
/
A[
16
]
SE
G63
/
A[
15
]
SE
G62
/
A[
14
]
SE
G61
/
A[
13
]
SE
G60
/
A[
12
]
SE
G59
/
A[
11
]
SE
G58
/
A[
10
]
SE
G
5
7
/
A
[
9]
SE
G
5
6
/
A
[
8]
SE
G
5
5
/
A
[
7]
SE
G
5
4
/
A
[
6]
SE
G
5
3
/
A
[
5]
SE
G
5
2
/
A
[
4]
SE
G
5
1
/
A
[
3]
SE
G
5
0
/
A
[
2]
SE
G
4
9
/
A
[
1]
SE
G
4
8
/
A
[
0]
SE
G
4
7
/
OE
SE
G
4
6
/
W
E
SE
G
4
5
/
C
S
0
SE
G
4
4
/
C
S
1
CS
2
CS
3
SG
KY4
3
SG
KY4
2
SG
KY4
1
SG
KY4
0
SG
KY3
9
SG
KY3
8
SG
KY3
7
SG
KY3
6
SG
KY3
5
SG
KY3
4
SG
KY3
3
SG
KY3
2
SG
KY3
1
SG
KY3
0
SG
KY2
9
SG
KY2
8
SG
KY2
7
SG
KY2
6
SG
KY2
5
SG
KY2
4
SEG
[
23]
/
P
R
T
14[
7
]
SEG
[
22]
/
P
R
T
14[
6
]
SEG
[
21]
/
P
R
T
14[
5
]
SEG
[
20]
/
P
R
T
14[
4
]
SEG
[
19]
/
P
R
T
14[
3
]
SEG
[
18]
/
P
R
T
14[
2
]
SEG
[
17]
/
P
R
T
14[
1
]
SEG
[
16]
/
P
R
T
14[
0
]
SEG
[
15]
/
P
R
T
15[
7
]
SEG
[
14]
/
P
R
T
15[
6
]
SEG
[
13]
/
P
R
T
15[
5
]
SEG
[
12]
/
P
R
T
15[
4
]
SEG
[
11]
/
P
R
T
15[
3
]
SEG
[
10]
/
P
R
T
15[
2
]
SE
G[
9]
/
P
R
T
15[
1
]
SE
G[
8]
/
P
R
T
15[
0
]
SE
G[
7]
/
P
R
T
17[
7
]
SE
G[
6]
/
P
R
T
17[
6
]
SE
G[
5]
/
P
R
T
17[
5
]
SE
G[
4]
/
P
R
T
17[
4
]
SE
G[
3]
/
P
R
T
17[
3
]
SE
G[
2]
/
P
R
T
17[
2
]
SE
G[
1]
/
P
R
T
17[
1
]
SE
G[
0]
/
P
R
T
17[
0
]
CM
S
G
3
2
CM
S
G
3
3
CM
S
G
3
4
CM
S
G
3
5
CM
S
G
3
6
CM
S
G
3
7
CM
S
G
3
8
CM
S
G
3
9
CM
S
G
4
0
CM
S
G
4
1
CM
S
G
4
2
CM
S
G
4
3
CM
S
G
4
4
CM
S
G
4
5
CM
S
G
4
6
CM
S
G
4
7
CM
S
G
4
8
CM
S
G
4
9
CM
S
G
5
0
CM
S
G
5
1
CM
S
G
5
2
CM
S
G
5
3
CM
S
G
5
4
CM
S
G
5
5
CM
S
G
5
6
CM
S
G
5
7
CM
S
G
5
8
CM
S
G
5
9
CM
S
G
6
0
CMSG61
CMSG62
CMSG63
CMSG64
CMSG65
CMSG66
CMSG67
CMSG68
CMSG69
CMSG70
CMSG71
CMSG72
CMSG73
CMSG74
CMSG75
CMSG76
CMSG77
CMSG78
CMSG79
Pin Name
I/O
Description
COM[31..0]
O LCD COMMON Driver pads.
LCAP2B
O Charge Pump Capacitor Pin.
LCAP1B
O Charge Pump Capacitor Pin.
LCAP5A
O Charge Pump Capacitor Pin.
LCAP4A
O Charge Pump Capacitor Pin.
LCAP3A
O Charge Pump Capacitor Pin.
LCAP2A
O Charge Pump Capacitor Pin.
King Billion Electronics Co., Ltd
HE84G770
HE80004H SERIES
October 31, 2003
5
Version:V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
Pin Name
I/O
Description
LCAP1A
O Charge Pump Capacitor Pin.
LVL5
P LCD Bias Voltage 5.
LVL4
P LCD Bias Voltage 4
LVL3 P
LCD Bias Voltage 3
LVL2
P LCD Bias Voltage 2
LVL1
P LCD Bias Voltage 1.
LGS1 I
Regulator
Voltage
Setting
LVREG O
Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns pumped
to LVL5. Adjust resistor between LGS1 and LVREG to set LVREG voltage.
VR12
I Charge Pump Input. The buffered output of the fine-adjusted VREG.
GND
P Power Ground Input.
VO O
DAC
Output.
DAO
O Alternate output of DAC.
OPIN
I Inverting input of OP Amp.
OPIP
I Non-inverting input of OP Amp.
OPO
O Output of OP Amp.
RSTP_N
I System Reset Input Pin. Level trigger, active low on this pin will put the chip in reset state.
FXO,
FXI
O,
B
External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (`0' for RC
type and `1' for crystal type). For RC type oscillator, one resistor needs to be connected
between FXI and GND. For crystal oscillator, one crystal needs to be placed between FXI
and FXO. Please refer to application for details.
TSTP_P I
Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But for
improving ESD, please connect this point with zero Ohm resistor to GND
.
SXO,
SXI
O,
I
External slow clock pins. Slow clock is clock source for LCD display, TIMER1, Time-Base
and other internal blocks. Both crystal and RC oscillator are provided. The slow clock type
can be selected by mask option MO_SXTAL. Choose `0' for RC type and `1' for crystal
oscillator.
VX I
Input pin for x32 PLL circuit. Connect to external resistor and capacitors as shown in
application circuit.
OLFR O
LCD frame signal for interfacing with LCD segment extender KDGS80.
OCCK O
LCD data load pin for interfacing with LCD segment extender KDGS80.
VDD P
Positive power Input. A 0.1 F decoupling capacitors should be placed as close to IC VDD
and GND pads as possible for best decoupling effect.
PRTD[7..2]
PRTD[1]/SIN
PRTD[0]/SOUT
B
8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask
option MO_DPP[7..0] (`1' for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, `1' must be outputted before reading the pin.
PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt sources.
PRTD[1] shares pad with UART Receiver SIN pin.
PRTD[0] shares pad with UART transmitter SOUT pin.
GND_PWM
O Dedicated Ground for PWM output.
PWM O
The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register as one to
turn on PWM. Using VDD & PWM to drive output device.
IRO
O The Infrared output.
PRTC[7..4]/
SCNI[3..0]
B
4-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask
option MO_CPP[7..4] (`1' for push-pull and `0' for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, `1' must be outputted before reading the pin.
PRTC[7..4] is shared with Key Scan Dedicated Input SCNI[3..0]. The Key Scan function
can be disabled by clearing MO_LCDKEY mask option to `0'.
VDD_RAM
P Dedicated power input for RAM
CMSG[32..79] O COM[32..79] pads are shared with SEG[127..80] outputs. The functions of the pads to be
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