Document Outline
- 1 Overview
- 2 Sensor Interface
- 3 Analog Signal Processing Chain
- 4 Additional Operational Conditions
- 5 KAC-0311 Waveform Diagrams
- 6 KAC-0311 Register Reference Map
- 7 Detailed Register Block Assignments
- 8 I2C Serial Interface
- 9 Electrical Characteristics
Revision No. 1
Page 1 of 56
Eastman Kodak Company
Technical Data
Kodak Digital Science KAC-0311 Image Sensor
Eastman Kodak Company - Image Sensor Solutions
For the most current information regarding this product:
Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
KAC 0311
640 x 480 VGA CMOS Image Sensor
Fully Integrated Timing, Analog Signal
Processing & 10 bit ADC
Key Specifications
Pixel Size: 7.8m x 7.8m
Fill factor: 40%
Image Size: 5.0mm x 3.7mm (1/3")
Responsivity: 90,000 electrons/Lux-sec
Saturation Signal: 45,000 electrons
Min Light: 5 Lux at 30FPS/F2 lens
Scan Modes: Progressive/Interlace
Operation Modes: Continuous & Single
Shutter Modes: Rolling or Global
Nominal Readout Rate: 14 MHz
Maximum Readout Rate: 20 MSPS
Frame Rate: 0-60 frames per second
System Dynamic Range: 49 dB
Programmable gain: -3.0dB to 17.4dB
ADC: 10-bit, RSD ADC (DNL +/-0.5
LSB, INL +/-1.0 LSB)
Power Dissipation: 215mW (dynamic) /
25mW (standby)
Features
1/3" Color VGA Digital Image Sensor
640 x 480 pixel progressive/interlace scan
7.8m square pixels with patented pinned photodiode
architecture
Bayer - CMY CFA, Monochrome
High sensitivity, quantum efficiency, and charge con-
version efficiency
Low fixed pattern noise / Wide dynamic range
Patented Electronic Shutter Operation
30fps full VGA at 10MHz Master Clock Rate
60fps full VGA at 20MHz Master Clock Rate
Antiblooming and continuous variable speed shutter
10x linear programmable gain
10-bit, pipelined algorithmic RSD ADC
User selectable digital output formats:
8-bit companded data
10-bit linear data
Pixel addressability to support `Window of Interest'
windowing, resolution, and sub-sampling
Analog column offset correction
Integrated on-chip timing/logic circuitry
Digitally programmable via I
2
C interface
CDS sample and hold for suppression of low fre-
quency and correlated reset noise
Dark reference pixels with automatic Frame Rate
Clamp
Single master clock operation
Single 3.3V power supply
48 pin CLCC package
Release Date: 8/5/2002
Revision No. 1
Page 2 of 56
Eastman Kodak Company
Technical Data
Kodak Digital Science KAC-0311 Image Sensor
Eastman Kodak Company - Image Sensor Solutions
For the most current information regarding this product:
Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
Figure 1: KAC-0311 Block Diagram
The KAC-0311 is a fully integrated, high performance 1/3" optical format VGA CMOS image sensor including integrated
timing control and programmable analog signal processing. This sensor provides system designers a complete imaging solu-
tion with a monolithic image capture and processing engine. System benefits enable design of smaller, portable, low cost and
low power systems. Each pixel on the sensor is individually addressable allowing the user to control the "Window of Inter-
est" (WOI), panning and zooming, sub-sampling, resolution, exposure, white balance, and other image processing features
via a two pin I
2
C compatible interface. This device runs from a single 3.3V supply and single master clock.
The imager uses Kodak's patented Pinned Photodiode CMOS active pixels. The 7.8
m pixel design provides true correlated
double sampling for low read noise operation, high quantum efficiency, low dark current, and no image lag. Kodak's pat-
ented pixel design combined with low noise mixed signal circuits provides a high sensitivity, low noise integrated "camera
on a chip".
704
VGA ACI Image Sensor Array
Column Decode, Sensing, CDS, and Muxing
Column
Sequencer
& Drivers
11
16
22
17
42
28
25
26
30
41
40
39
38
37
36
45
44
43
Master Row
Se
qu
encer,
I
nteg
r
ati
o
n
C
ontr
ol,
an
d Tim
ing
Generat
o
r
R
o
w
De
c
o
d
e
r
a
n
d
Dr
i
v
e
r
s
48
0
640
51
2
12Dark + 8Isolation
4Dark + 8Isolation
40D
ark
+ 8Isola
ti
on
8Da
rk
+ 8Iso
lat
ion
21
20
0 1
0
1
HCLK
VCLK
SOF
TRIGGER
EXTRES
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
MCLK
SCLK
SDATA
INIT
Column
DOVA
WB
PGA
0.84
2.73x
Exposure
PGA A&B
0.84
2.73x
Global
Dova
2.0x
6dB
-
1.51
8.72 dB
2.0x
6dB
Frame
Rate
Clamp
10 Bit
RSD
Pipelined
ADC
CFRCB
CFRCA
Bandgap
Reference
and Bias
Generation
18
19
CVREFP
CVREFM
46
47
48
1
2
3
4
5
6
7
I
2
C Serial
Interface and
Register Decode
6
6
6
6
6
Mux and
Color Sequencer
6
6
6
13
24
A
VDD
8
D
VDD
N/C
N/C
N/C
N/C
10
BL
ANK
N/C
12
27
ST
B
Y
N/C
29
TS
23
AV
S
S
9
DV
S
S
31
D
VDD
-
1.51
8.72 dB
35
34
33
32
15
14
N/C
N/C
N/C
N/C
N/C
N/C
AV
D
D
AV
D
D
AV
S
S
AV
S
S
DV
S
S
Revision No. 1
Page 3 of 56
Eastman Kodak Company
Technical Data
Kodak Digital Science KAC-0311 Image Sensor
Eastman Kodak Company - Image Sensor Solutions
For the most current information regarding this product:
Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
Pin
No.
Pin
Name
Description
Pin
Type
Power
Value
Pin
No.
Pin
Name
Description
Pin
Type
Power
Value
1
ADC6
Output Bit 6=64d
O
D
25
SCLK
I
2
C Serial Clock Line
I
D
2
ADC5
Output Bit 5=32d
O
D
26
SDATA
I
2
C Serial Data Line
I/O
D
3
ADC4
Output Bit 4=16d
O
D
27
STBY
Power Down Standby Enable
I
D
4
ADC3
Output Bit 3=8d
O
D
28
INIT
Sensor Initialize
I
D
5
ADC2
Output Bit 2=4d
O
D
29
TS
Dig Output Tri-State Enable
I
D
6
ADC1
Output Bit 1=2d
O
D
30
TRIGGER Still Frame Capture Trigger
I
D
7
ADC0
Output Bit 0=1d
O
D
31
DVDD
Digital Power
P
D
3.3 V
8
DVDD
Digital Power
P
D
3.3 V
32
NC
Unused
I
D
9
DVSS
Digital Ground
G
D
0 V
33
NC
Unused
I
D
10
BLANK
Pixel Invalid
O
D
34
NC
Unused
I
D
11
AVDD
Analog Power
P
A
3.3 V
35
NC
Unused
I
D
12
AVSS
Analog Ground
G
A
0 V
36
NC
Unused
I
D
13
EXTRES
External Bias Resistor
I
A
27k
37
NC
Unused
I
D
14
NC
Unused
A
38
NC
Unused
I
D
15
NC
Unused
A
39
NC
Unused
I
D
16
AVDD
Analog Power
P
A
3.3 V
40
NC
Unused
I
D
17
AVSS
Analog Ground
G
A
0 V
41
NC
Unused
I
D
18
CVREFM ADC Bottom Bias Ref Capacitor
O
A
0.1F
42
DVSS
Digital Ground
G
D
0 V
19
CVREFP
ADC Top Bias Ref Capacitor
O
A
0.1F
43
HCLK
Pixel Sync
O
D
20
CFRCB
Frame Rate Clamp Capacitor
O
A
1.0F
44
VCLK
Line Sync
O
D
21
CFRCA
Frame Rate Clamp Capacitor
O
A
1.0F
45
SOF
Start of Frame Sync
O
D
22
AVDD
Analog Power
P
A
3.3 V
46
ADC9
Output Bit 9=512d
O
D
23
AVSS
Analog Ground
G
A
0 V
47
ADC8
Output Bit 8=256d
O
D
24
MCLK
Master Clock = Pixel Rate
I
D
48
ADC7
Output Bit 7=128d
O
D
KAC-0311 Pin Definitions
Optical
Center
181.5um (7.1mil)
1225.
5um
(
48.
2m
il
)
Die Placement
position tolerance
200um (7.9mil)
Die Center
(0,0)
Column 0
Row 0
7
8
9
10
11
12
13
14
15
16
17
18
31
32
33
34
35
36
37
38
39
40
41
42
2
3
4
5
6
19
20
21
22
23
2
4
25
26
27
28
2
9
30
43
44
45
46
47
48
1
0.280" (7.11mm)
0.
280"
(
7
.
11m
m
)
Figure 2 Pinout Diagram
Legend:
P = VDD
G = VSS
I = Input
O = Output
D = Digital
A = Analog
Revision No. 1
Page 4 of 56
Eastman Kodak Company
Technical Data
Kodak Digital Science KAC-0311 Image Sensor
Eastman Kodak Company - Image Sensor Solutions
For the most current information regarding this product:
Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
Table Of Contents
1
Overview .....................................................................................................................................................................7
2
Sensor Interface...........................................................................................................................................................8
2.1
Pixel Architecture........................................................................................................................................................8
2.2
Color Filters.................................................................................................................................................................9
2.3
Frame Capture Modes ...............................................................................................................................................10
2.3.1
Continuous Frame Rolling Shutter Capture Mode (CFRS).......................................................................................10
2.3.2
Single Frame Rolling Shutter capture mode (SFRS).................................................................................................10
2.3.3
Single Frame Global Shutter capture mode (SFGS) .................................................................................................10
2.3.4
Image Scan Modes ....................................................................................................................................................10
2.3.5
Window of Interest Control.......................................................................................................................................11
2.3.6
Sub-Sampling Control(Resolution) ...........................................................................................................................11
2.4
Virtual Frame (VF)....................................................................................................................................................11
2.5
Integration Time ........................................................................................................................................................12
2.5.1
CFRS Integration Time .............................................................................................................................................12
2.5.2
SFRS Integration Time..............................................................................................................................................12
2.5.3
SFGS Integration Time Control ................................................................................................................................12
2.6
Frame Rate ................................................................................................................................................................12
2.6.1
CFRS Frame Rate......................................................................................................................................................13
2.6.2
SFRS Frame Rate ......................................................................................................................................................13
2.6.3
SFGS Frame Rate......................................................................................................................................................13
3
Analog Signal Processing Chain Overview ..............................................................................................................14
3.1
Correlated Double Sampling (CDS)..........................................................................................................................14
3.2
Frame Rate Clamp (FRC)..........................................................................................................................................14
3.2.1
Column Digital Offset Voltage Adjust (DOVA).......................................................................................................15
3.2.2
Digitally Programmable Gain Amplifiers (DPGA)...................................................................................................15
3.2.3
White Balance Control PGA .....................................................................................................................................15
3.2.4
Global Gain PGA ......................................................................................................................................................16
3.2.5
Global Digital Offset Voltage Adjust (DOVA).........................................................................................................16
3.2.6
Analog to Digital Converter (ADC)..........................................................................................................................16
3.2.7
Digital Signal Post Processing Data Compander ......................................................................................................17
4
Additional Operational Conditions............................................................................................................................17
4.1
Initialization...............................................................................................................................................................17
4.2
Standby Mode ...........................................................................................................................................................17
4.3
Internal Bias Current Control ....................................................................................................................................17
4.4
Readout Speed...........................................................................................................................................................18
5
KAC-0311 Waveform Diagrams...............................................................................................................................19
5.1
CFRS Data Waveforms .............................................................................................................................................19
5.2
SFGS Data Waveforms .............................................................................................................................................21
6
KAC-0311 Register Reference Map .........................................................................................................................22
7
Detailed Register Block Assignments .......................................................................................................................25
7.1
Color Gain Registers 00h 03h ..............................................................................................................................25
7.2
Reference Voltage Adjust Registers (0A
h
, 0B
h
)........................................................................................................27
7.3
Power Configuration Registers (0C
h
)........................................................................................................................28
7.4
Reset and Tristate Control Register (0E
h
) .................................................................................................................29
7.5
Global Gain Register (10
h
) ........................................................................................................................................29
7.6
Column DOVA DC Register (20
h
)............................................................................................................................30
Revision No. 1
Page 5 of 56
Eastman Kodak Company
Technical Data
Kodak Digital Science KAC-0311 Image Sensor
Eastman Kodak Company - Image Sensor Solutions
For the most current information regarding this product:
Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
7.7
Column DOVA Control (21
h
) ...................................................................................................................................31
7.8
Column DOVA RAM (22
h
) ......................................................................................................................................32
7.9
Global DOVA (23
h
) ..................................................................................................................................................33
7.10
Post ADC Control (32
h
) ............................................................................................................................................34
7.11
Capture Mode Control (40
h
)......................................................................................................................................35
7.12
Subsample Control (41
h
) ...........................................................................................................................................36
7.13
Programmable Window of Interest (WOI) (45
h
-4C
h
)................................................................................................37
7.14
Integration Time Control (4D
h
4F
h
)......................................................................................................................40
7.15
Programmable Virtual Frame (50
h
53
h
)................................................................................................................41
7.16
SOF Control Register (54
h
) .......................................................................................................................................43
7.17
VCLK Control Register (55
h
)....................................................................................................................................43
7.18
Internal Timing Control Register (60h).....................................................................................................................44
8
I
2
C Serial Interface ....................................................................................................................................................45
8.1
KAC-0311 I
2
C Bus Protocol .....................................................................................................................................46
8.2
START Signal ...........................................................................................................................................................46
8.3
Slave Address Transmission .....................................................................................................................................46
8.4
Acknowledgment.......................................................................................................................................................46
8.5
Data Transfer.............................................................................................................................................................46
8.6
Stop Signal ................................................................................................................................................................47
8.7
Repeated START Signal ...........................................................................................................................................47
8.8
I
2
C Bus Clocking and Synchronization.....................................................................................................................47
8.9
Register Write ...........................................................................................................................................................47
8.10
Register Read ............................................................................................................................................................48
9
Electrical Characteristics ...........................................................................................................................................50
Table Of Figures
Figure 1: KAC-0311 Block Diagram ........................................................................................................................................2
Figure 2 Pinout Diagram ..........................................................................................................................................................3
Figure 3: KAC-0311 Spectral Response....................................................................................................................................9
Figure 4: Optional Bayer CMY Pattern CFA ............................................................................................................................9
Figure 5: WOI Definition ........................................................................................................................................................11
Figure 6: Bayer x Sub-sample Example. .........................................................................................................................11
Figure 7: Virtual Frame Definition..........................................................................................................................................12
Figure 8: Conceptual block diagram of CDS...........................................................................................................................14
Figure 9: FRC Conceptual Block Diagram..............................................................................................................................14
Figure 10: Color Gain Register Selection................................................................................................................................16
Figure 11: Available Companding Curves ..............................................................................................................................17
Figure 12: Power Consumption dependence on External Resistor..........................................................................................18
Figure 13 : Dynamic Range wrt Mclk Frequency ...................................................................................................................18
Figure 14: CFRS Default Frame Sync Waveforms .................................................................................................................19
Figure 15: CFRS Default Row Syncs Waveforms ..................................................................................................................19
Figure 16: SFRS Single Frame Mode Sync Waveforms .........................................................................................................20
Figure 17: SFRS Interlaced Scan Mode Sync Waveforms......................................................................................................21
Figure 18: Frame View of SFGS Sync Waveforms ................................................................................................................21
Figure 19: One row view of SFGS Sync Waveforms..............................................................................................................21
Figure 20: I
2
C Bus WRITE Cycle ...........................................................................................................................................45
Figure 21: I
2
C Bus READ Cycle .............................................................................................................................................49
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