K A F - 2 2 0 0 0 C E R e v . 2 . 0

w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

TABLE OF CONTENTS

DEVICE DESCRIPTION ............................4

RCHITECTURE

..........................................4

Dark Reference Pixels........................4
Active Buffer Pixels .............................4
Dummy Pixels......................................5
CTE Monitor Pixels .............................5

MAGE

CQUISITION

...................................5

HARGE

RANSPORT

.................................5

ORIZONTAL

EGISTER

.............................6

Output Structure ..................................6
Output Load..........................................7

HYSICAL

ESCRIPTION

............................8

Pin Description and Device
Orientation ............................................8

PERFORMANCE ......................................10

Image Performance Operational
Conditions...........................................10
Imaging Performance Specifications
..............................................................10
Typical Performance Curves...........12

EFECT

EFINITIONS

...............................13

Defect Operational Conditions........13
Defect Specifications ........................13

OPERATION ..............................................14

BSOLUTE

AXIMUM

ATINGS

................14

Power-up Sequence .........................14

DC B

IAS

PERATING

ONDITIONS

.........15

AC O

PERATING

ONDITIONS

..................15

Clock Levels.......................................15
Timing Requirements........................16
Frame Timing.....................................17
Frame Timing Detail..........................17
Line Timing.........................................18

PIXEL TIMING...........................................18

Pixel Timing........................................18
Pixel Timing Detail ............................19
Pixel Timing Edge Alignment ..........20

MODE OF OPERATION ..........................20

Power-up Flush Cycle ......................20

STORAGE AND HANDLING..................21

TORAGE

ONDITIONS

............................21

ESD .........................................................21
C

OVER GLASS

ARE

................................21

OLDERING

ECOMMENDATIONS

............21

MECHANICAL DRAWINGS ...................22

PACKAGE..................................................22

LASS

......................................................23

QUALITY ASSURANCE AND
RELIABILITY.............................................24

ORDERING INFORMATION ...................25

VAILABLE

ART

ONFIGURATIONS

........25

REVISION CHANGES ............................26

TABLE OF FIGURES

Figure 1 - Sensor Architecture .........................4
Figure 2 - Output Architecture..........................6
Figure 3 � Recommended Output Structure Load

Diagram .................................................7

Figure 5 � Typical Quantum Efficiency ...........12
Figure 6 � Typical Blooming Performance ......12
Figure 7 - Frame Timing ................................17
Figure 8 - Frame Timing Detail ......................17
Figure 9 - Line Timing ...................................18
Figure 10 � Pixel Timing................................18
Figure 11 - Pixel Timing Detail .......................19
Figure 12 - Pixel Timing Edge Alignment ........20
Figure 13 � Power-up Flush Cycle .................20
Figure 14 - Package Drawing ........................22
Figure 15 - Glass Drawing .............................23

K A F - 2 2 0 0 0 C E R e v . 2 . 0

w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

SUMMARY S P E C I F I C A T I O N

KODAK KAF-22000CE Image Sensor

4080 (H) x 5440 (V) Full-Frame
CCD Color Image Sensor

Description

The KAF-22000CE is a high
performance color array CCD (charge
coupled device) image sensor with
4080(H) x 5440(V) photoactive pixels
designed for a wide range of color image
sensing applications including digital
imaging. Each pixel contains anti-
blooming protection by means of a lateral
overflow drain thereby preventing image
corruption during high light level
conditions. Each of the 9�m square
pixels are selectively covered with red,
green or blue pigmented filters for color
separation. The photoactive pixels are
surrounded by a border of buffer and
light shielded pixels as shown in Figure
1. Total chip size is 38.8 mm x 50.0 mm
and is housed in a 44 pin, 2.010" wide
DIL ceramic package with 0.100" pin
spacing.

REVISION NO.: 2.0
EFFECTIVE DATE: July 28, 2003

Parameter

Typical Value

Architecture

Full Frame CCD; with

Square Pixels

Total Number of Pixels

4145 (H) x 5488 (V) =

22.7M

Number of Effective
Pixels

4098 (H) x 5458 (V) =

22.4M

Number of Active
Pixels

4080 (H) x 5440 (V) =

22.2M

Pixel Size

�

m (H) x 9

�

m (V)

Imager Size

61.2 mm (diagonal)

Chip Size

38.8mm (H) x

50.0mm (V)

Aspect Ratio

4:3

Saturation Signal

94 K e

Charge to Voltage
Conversion

17.5 �V/e

Quantum Efficiency
(RGB)

0.23, 0.19, 0.17

Total Noise

21 e

Dark Signal

4 mV

Dark Current Doubling

Temperature

6.3 dC

Linear Dynamic Range

73 dB

Charge Transfer
Efficiency

0.999999

Blooming Protection

@4ms exposure time

1200 x saturation

exposure

Maximum Data Rate

20 MHz

All parameters above are specified at T = 20*C

K A F - 2 2 0 0 0 C E R e v . 2 . 0

w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

DEVICE DESCRIPTION

Architecture

Figure 1 - Sensor Architecture

Dark Reference Pixels

Surrounding the periphery of the device
is a border of light shielded pixels. This
includes 20 leading and 9 trailing pixels
on every line excluding dummy pixels.
There are also 20 full dark lines at the
start of every frame and 9 full dark lines
at the end of each frame. Under normal
circumstances, these pixels do not
respond to light. However, dark
reference pixels in close proximity to an
active pixel, or the outer bounds of the

chip (including the first two lines out), can
scavenge signal depending on light
intensity and wavelength.

Active Buffer Pixels

The first 9 pixels in from any dark
reference regions are classified as active
buffer pixels. These pixels are light
sensitive but tend to have inconsistent
spectral responsivities than the remainder
of the array. Active buffer pixels are not
tested for defects and uniformity.

VDD

VSS

VOUT

SUB

H1L

Color Filter Pattern

Last Hccd Phase: H1

Last Vccd Phase: V2

9 Active Buffer
20 Dark

2 Dummy

1 Active (CTE Monitor)

11 Dummy

3 Dummy

LODT

LODB

9 Active Buffer Lines

5440 Active Lines/Frame

20 Dark Lines

9 Dark

1 Active (CTE Monitor)

4080 Active Pixels/Line

9 Active Buffer

Usable Active Image Area

4080 (H) x 5440 (V)

9 microns x 9 microns pixels

KAF-22000CE

9 Active Buffer Lines

9 Dark Lines

K A F - 2 2 0 0 0 C E R e v . 2 . 0

w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Dummy Pixels

Within the horizontal shift register are 11
leading and 2 trailing additional shift
phases, which are not associated with a
column of pixels within the vertical
register. These pixels contain only
horizontal shift register dark current
signal and do not respond to light. A few

leading dummy pixels may scavenge
false signal depending on operating
conditions.

CTE Monitor Pixels

Two CTE test colum ns, one on each of
the leading and trailing ends and one
CTE test row are included for
manufacturing test purposes.

Image Acquisition

An electronic representation of an image
is formed when incident photons falling
on the sensor plane create electron-hole
pairs within the device. These photon
induced electrons are collected locally
by the formation of potential wells at
each photogate or pixel site. The
number of electrons collected is linearly
dependent on light level and exposure

time and non-linearly dependent on
wavelength. When the pixel's capacity
is reached, excess electrons are
discharged into the lateral overflow drain
to prevent crosstalk or `blooming'.
During the integration period, the V1
and V2 register clocks are held at a
constant (low) level

Charge Transport

The integrated charge from each
photogate is transported to the output
using a two step process. Each line
(row) of charge is first transported from
the vertical CCD's to a horizontal CCD
register using the V1 and V2 register
clocks. The horizontal CCD is presented
a new line on the falling edge of V2
while H1 is held high. The horizontal
CCD's then transport each line, pixel by

pixel, to the output structure by
alternately clocking the H1 and H2 pins
in a complementary fashion. A separate
connection to the last H1 phase (H1L) is
provided to improve the transfer speed
of charge to the floating diffusion. On
each falling edge of H1 a new charge
packet is dumped onto a floating
diffusion and sensed by the output
amplifier.

Электронный компонент: KAF-22000CE