ispLSI

1032/883

In-System Programmable High Density PLD

Features

· HIGH-DENSITY PROGRAMMABLE LOGIC

-- High Speed Global Interconnect
-- 6000 PLD Gates
-- 64 I/O Pins, Eight Dedicated Inputs
-- 192 Registers
-- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
-- Small Logic Block Size for Fast Random Logic
-- Security Cell Prevents Unauthorized Copying

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 60 MHz Maximum Operating Frequency

pd = 20 ns Propagation Delay

-- TTL Compatible Inputs and Outputs
-- Electrically Erasable and Reprogrammable
-- Non-Volatile E

CMOS Technology

-- 100% Tested

· IN-SYSTEM PROGRAMMABLE

-- In-System ProgrammableTM (ISPTM) 5-Volt Only
-- Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

-- Reprogram Soldered Devices for Faster Prototyping

· COMBINES EASE OF USE AND THE FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEX-

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

-- Complete Programmable Device Can Combine Glue

Logic and Structured Designs

-- Four Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global

Interconnectivity

· ispDesignEXPERTTM LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

1032MIL_01

Functional Block Diagram

Output Routing Pool

D7 D6 D5 D4 D3 D2 D1 D0

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

Output Routing Pool

Global Routing Pool (GRP)

Logic

Array

D Q

GLB

Description

The ispLSI 1032/883 is a High-Density Programmable
Logic Device processed in full compliance to MIL-STD-
883. This military grade device contains 192 Registers,
64 Universal I/O pins, eight Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1032/883
features 5-Volt in-system programming and in-system
diagnostic capabilities. It is the first device which offers
non-volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 1032/883 device is
the Generic Logic Block (GLB). The GLBs are labeled A0,
A1 .. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032/883 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

September 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications

ispLSI 1032/883

Functional Block Diagram

Figure 1. ispLSI 1032/883 Functional Block Diagram

The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional I/O pin with
3-state control. Additionally, all outputs are polarity se-
lectable, active high or active low. The signal levels are
TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA.

Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI 1032/883 device con-
tains four of these Megablocks.

The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 1032/883 device are selected using
the Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032/883 device). The logic of this GLB allows the user
to create an internal clock from a combination of internal
signals within the device.

I/O 0
I/O 1

I/O 2

I/O 3

IN 5
IN 4

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13
I/O 14

I/O 15

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42
I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 33

I/O 32

SDI/IN 0

MODE/IN 1

I/O

SDO/IN 2

SCLK/IN 3

I/O 4

I/O 5

RESET

Global

Routing

Pool

(GRP)

Output Routing Pool (ORP)

CLK 0

CLK 1
CLK 2
IOCLK 0
IOCLK 1

Clock

Distribution

Network

Output Routing Pool (ORP)

Generic

Logic Blocks

(GLBs)

Megablock

Output Routing Pool (ORP)

Input Bus

ispEN

lnput Bus

0139(1)-32-isp

Specifications

ispLSI 1032/883

Absolute Maximum Ratings

Supply Voltage V

................................... -0.5 to +7.0V

Input Voltage Applied ........................ -2.5 to V

+1.0V

Off-State Output Voltage Applied ..... -2.5 to V

+1.0V

Storage Temperature ................................ -65 to 150

Case Temp. with Power Applied .............. -55 to 125

Max. Junction Temp. (T

) with Power Applied ... 150

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

PARAMETER

SYMBOL

MIN.

MAX.

UNITS

5.5

0.8

Vcc + 1

Supply Voltage

0005A mil.eps

4.5

2.0

Military/883

= -55

C to +125

Input Low Voltage

Input High Voltage

Capacitance (T

=25

C, f=1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM

UNITS

TEST CONDITIONS

=5.0V, V

=2.0V

I/O and Clock Capacitance

=5.0V, V

I/O

, V

=2.0V

1. Characterized but not 100% tested.

Table 2- 0006mil

Dedicated Input Capacitance

Data Retention Specifications

Table 2- 0008B

PARAMETER

Data Retention

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10000

Years

Cycles

Specifications

ispLSI 1032/883

Switching Test Conditions

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Time

3ns 10% to 90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See figure 2

3-state levels are measured 0.5V from steady-state
active level.

Table 2- 0003

Output Load Conditions (see figure 2)

Test Condition

470

390

35pF

Active High

390

35pF

Active Low

470

390

35pF

Active High to Z

390

5pF

at V

- 0.5V

Active Low to Z

470

390

5pF

at V

+ 0.5V

Figure 2. Test Load

+ 5V

Device
Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

DC Electrical Characteristics

Over Recommended Operating Conditions

0.4

-10

-150

-200

220

IL-isp

IL-PU

2,4

=8 mA

=-4 mA

(MAX.)

3.5V

(MAX.)

= 5V, V

OUT

= 0.5V

= 0.5V, V

= 3.0V

TOGGLE

= 1 MHz

135

2.4

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

Output Low Voltage

Output High Voltage

Input or I/O Low Leakage Current

Input or I/O High Leakage Current

isp Input Low Leakage Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

UNITS

TYP.

1. One output at a time for a maximum duration of one second. V

out

= 0.5V was selected to avoid test problems by tester ground

degradation. Characterized but not 100% tested.

2. Measured using six 16-bit counters.
3. Typical values are at V

= 5V and T

= 25

4. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-

tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
I

0007A-32 mil

Specifications

ispLSI 1032/883

External Timing Parameters

Over Recommended Operating Conditions

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.

MIN. MAX.

Data Propagation Delay, 4PT bypass, ORP bypass

Data Propagation Delay, Worst Case Path

Clock Frequency with Internal Feedback

Clock Frequency with External Feedback

Clock Frequency, Max Toggle

GLB Reg. Setup Time before Clock, 4PT bypass

GLB Reg. Clock to Output Delay, ORP bypass

GLB Reg. Hold Time after Clock, 4 PT bypass

GLB Reg. Setup Time before Clock

GLB Reg. Clock to Output Delay

GLB Reg. Hold Time after Clock

Ext. Reset Pin to Output Delay

Ext. Reset Pulse Duration

Input to Output Enable

Input to Output Disable

Ext. Sync. Clock Pulse Duration, High

Ext. Sync. Clock Pulse Duration, Low

I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)

I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

MHz

pd1

pd2

max (Int.)

max (Ext.)

max (Tog.)

su1

co1

su2

co2

rw1

dis

su5

DESCRIPTION

PARAMETER

UNITS

TEST

COND.

tsu2 + tco1

( )

2.5

8.5

22.5

-60

Table 2-0030-32/60C

Specifications

ispLSI 1032/883

Internal Timing Parameters

7.3

1.3

6.0

4.6

2.7

4.0

3.3

5.3

2.0

2.7

4.0

5.0

6.0

10.6

8.6

9.3

10.6

12.7

1.3

2.7

3.3

13.3

12.0

9.9

3.3

0.7

MIN. MAX.

DESCRIPTION

PARAMETER

UNITS

-60

Inputs
t

iobp

iolat

iosu

ioh

ioco

ior

din

GRP
t

grp1

grp4

grp8

grp12

grp16

grp32

GLB
t

4ptbp

1ptxor

20ptxor

xoradj

gbp

gsu

gco

ptre

ptoe

ptck

ORP
t

orp

orpbp

I/O Register Bypass

I/O Latch Delay

I/O Register Setup Time before Clock

I/O Register Hold Time after Clock

I/O Register Clock to Out Delay

I/O Register Reset to Out Delay

Dedicated Input Delay

GRP Delay, 1 GLB Load

GRP Delay, 4 GLB Loads

GRP Delay, 8 GLB Loads

GRP Delay, 12 GLB Loads

GRP Delay, 16 GLB Loads

GRP Delay, 32 GLB Loads

4 Product Term Bypass Path Delay

1 Product Term/XOR Path Delay

20 Product Term/XOR Path Delay

XOR Adjacent Path Delay

GLB Register Bypass Delay

GLB Register Setup Time before Clock

GLB Register Hold Time after Clock

GLB Register Clock to Output Delay

GLB Register Reset to Output Delay

GLB Product Term Reset to Register Delay

GLB Product Term Output Enable to I/O Cell Delay

GLB Product Term Clock Delay

ORP Delay

ORP Bypass Delay

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.

Specifications

ispLSI 1032/883

Internal Timing Parameters

6.0

4.6

1.3

4.6

1.3

4.0

6.7

6.0

7.3

6.6

7.3

6.6

12.0

Outputs
t

oen

odis

Clocks
t

gy0

gy1/2

gcp

ioy2/3

iocp

Global Reset
t

Output Buffer Delay

I/O Cell OE to Output Enabled

I/O Cell OE to Output Disabled

Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

Clock Delay, Y1 or Y2 to Global GLB Clock Line

Clock Delay, Clock GLB to Global GLB Clock Line

Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

Clock Delay, Clock GLB to I/O Cell Global Clock Line

Global Reset to GLB and I/O Registers

MIN. MAX.

DESCRIPTION

PARAMETER

UNITS

-60

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.

Specifications

ispLSI 1032/883

ispLSI 1032/883 Timing Model

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

4 PT Bypass

20 PT

XOR Delays

Control
PTs

GRP

Delay

Input

Clock

Distribution

I/O Pin

(Input)

Y1,2,3

GRP 4

GLB Reg Bypass

ORP Bypass

RST

I/O Reg Bypass

I/O Cell

ORP

GLB

GRP

I/O Cell

#21 - 25

#27, 29,

30, 31, 32

#28

#33

#34, 35, 36

#51, 52,

53, 54

#42, 43,

#50

#45

#46

Reset

Ded. In

#26

#20

RST

#55

#37

#38, 39,

40, 41

#48, 49

#47

1. Calculations are based upon timing specifications for the ispLSI 1032-60.

Derivations of

su,

h and

co from the Product Term Clock

= Logic + Reg su - Clock (min)
=

iobp +

grp4 +

20ptxor

)

gsu

) - (t

iobp +

grp4 +

ptck(min)

)

(

#20 + #28 + #35

)

(

#38

) - (

#20 + #28 + #44

)

7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (2.7 + 2.7 + 4.6)

= Clock (max) + Reg h - Logic
=

iobp +

grp4 +

ptck(max)

)

) - (t

iobp +

grp4 +

20ptxor

)

(

#20 + #28 + #44

)

(

#39

) - (

#20 + #28 + #35

)

5.3 ns = (2.7 + 2.7 + 9.9) + (6.0) - (2.7 + 2.7 + 10.6)

= Clock (max) + Reg co + Output
=

iobp +

grp4 +

ptck(max)

)

gco

)

orp +

)

(

#20 + #28 + #44

)

(

#40

)

(

#45 + #47

)

25.3 ns = (2.7+ 2.7 +9.9) + (2.7) + (3.3 + 4.0)

Derivations of

su,

h and

co from the Clock GLB

= Logic + Reg su - Clock (min)
=

iobp +

grp4 +

20ptxor

)

gsu

) - (t

gy0(min) +

gco +

gcp(min)

)

(

#20 + #28 + #35

)

(

#38

) - (

#50 + #40 + #52

)

7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (6.0 + 2.7 + 1.3)

= Clock (max) + Reg h - Logic
=

gy0(max) +

gco +

gcp(max)

)

) - (t

iobp +

grp4 +

20ptxor

)

(

#50 + #40 + #52

)

(

#39

) - (

#20 + #28 + #35

)

5.3 ns = (6.0 + 2.7 + 6.6) + (6.0) - (2.7 + 2.7 + 10.6)

= Clock (max) + Reg co + Output
=

gy0(max) +

gco +

gcp(max)

)

gco

)

orp +

)

(

#50 + #40 + #52

)

(

#40

)

(

#45 + #47

)

25.3 ns = (6.0 + 2.7 + 6.6) + (2.7) + (3.3 + 4.0)

Specifications

ispLSI 1032/883

Maximum GRP Delay vs GLB Loads

ispLSI 1032-60

0126A-80-32-mil

GLB Loads

GRP Delay (ns)

Power Consumption

used. Figure 3 shows the relationship between power
and operating speed.

Power consumption in the ispLSI 1032/883 device de-
pends on two primary factors: the speed at which the
device is operating, and the number of Product Terms

Figure 3. Typical Device Power Consumption vs fmax

100

150

200

250

max (MHz)

CC (mA)

Notes: Configuration of eight 16-bit Counters
Typical Current at 5V, 25ßC

ispLSI 1032

0127A-32-80-isp

ICC can be estimated for the ispLSI 1032 using the following equation:

ICC = 52 + (# of PTs * 0.30) + (# of nets * Max. freq * 0.009) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device

The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.

Specifications

ispLSI 1032/883

Pin Description

RESET

E11

G11

GND

C6,

F3,

F9,

F2,

F11

I/O 0 - I/O 3

F1,

H1,

H2,

J1,

I/O 4 - I/O 7

K1,

J2,

L1,

K2,

I/O 8 - I/O 11

K3,

L2,

L3,

K4,

I/O 12 - I/O 15

L4,

J5,

K5,

L5,

I/O 16 - I/O 19

L7,

K7,

L6,

L8,

I/O 20 - I/O 23

K8,

L9,

L10,

K9,

I/O 24 - I/O 27

L11,

K10,

J10,

K11,

I/O 28 - I/O 31

J11,

H10, H11, F10,

I/O 32 - I/O 35

E9,

D11, D10, C11,

I/O 36 - I/O 39

B11,

C10, A11,

B10,

I/O 40 - I/O 43

B9,

A10,

A9,

B8,

I/O 44 - I/O 47

A8,

B6,

B7,

A7,

I/O 48 - I/O 51

A5,

B5,

C5,

A4,

I/O 52 - I/O 55

B4,

A3,

A2,

B3,

I/O 56 - I/O 59

A1,

B2,

C2,

B1,

I/O 60 - I/O 63

C1,

D2,

D1,

IN 4 - IN 7

E10,

C7,

A6,

Dedicated input pins to the device.

Input/Output Pins - These are the general purpose I/O pins used by the
logic array.

Name

CPGA Pin Numbers

Description

Input Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.

Input This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.

Input This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.

Input/Output This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.

Input This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.

ispEN

SDI/IN 0

MODE/IN 1

SDO/IN 2

SCLK/IN 3

G10

Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.

Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.

Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.

Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.

Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.

No Connect

Ground (GND)
V

Table 2-0002-32/883

1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.

Specifications

ispLSI 1032/883

/O38

/O36

/O35

/O33

Vcc

/O30

/O28

/O27

/O24

/O41

/O39

/O37

/O34

/O31

*SCLK/

/O29

/O26

/O25

/O22

/O42

/O40

/O32

GND

/O23

/O21

/O44

/O43

/O20

/O19

/O47

/O46

*SDO/

/O17

/O16

/O45

GND

*MODE/

/O18

/O48

/O49

/O50

/O13

/O14

/O15

/O51

/O52

/O11

/O12

/O53

/O55

INDEX

/O63

GND

ispEN

/O8

/O10

/O54

/O57

/O58

/O61

Vcc

*SDI/

/O2

/O5

/O7

/O9

/O56

/O59

/O60

/O62

/O0

RESET

/O1

/O3

/O4

/O6

ispLSI 1032/883

Bottom View

11 10 9 8 7 6 5 4 3 2 1

PIN A1

*Pins have dual function capability.

0488A-32-isp/883

Pin Configuration

ispLSI 1032/883/883 84-Pin CPGA Pinout Diagram

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