ispLSI

1048C/883

In-System Programmable High Density PLD

1048CMIL_01

Functional Block Diagram

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

E7 E6 E5 E4 E3 E2 E1 E0

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

Logic

Array

D Q

Global Routing Pool (GRP)

GLB

0139G1A-isp

Description

The ispLSI 1048C/883 is a High-Density Programmable
Logic Device processed in full compliance to MIL-STD-
883. This military grade device contains 288 Registers,
96 Universal I/O pins, 12 Dedicated Input pins, two
Global Output Enables (GOE), four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1048C/883 features 5-Volt in-
system programming and in-system diagnostic
capabilities. It is the first device which offers non-volatile
reprogrammability of the logic, and the interconnect to
provide truly reconfigurable systems. Compared to the
ispLSI 1048, the ispLSI 1048C/883 offers two additional
dedicated inputs and two new Global Output Enable pins.

The basic unit of logic on the ispLSI 1048C/883 device is
the Generic Logic Block (GLB). The GLBs are labeled A0,
A1 .. F7 in figure 1. There are a total of 48 GLBs in the
ispLSI 1048C/883 devices. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.

Features

· HIGH-DENSITY PROGRAMMABLE LOGIC

-- 8000 PLD Gates
-- 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output

Enables

-- 288 Registers
-- High-Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

-- Small Logic Block Size for Random Logic
-- Security Cell Prevents Unauthorized Copying

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 50 MHz Maximum Operating Frequency

pd = 22 ns Propagation Delay

-- TTL Compatible Inputs and Outputs
-- Electrically Erasable and Reprogrammable
-- Non-Volatile E

CMOS

Technology

-- 100% Tested at Time of Manufacture

· IN-SYSTEM PROGRAMMABLE

-- In-System ProgrammableTM (ISPTM) 5-Volt Only
-- Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

-- Reprogram Soldered Devices for Faster Debugging

· COMBINES EASE OF USE AND THE FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEX-

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

-- Complete Programmable Device Can Combine Glue

Logic and Structured Designs

-- Four Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global
Interconnectivity

· ispDesignEXPERTTM LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

September 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications

ispLSI 1048C/883

The device also has a 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs have
selectable polarity, active high or active low. The signal
voltage levels are TTL-compatible, and the output drivers
can source 4 mA or sink 8 mA.

Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock as
shown in figure 1. The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1048C/883 device contains six Megablocks.

The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 1048C/883 device are selected
using the Clock Distribution Network. Four dedicated
clock pins (Y0, Y1, Y2 and Y3) are brought into the
distribution network, and five clock outputs (CLK 0, CLK
1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route
clocks to the GLBs and I/O cells. The Clock Distribution
Network can also be driven from a special clock GLB (D0
on the ispLSI 1048C/883 device). The logic of this GLB
allows the user to create an internal clock from a combi-
nation of internal signals.

Functional Block Diagram

Figure 1. ispLSI 1048C/883 Functional Block Diagram

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

Generic

Logic Blocks

(GLBs)

Megablock

Input Bus

Global

Routing

Pool

(GRP)

CLK 0

CLK 1
CLK 2
IOCLK 0
IOCLK 1

Clock

Distribution

Network

Output Routing Pool (ORP)

I/O

IN
11

I/O

IN
10

I/O

SDO/

IN3

Y
0

Y
1

Y
2

Y
3

I/O

SCLK/

IN 5

IN 7
IN 6

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58
I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

I/O 0
I/O 1

I/O 2

I/O 3

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13
I/O 14

I/O 15

SDI/IN 0

MODE/IN 1

I/O 4

I/O 5

ispEN

RESET

Input Bus

lnput Bus

0139F(2)-48B-isp

GOE0

GOE1

IN2

Specifications

ispLSI 1048C/883

Absolute Maximum Ratings

Supply Voltage V

................................... -0.5 to +7.0V

Input Voltage Applied ........................ -2.5 to V

+1.0V

Off-State Output Voltage Applied ..... -2.5 to V

+1.0V

Storage Temperature ................................ -65 to 150

Case Temp. with Power Applied .............. -55 to 125

Max. Junction Temp. (T

) with Power Applied ... 150

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

PARAMETER

SYMBOL

MIN.

MAX.

UNITS

5.5

0.8

Vcc + 1

Supply Voltage

0005A mil.eps

4.5

2.0

Military/883

= -55

C to +125

Input Low Voltage

Input High Voltage

Capacitance (T

=25

C, f=1.0 MHz)

SYMBOL

PARAMETER

MAXIMUM

UNITS

TEST CONDITIONS

=5.0V, V

=2.0V

I/O and Clock Capacitance

=5.0V, V

I/O

, V

=2.0V

1. Characterized but not 100% tested.

Table 2- 0006mil

Dedicated Input Capacitance

Data Retention Specifications

Table 2- 0008B

PARAMETER

Data Retention

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10000

Years

Cycles

Specifications

ispLSI 1048C/883

Switching Test Conditions

DC Electrical Characteristics

Over Recommended Operating Conditions

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Time

3ns 10% to 90%

Input Timing Reference Levels

1.5V

Output Timing Reference Levels

1.5V

Output Load

See figure 2

3-state levels are measured 0.5V from steady-state
active level.

Table 2- 0003

Output Load Conditions (see figure 2)

Test Condition

470

390

35pF

Active High

390

35pF

Active Low

470

390

35pF

Active High to Z

390

5pF

at V

- 0.5V

Active Low to Z

470

390

5pF

at V

+ 0.5V

Table 2- 0004A

Figure 2. Test Load

+ 5V

Device
Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

0.4

-10

-150

-200

260

IL-isp

IL-PU

2,4

=8 mA

=-4 mA

(MAX.)

3.5V

(MAX.)

= 5V, V

OUT

= 0.5V

= 0.5V, V

= 3.0V

TOGGLE

= 1 MHz

165

2.4

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

Output Low Voltage

Output High Voltage

Input or I/O Low Leakage Current

Input or I/O High Leakage Current

isp Input Low Leakage Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

UNITS

TYP.

1. One output at a time for a maximum duration of one second. V

out

= 0.5V was selected to avoid test problems by tester ground

degradation. Characterized but not 100% tested.

2. Measured using twelve 16-bit counters.
3. Typical values are at V

= 5V and T

= 25

4. Maximum I

varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-

tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
I

0007A-48C mil

Specifications

ispLSI 1048C/883

External Timing Parameters

Over Recommended Operating Conditions

pd1

pd2

max (Int.)

max (Ext.)

max (Tog.)

su1

co1

su2

co2

rw1

ptoeen

ptoedis

goeen

goedis

su3

Data Propagation Delay, 4PT bypass, ORP bypass

Data Propagation Delay

Clock Frequency with Internal Feedback

Clock Frequency with External Feedback

Clock Frequency, Max Toggle

GLB Reg. Setup Time before Clock, 4PT bypass

GLB Reg. Clock to Output Delay, ORP bypass

GLB Reg. Hold Time after Clock, 4 PT bypass

GLB Reg. Setup Time before Clock

GLB Reg. Clock to Output Delay

GLB Reg. Hold Time after Clock

Ext. Reset Pin to Output Delay

Ext. Reset Pulse Duration

Input to Output Enable

Input to Output Disable

Global OE Output Enable

Global OE Output Disable

Ext. Sync. Clock Pulse Duration, High

Ext. Sync. Clock Pulse Duration, Low

I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)

I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

DESCRIPTION

PARAMETER

-50

MAX.

22.0

26.0

14.0

16.0

20.5

27.5

20.5

MHz

MIN.

UNITS

Table 2- 0030-48C/50 mil

50.3

34.5

58.8

13.0

15.0

13.5

8.5

3.0

9.0

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. Reference Switching Test Conditions section.

( )

twh + tw1

( )

tsu2 + tco1

TEST

COND.

Specifications

ispLSI 1048C/883

Internal Timing Parameters

4.3

5.5

4.6

5.1

7.4

6.2

6.7

8.0

10.5

22.7

5.5

6.7

7.5

8.9

1.2

2.3

2.8

11.1

9.6

8.2

3.4

1.4

9.1

0.3

3.9

7.3

3.4

iobp

iolat

iosu

ioh

ioco

ior

din

grp1

grp4

grp8

grp16

grp48

4ptbp

1ptxor

20ptxor

xoradj

gbp

gsu

gco

gro

ptre

ptoe

ptck

orp

orpbp

MIN. MAX.

DESCRIPTION

PARAMETER

UNITS

-50

Inputs

I/O Register Bypass

I/O Latch Delay

I/O Register Setup Time before Clock

I/O Register Hold Time after Clock

I/O Register Clock to Out Delay

I/O Register Reset to Out Delay

Dedicated Input Delay

GRP Delay, 1 GLB Load

GRP Delay, 4 GLB Loads

GRP Delay, 8 GLB Loads

GRP Delay, 16 GLB Loads

GRP Delay, 48 GLB Loads

4 Product Term Bypass Path Delay

1 Product Term/XOR Path Delay

20 Product Term/XOR Path Delay

XOR Adjacent Path Delay

GLB Register Bypass Delay

GLB Register Setup Time before Clock

GLB Register Hold Time after Clock

GLB Register Clock to Output Delay

GLB Register Reset to Output Delay

GLB Product Term Reset to Register Delay

GLB Product Term Output Enable to I/O Cell Delay

GLB Product Term Clock Delay

ORP Delay

ORP Bypass Delay

GRP

GLB

ORP

Table 2- 0036-48C/50MIL

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.

Specifications

ispLSI 1048C/883

Output Buffer Delay

I/O Cell OE to Output Enabled

I/O Cell OE to Output Disabled

Global OE

Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

Clock Delay, Y1 or Y2 to Global GLB Clock Line

Clock Delay, Clock GLB to Global GLB Clock Line

Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

Clock Delay, Clock GLB to I/O Cell Global Clock Line

Global Reset to GLB and I/O Registers

7.4

6.1

2.6

6.1

2.6

oen

odis

goe

gy0

gy1/2

gcp

ioy2/3

iocp

2.9

6.9

13.6

7.4

8.7

7.6

8.7

7.6

11.4

MIN. MAX.

DESCRIPTION

PARAMETER

UNITS

-50

Outputs

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.

Global Reset

Table 2- 0037-48C/50mil

Clocks

Internal Timing Parameters

Specifications

ispLSI 1048C/883

ispLSI 1048C/883 Timing Model

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

4 PT Bypass

20 PT

XOR Delays

Control
PTs

GRP

Delay

Input

Clock

Distribution

I/O Pin

(Input)

Y1,2,3

GRP 4

GLB Reg Bypass

ORP Bypass

RST

I/O Reg Bypass

I/O Cell

ORP

GLB

GRP

I/O Cell

#25 - 29

#32

#36

#37, 38, 39

#55, 56,

57, 58

#45, 46,

#54

#48

#49

Reset

Ded. In

#30

#24

RST

#59

#40

#41, 42,

43, 44

#51, 52

#50

GOE0, 1

0491A/48

#53

#31, 33,

34, 35

Derivations of

su,

h and

co from the Product Term Clock

= Logic + Reg su - Clock (min)
=

iobp +

grp4 +

20ptxor

)

gsu

) - (t

iobp +

grp4 +

ptck(min)

)

(

#24 + #32 + #38

)

(

#41

) - (

#24 + #32 + #47

)

8.0 ns = (4.3 + 6.7 + 7.5) + (3.9) - (4.3 + 6.7 + 3.4)

= Clock (max) + Reg h - Logic
=

iobp +

grp4 +

ptck(max)

)

) - (t

iobp +

grp4 +

20ptxor

)

(

#24 + #32 + #47

)

(

#42

) - (

#24 + #32 + #38

)

8.0 ns = (4.3 + 6.7 + 8.2) + (7.3) - (4.3 + 6.7 + 7.5)

= Clock (max) + Reg co + Output
=

iobp +

grp4 +

ptck(max)

)

gco

)

orp +

)

(

#24 + #32 + #47

)

(

#43

)

(

#48 + #50

)

32.8 ns = (4.3 + 6.7 + 8.2) + (7.3) + (3.4 + 2.9)

Derivations of

su,

h and

co from the Clock GLB

= Logic + Reg su - Clock (min)
=

iobp +

grp4 +

20ptxor

)

gsu

) - (t

gy0(min) +

gco +

gcp(min)

)

(

#24 + #32 + #38

)

(

#41

) - (

#54 + #43 + #56

)

10.1 ns= (4.3 + 6.7 + 7.5) + (3.9) - (7.4 + 2.3 + 2.6)

= Clock (max) + Reg h - Logic
=

gy0(max) +

gco +

gcp(max)

)

) - (t

iobp +

grp4 +

20ptxor

)

(

#54 + #43 + #56

)

(

#42

) - (

#24 + #32 + #38

)

6.1 ns = (7.4 + 2.3 + 7.6) + (7.3) - (4.3 + 6.7 + 7.5)

= Clock (max) + Reg co + Output
=

gy0(max) +

gco +

gcp(max)

)

gco

)

orp +

)

(

#54 + #43 + #56

)

(

#43

)

(

#48 + #50

)

30.9 ns = (7.4 + 2.3 + 7.6) + (7.3) + (3.4 + 2.9)

1. Calculations are based upon timing specifications for the ispLSI 1048C-50

Specifications

ispLSI 1048C/883

Maximum GRP Delay vs GLB Loads

GLB Loads

GRP Dela

(ns)

ispLSI 1048C-50

0126A-48C-80-ispmil

Power Consumption

Power consumption in the ispLSI 1048C/883 device
depends on two primary factors: the speed at which the
device is operating, and the number of Product Terms

Figure 3. Typical Device Power Consumption vs fmax

used. Figure 3 shows the relationship between power
and operating speed.

100

150

200

250

max (MHz)

CC (mA)

Notes: Configuration of Twelve 16-bit Counters
Typical Current at 5V, 25°C

ispLSI 1048C

0127A-48C-80-isp

ICC can be estimated for the ispLSI 1048C using the following equation:

ICC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device

The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.

Specifications

ispLSI 1048C/883

GND

B2,

B8, B13,

C8,

H3, H12,

M8,

N2,

VCC

C7, G2,

G3, G12, G13,

M7,

I/O 0 - I/O 5

J2,

J3,

K1,

L1,

K2,

M1,

I/O 6 - I/O 11

L2,

K3,

N1,

M2,

L3,

P1,

I/O 12 - I/O 17

M3,

P2,

N3,

M4,

P3,

N4,

I/O 18 - I/O 23

P4,

M5,

N5, P5,

M6,

N6,

I/O 24 - I/O 29

N9,

M9, P10, P11, N10, P12,

I/O 30 - I/O 35

N11, M10, P13, N12, M11, P14,

I/O 36 - I/O 41

M12, N14, M13, L12, M14, L13,

I/O 42 - I/O 47

L14, K12, K13, K14, J12, J13,

I/O 48 - I/O 53

F13, F12, E14, D14, E13, C14,

I/O 54 - I/O 59

D13, E12, B14, C13, D12, A14,

I/O 60 - I/O 65

C12, A13, B12, C11, A12, B11,

I/O 66 - I/O 71

A11, C10, B10, A10,

C9,

B9,

I/O 72 - I/O 77

B6,

C6,

A5,

A4,

B5,

A3,

I/O 78 - I/O 83

B4,

C5,

A2,

B3,

C4,

A1,

I/O 84 - I/O 89

C3,

B1,

C2,

D3,

C1,

D2,

I/O 90 - I/O 95

D1,

E3,

E2,

E1,

F3,

RESET

G14

H13

H14

IN 2, IN 4

P7,

IN 6 - IN 11

F14,

A9,

A8,

A7,

A6,

GOE0, GOE1

N13,

B7,

Input Dedicated in-system programming enable input pin. This
pin is brought low to enable the programming mode. The MODE,
SDI, SDO and SCLK options become active.

Input This pin performs two functions. It is a dedicated input pin
when

ispEN

is logic high. When

ispEN

is logic low, it functions as

an input pin to load programming data into the device. SDI/IN 0
also is used as one of the two control pins for the isp state machine.

Input This pin performs two functions. It is a dedicated input pin
when

ispEN

is logic high. When

ispEN

is logic low, it functions as

a pin to control the operation of the isp state machine.

Input/Output This pin performs two functions. It is a dedicated
input pin when

ispEN

is logic high. When

ispEN

is logic low, it

functions as an output pin to read serial shift register data.

Input This pin performs two functions. It is a dedicated input
when

ispEN

is logic high. When

ispEN

is logic low, it functions as

a clock pin for the Serial Shift Register.

Input/Output Pins - These are the general purpose I/O pins used
by the logic array.

Ground (GND)

Active Low (0) Reset pin which resets all of the GLB and I/O
registers in the device.

Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.

Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on
the device.

Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/
or any I/O cell on the device.

Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on
the device.

Dedicated input pins to the device.

Global output enables for all I/Os.

Table 2- 0002C-48C/CPGA

DESCRIPTION

NAME

CPGA PIN NUMBERS

ispEN

SDI/IN 0

MODE/IN 1

SDO/IN 3

SCLK/IN 5

J14

1. Pins have dual function capability.

Pin Description

Specifications

ispLSI 1048C/883

Pin Configuration

ispLSI 1048C/883 133-Pin CPGA Pinout Diagram

I/O59

I/O56

I/O53

I/O51

I/O50

IN6

I/O40

I/O37

I/O35

I/O61

GND

I/O57

I/O54

I/O52

I/O48

Vcc

I/O38

GOE0

I/O32

I/O64

I/O62

I/O55

I/O49

Vcc

I/O33

I/O29

IN8

GND

SDO/

IN31

IN9

GOE1

Vcc

IN2

IN10

I/O72

I/O73

I/O22

I/O23

MODE/

IN11

I/O74

I/O76

I/O79

I/O19

I/O20

I/O21

I/O75

I/O78

I/O17

I/O18

I/O77

I/O81

I/O84

I/O91

I/O94

Vcc

I/O14

I/O16

I/O80

GND

I/O86

I/O89

I/O92

I/O95

Vcc

I/O9

GND

I/O13

I/O83

I/O85

I/O88

I/O90

I/O93

IN11

I/O5

I/O8

I/O11

ispLSI 1048C/883

Bottom View

14 13 12 11 10 9 8 7 6 5 4 3 2 1

PIN A1

133 CPGA Pinout.eps

I/O66

I/O65

I/O69

I/O68

IN7

I/O71

I/O30

I/O27

I/O28

I/O26

I/O24

IN4

I/O15

I/O12

I/O67

I/O70

GND

I/O60

I/O63

I/O82

I/O87

I/O58

GND

I/O1

I/O7

I/O10

I/O0

I/O4

I/O6

SDI/

IN01

I/O2

I/O3

SCLK/

IN51

I/O45

I/O42

I/O47

I/O44

I/O41

I/O46

I/O43

I/O39

I/O36

I/O34

I/O31

I/O25

GND

INDEX

GND

RESET

ispEN

1. Pins have dual function capability.

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 1048C

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 1048C

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 1048C