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Электронный компонент: 2096VE

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ispLSI
2096VE
3.3V In-System Programmable
SuperFASTTM High Density PLD
2096ve_05
1
Features
SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
-- 4000 PLD Gates
-- 96 I/O Pins, Six Dedicated Inputs
-- 96 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
-- Small Logic Block Size for Random Logic
-- 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2096V Devices
-- Pinout Compatible with ispLSI 2192VE
3.3V LOW VOLTAGE 2096 ARCHITECTURE
-- Interfaces with Standard 5V TTL Devices
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
--
f
max = 250MHz* Maximum Operating Frequency
--
t
pd = 4.0ns* Propagation Delay
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture
-- Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
-- 3.3V In-System Programmability (ISPTM) Using
Boundary Scan Test Access Port (TAP)
-- Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
-- Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
-- Reprogram Soldered Devices for Faster Prototyping
100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERTTM LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZERTM
-- PC and UNIX Platforms
*Advanced Information
Description
The ispLSI 2096VE is a High Density Programmable
Logic Device containing 96 Registers, six Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2096VE
features in-system programmability through the Bound-
ary Scan Test Access Port (TAP) and is 100% IEEE
1149.1 Boundary Scan Testable. The ispLSI 2096VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
The basic unit of logic on the ispLSI 2096VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
Global Routing Pool
(GRP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0919/2096VE
C7
C4
C5
C6
A4
A7
A6
A5
GLB
Logic
Array
D Q
D Q
D Q
D Q
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C3
C0
C1
C2
B0
B3
B2
B1
Output Routing Pool (ORP)
Output Routing Pool (ORP)
B7
B6
B4
B5
A0
A1
A3
A2
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
September 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Functional Block Diagram
Specifications
ispLSI 2096VE
2
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 5V signal levels to
support mixed-voltage systems.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096VE device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
A0
A3
A1
A2
B7
B4
B6
B5
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
I/O 95
I/O 94
I/O 93
I/O 92
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
TDO/IN 2
TCK/IN 3
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
Y0
Y1
Y2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
TDI/IN 0
TMS/IN 1
RESET
BSCAN
GOE 1
GOE 0
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
Input Bus
0917/2096VE
Megablock
C7
C6
C5
C4
A4
A5
A6
A7
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
B0
B1
B2
B3
Output Routing Pool (ORP)
C3
C2
C1
C0
Output Routing Pool (ORP)
Input Bus
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
IN 5
IN 4
Generic Logic
Blocks (GLBs)
Functional Block Diagram
Figure 1. ispLSI 2096VE Functional Block Diagram
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096VE are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Specifications
ispLSI 2096VE
3
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150
C
Case Temp. with Power Applied .............. -55 to 125
C
Max. Junction Temp. (T
J
) with Power Applied ... 150
C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
Table 2-0008/2096VE
PARAMETER
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
10000
Cycles
C
SYMBOL
Table 2-0006/2096VE
C
PARAMETER
I/O Capacitance
6
UNITS
TYPICAL
TEST CONDITIONS
1
2
8
Dedicated Input Capacitance
pf
pf
V = 3.3V, V = 0.0V
V = 3.3V, V = 0.0V
CC
CC
I/O
IN
C
Clock and Global Output Enable Capacitance
10
3
pf
V = 3.3V, V = 0.0V
CC
Y
T
A
= 0
C to + 70
C
T
A
= -40
C to + 85
C
SYMBOL
Table 2-0005/2096VE
V
CC
V
IH
V
IL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN.
MAX.
UNITS
3.0
3.0
2.0
V 0.5
3.6
3.6
5.25
0.8
V
V
V
V
SS
Commercial
Industrial
DC Recommended Operating Condition
Capacitance (T
A
=25
C, f=1.0 MHz)
Erase Reprogram Specifications
Specifications
ispLSI 2096VE
4
Input Pulse Levels
Table 2-0003/2096VE
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5ns 10% to 90%
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
TEST CONDITION
R1
R2
CL
A
316
348
35pF
B
348
35pF
316
348
35pF
Active High
Active Low
C
316
348
5pF
348
5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004/2096VE
V
OL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at V = 3.3V and T = 25
C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .
Table 2-0007A/2096VE
1
V
OH
I
IH
I
IL
I
IL-isp
PARAMETER
I
IL-PU
I
OS
2, 4
I
CC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
BSCAN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
0V
V
V (Max.)
0V
V
V
0V
V
V
V = 3.3V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN
IL
IN IL
CC OUT
CLOCK
IL
IH
CONDITION
MIN.
TYP.
MAX.
UNITS
3
2.4
125
0.4
10
10
-10
-150
-150
-100
V
V
A
A
A
A
A
mA
mA
CC
A
OUT
CC
CC
(V 0.2)V
V
V
V
V
5.25V
IN
CC
CC
IN
CC
+ 3.3V
R1
R2
CL
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213A/2096VE
Figure 2. Test Load
Switching Test Conditions
Output Load Conditions (see Figure 2)
DC Electrical Characteristics
Over Recommended Operating Conditions
Specifications
ispLSI 2096VE
5
A
D
V
A
N
C
E
D
IN
F
O
R
M
A
T
IO
N
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2096VE
1
3
2
1
tsu2 + tco1
( )
DESCRIPTION
#
PARAMETER
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
ns
t
pd2
A
2
Data Propagation Delay
ns
f
max
A
3
Clock Frequency with Internal Feedback
MHz
f
max (Ext.)
--
4
Clock Frequency with External Feedback
MHz
f
max (Tog.)
--
5
Clock Frequency, Max. Toggle
MHz
t
su1
--
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
ns
t
co1
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
ns
t
h1
--
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
ns
t
su2
--
9
GLB Reg. Setup Time before Clock
ns
t
co2
A
10
GLB Reg. Clock to Output Delay
ns
t
h2
--
11
GLB Reg. Hold Time after Clock
ns
t
r1
A
12
Ext. Reset Pin to Output Delay
ns
t
rw1
--
13
Ext. Reset Pulse Duration
ns
t
ptoeen
B
14
Input to Output Enable
ns
t
ptoedis
C
15
Input to Output Disable
ns
t
goeen
B
16
Global OE Output Enable
ns
t
goedis
C
17
Global OE Output Disable
ns
t
wh
--
18
External Synchronous Clock Pulse Duration, High
ns
t
wl
--
19
External Synchronous Clock Pulse Duration, Low
ns
-250
MIN. MAX.
--
4.0
--
250
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-200
MIN. MAX.
--
4.5
--
200
--
--
--
--
--
0.0
4.0
--
0.0
--
4.0
--
--
--
--
2.5
--
2.5
--
133
200
3.0
3.5
--
--
4.5
--
6.0
--
8.0
8.0
5.0
5.0
7.0