ispLSI

2096VL

2.5V In-System Programmable

SuperFASTTM High Density PLD

2096vl_02

Features

· SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC

-- 4000 PLD Gates
-- 96 I/O Pins, Six Dedicated Inputs
-- 96 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

-- Small Logic Block Size for Random Logic
-- 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2096V and 2096VE Devices

· 2.5V LOW VOLTAGE 2096 ARCHITECTURE

-- Interfaces with Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)

-- 85 mA Typical Active Current

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 165 MHz Maximum Operating Frequency

pd = 5.5 ns Propagation Delay

-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture
-- Unused Product Term Shutdown Saves Power

· IN-SYSTEM PROGRAMMABLE

-- 2.5V In-System Programmability (ISPTM) Using

Boundary Scan Test Access Port (TAP)

-- Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic

-- Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

-- Reprogram Soldered Devices for Faster Prototyping

· 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

· THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global

Interconnectivity

· ispDesignEXPERTTM LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

Description

The ispLSI 2096VL is a High Density Programmable
Logic Device containing 96 Registers, six Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2096VL fea-
tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2096VL offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2096VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control, and
the output drivers can source 4 mA or sink 8 mA. Each
output can be programmed independently for fast or slow
output slew rate to minimize overall output switching

Global Routing Pool

(GRP)

Output Routing Pool (ORP)

0919/2096VL

GLB

Logic
Array

D Q

Output Routing Pool (ORP)

Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

September 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Functional Block Diagram

Specifications

ispLSI 2096VL

noise. Device pins can be safely driven to 3.3V signal
levels to support mixed-voltage systems.

Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096VL device contains three Megablocks.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 2096VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.

Output Routing Pool (ORP)

Input Bus

Global

Routing

Pool

(GRP)

CLK 0

CLK 1

CLK 2

I/O 95

I/O 94

I/O 93

I/O 92

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 32

I/O 33

I/O 34

I/O 35

TDO/IN 2

TCK/IN 3

I/O 36

I/O 37

I/O 38

I/O 39

I/O 40

I/O 41

I/O 42

I/O 43

I/O 44

I/O 45

I/O 46

I/O 47

I/O 0
I/O 1
I/O 2
I/O 3

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8
I/O 9

I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

I/O 63
I/O 62
I/O 61
I/O 60

I/O 59
I/O 58
I/O 57
I/O 56

I/O 55
I/O 54
I/O 53
I/O 52

I/O 51
I/O 50
I/O 49
I/O 48

TDI/IN 0

TMS/IN 1

RESET

BSCAN

GOE 1

GOE 0

I/O 91

I/O 90

I/O 89

I/O 88

I/O 87

I/O 86

I/O 85

I/O 84

I/O 83

I/O 82

I/O 81

I/O 80

Input Bus

0917/2096VL

Megablock

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

Input Bus

I/O 79

I/O 78

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

IN 5

IN 4

Generic Logic

Blocks (GLBs)

Functional Block Diagram

Figure 1. ispLSI 2096VL Functional Block Diagram

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2096VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.

Specifications

ispLSI 2096VL

Absolute Maximum Ratings

Supply Voltage V

................................ -0.5 to +4.05V

Input Voltage Applied ............................. -0.5 to +4.05V

Off-State Output Voltage Applied .......... -0.5 to +4.05V

Storage Temperature ................................ -65 to 150

Case Temp. with Power Applied .............. -55 to 125

Max. Junction Temp. (T

) with Power Applied ... 150

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

Table 2-0008/2096VL

PARAMETER

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10,000

Cycles

SYMBOL

Table 2-0006/2096VL

PARAMETER

I/O Capacitance

UNITS

TYPICAL

TEST CONDITIONS

Dedicated Input Capacitance

V = 2.5V, V = 0.0V

I/O

Clock and Global Output Enable Capacitance

V = 2.5V, V = 0.0V

= 0

C to + 70

= -40

C to + 85

SYMBOL

Table 2-0005/2096VL

PARAMETER

Supply Voltage

Input High Voltage

Input Low Voltage

MIN.

MAX.

UNITS

2.3

1.7

-0.3

2.7

3.6

0.7

Commercial

Industrial

DC Recommended Operating Condition

Capacitance (T

=25

C, f=1.0 MHz)

Erase Reprogram Specifications

Specifications

ispLSI 2096VL

Input Pulse Levels

Table 2-0003/2096VL

Input Rise and Fall Time

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to V

1.5ns 10% to 90%

See Figure 2

3-state levels are measured 0.15V from
steady-state active level.

TEST CONDITION

250

218

35pF

218

35pF

250

35pF

Active High

Active Low

250

5pF

218

5pF

Active Low to Z
at V +0.15V

Active High to Z
at V -0.15V

Table 2-0004/2096VL

Device
Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

0213A/2096VL

Figure 2. Test Load

Switching Test Conditions

Output Load Conditions (see Figure 2)

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

1. One output at a time for a maximum duration of one second. V

OUT

= 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at V

= 2.5V and T

= 25

4. Maximum I

varies widely with specific device configuration and operating frequency. Refer to Power Consumption

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I

5. With no pull-up resistors.

Table 2-0007/2096VL

IL-isp

PARAMETER

IL-PU

2, 4

Output Low Voltage

Output High Voltage

Input or I/O High Leakage Current

Input or I/O Low Leakage Current

BSCAN

Input Pull-Up Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

= 100

V (Max.)

V = 2.5V, V = 0.5V

V = 0.0V, V = 2.5V

f = 1 MHz

IN IL

CC OUT

CLK

IL IH

CONDITION

MIN.

TYP.

MAX.

UNITS

2.0

0.2

-10

-150

-100

(min)

3.6V

= 8mA

= -1mA

- 0.2

= -100

1.8

= -4mA

0.4

Specifications

ispLSI 2096VL

External Timing Parameters

Over Recommended Operating Conditions

pd1

UNITS

-135

MIN.

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.

Table 2-0030/2096VL

1
tsu2 + tco1

( )

-100

MIN.

MAX.

DESCRIPTION

PARAMETER

Data Propagation Delay, 4PT Bypass, ORP Bypass

7.5

10.0

pd2

Data Propagation Delay

max

Clock Frequency with Internal Feedback

135

100

MHz

max (Ext.)

Clock Frequency with External Feedback

MHz

max (Tog.)

Clock Frequency, Max. Toggle

MHz

su1

GLB Reg. Setup Time before Clock, 4 PT Bypass

co1

GLB Reg. Clock to Output Delay, ORP Bypass

GLB Reg. Hold Time after Clock, 4 PT Bypass

0.0

su2

GLB Reg. Setup Time before Clock

6.0

co2

GLB Reg. Clock to Output Delay

GLB Reg. Hold Time after Clock

0.0

Ext. Reset Pin to Output Delay, ORP Bypass

rw1

Ext. Reset Pulse Duration

5.5

ptoeen

Input to Output Enable

ptoedis

Input to Output Disable

goeen

Global OE Output Enable

goedis

Global OE Output Disable

External Synchronous Clock Pulse Duration, High

3.5

External Synchronous Clock Pulse Duration, Low

3.5

143

5.0

4.5

5.5

8.0

12.0

7.0

10.0

100

6.5

0.0

8.0

0.0

6.5

5.0

13.0

5.0

6.0

13.5

15.0

9.0

-165

MIN. MAX.

5.5

165

0.0

4.5

0.0

5.0

3.0

118

166

3.5

4.0

5.0

6.0

10.0

6.0

8.0

Specifications

ispLSI 2096VL

Internal Timing Parameters

Over Recommended Operating Conditions

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.

Table 2-0036/2096VL

Inputs

UNITS

-135

-165

MIN.

-100

MIN.

MAX.

MIN. MAX.

MAX.

DESCRIPTION

PARAMETER

20 Input Buffer Delay

din

21 Dedicated Input Delay

grp

22 GRP Delay

GLB

1ptxor

25 1 Product Term/XOR Path Delay

20ptxor

26 20 Product Term/XOR Path Delay

xoradj

27 XOR Adjacent Path Delay

gbp

28 GLB Register Bypass Delay

gsu

29 GLB Register Setup Time before Clock

30 GLB Register Hold Time after Clock

gco

31 GLB Register Clock to Output Delay

gro

32 GLB Register Reset to Output Delay

ptre

33 GLB Product Term Reset to Register Delay

ptoe

34 GLB Product Term Output Enable to I/O Cell Delay

ptck

35 GLB Product Term Clock Delay

ORP

38 Output Buffer Delay

39 Output Slew Limited Delay Adder

GRP

4ptbpc

23 4 Product Term Bypass Path Delay (Combinatorial)

4ptbpr

24 4 Product Term Bypass Path Delay (Registered)

orp

36 ORP Delay

orpbp

37 ORP Bypass Delay

Outputs

oen

40 I/O Cell OE to Output Enabled

odis

41 I/O Cell OE to Output Disabled

goe

42 Global Output Enable

gy0

43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

gy1/2

44 Clock Delay, Y1 or Y2 to Global GLB Clock Line

Clocks

45 Global Reset to GLB

0.5

1.6

1.1

3.4

0.0

0.3

0.6

4.8

4.9

4.1

1.6

2.0

1.9

2.4

1.4

0.4

3.5

2.5

1.7

1.9

3.4

1.2

2.3

1.1

1.7

1.9

1.0

2.2

1.2

4.2

0.5

0.3

1.1

6.6

5.8

4.5

1.6

2.0

3.2

1.5

0.5

4.0

3.0

2.1

2.3

4.8

1.7

3.3

2.1

2.3

0.9

2.7

1.8

6.2

1.0

0.3

4.3

8.9

7.4

4.8

1.6

2.0

5.2

4.7

1.5

0.5

4.9

4.1

2.6

2.8

7.1

1.7

4.8

2.8

2.6

2.8

Global Reset

Specifications

ispLSI 2096VL

ispLSI 2096VL Timing Model

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

Reg 4 PT Bypass

20 PT

XOR Delays

Control
PTs

I/O Pin

(Input)

Y0,1,2

GRP

GLB Reg Bypass

ORP Bypass

RST

I/O Delay

I/O Cell

ORP

GLB

GRP

I/O Cell

#24

#25, 26, 27

#33, 34,

#43, 44

#36

Reset

Ded. In

#21

#20

#28

#29, 30,

31, 32

#38,

GOE 0

#42

#40, 41

0491/2032

#22

Comb 4 PT Bypass #23

#37

#45

Derivations of

su,

h and

co from the Product Term Clock

=
=
=
=

Logic + Reg su - Clock (min)
(

io +

grp +

20ptxor) + (

gsu) - (

io +

grp +

ptck(min))

(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 1.1 + 3.4) + (1.2) - (0.5 + 1.1 + 1.1)

=
=
=
=

Clock (max) + Reg h - Logic
(

io +

grp +

ptck(max)) + (

gh) - (

io +

grp +

20ptxor)

(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 1.1 + 4.1) + (2.3) - (0.5 + 1.1 + 3.4)

=
=
=
=

Clock (max) + Reg co + Output
(

io +

grp +

ptck(max)) + (

gco) + (

orp +

ob)

(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 1.1 + 4.1) + (0.3) + (1.4 + 1.6)

Table 2-0042/2096VL

Note: Calculations are based on timing specifications for the ispLSI 2096VL-165L.

3.5ns

3.0ns

9.0ns

Specifications

ispLSI 2096VL

Power Consumption

Power consumption in the ispLSI 2096VL device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms

used. Figure 3 shows the relationship between power
and operating speed.

Figure 3. Typical Device Power Consumption vs fmax

0127/2096VL

ICC can be estimated for the ispLSI 2096VL using the following equation:

ICC (mA) = 8.0 + (# of PTs * 0.41) + (# of Nets * Max Freq * 0.0026)

Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)

The ICC estimate is based on typical conditions (VCC = 2.5V, room temperature) and an assumption of two

GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to

operating conditions and the program in the device, the actual ICC should be verified.

Notes: Configuration of six 16-bit counters

Typical current at 2.5V, 25

100

120

150

180

max (MHz)

CC (mA)

120

140

ispLSI 2096VL

Specifications

ispLSI 2096VL

Pin Description

Input/Output Pins - These are the general purpose I/O pins used by the
logic array.

NAME

Table 2-0002-2096VL

TQFP PIN NUMBERS

DESCRIPTION

21,
27,
35,
41,
51,
57,
64,
71,
85,
91,
99,

105,
115,
121,
128,

112

22,
28,
36,
42,
52,
58,
65,
72,
86,
92,

100,
106,
116,
122,

1,
8,

80,

23,
29,
37,
43,
53,
59,
67,
73,
87,
93,

101,
107,
117,
123,

3,
9,

I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95

24,
30,
38,
44,
54,
60,
68,
74,
88,
94,

102,
108,
118,
124,

10,

25,
32,
39,
45,
55,
61,
69,
75,
89,
96,

103,
109,
119,
125,

11,

26
33
40
46
56
62
70
76
90
97

104
110
120
126

18,

111,

34,

127

50,

63,

95,

16,

114

31,

47,

66,

81,

79,

98,

Global Output Enables input pins.

GOE 0, GOE 1

GND

VCC

Ground (GND)

Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.

Active Low (0) Reset pin which resets all of the registers in the device.

RESET

Y0, Y1, Y2

13,

49,

No Connect.

TDI/IN 0

BSCAN

TMS/IN 1

113

84,

83,

Dedicated input pins to the device.

IN 4, IN 5

TDO/IN 2

TCK/IN 3

Output/Input This pin performs two functions. When

BSCAN

is logic

low, it functions as an output pin to read serial shift register data. When

BSCAN

is high, it functions as a dedicated input pin.

Input Dedicated in-system programming Boundary Scan enable input
pin. This pin is brought low to enable the programming mode. The TMS,
TDI, TDO and TCK controls become active.

Input This pin performs two functions. When

BSCAN

is logic low, it

functions as a serial data input pin to load programming data into the
device. When

BSCAN

is high, it functions as a dedicated input pin.

Input This pin performs two functions. When

BSCAN

is logic low, it

functions as a mode control pin for the Boundary Scan state machine.
When

BSCAN

is high, it functions as a dedicated input pin.

Input This pin performs two functions. When

BSCAN

is logic low, it

functions as a clock pin for the Boundary Scan state machine. When

BSCAN

is high, it functions as a dedicated input pin.

1. NC pins are not to be connected to any active signal, VCC or GND.

Specifications

ispLSI 2096VL

Pin Configuration

ispLSI 2096VL 128-Pin TQFP Pinout Diagram

VCC

I/O 85

I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95

RESET

VCC

GOE 1

GND

BSCAN

I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9

VCC
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 4
Y1
NC

VCC
GOE 0

Y2
TCK/IN 3
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
VCC

I/O 84

GND

I/O 83

I/O 82

I/O 81

I/O 80

I/O 79

I/O 78

I/O 77

I/O 76

I/O 75

I/O 74

I/O 73

I/O 72

IN 5

GND

I/O 71

I/O 70

I/O 69

I/O 68

I/O 67

I/O 66

I/O 65

I/O 64

I/O 63

I/O 62

I/O 61

I/O 60

GND

I/O 59

I/O 10

GND

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

TMS/IN 1

GND

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 32

I/O 33

I/O 34

I/O 35

GND

ispLSI 2096VL

Top View

VCC

TDI/IN 0

I/O 58

TDO/IN 2

GND

I/O 37

I/O 11

VCC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

33 34

95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

128

127

126

125

124

123

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

122

I/O 36

VCC

1. NC pins are not to be connected to any active signals, VCC or GND.

0124-2096VL

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 2096VL

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 2096VL

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 2096VL