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Электронный компонент: 2128E

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ispLSI
2128E
In-System Programmable
SuperFASTTM High Density PLD
2128e_02
1
Features
SUPERFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
-- 6000 PLD Gates
-- 128 I/O Pins, Eight Dedicated Inputs
-- 128 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
-- Small Logic Block Size for Random Logic
-- 100% Functional/JEDEC Upward Compatible with
ispLSI 2128 Devices
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
--
f
max = 180 MHz Maximum Operating Frequency
--
t
pd = 5.0 ns Propagation Delay
-- TTL Compatible Inputs and Outputs
-- 5V Programmable Logic Core
-- ispJTAGTM In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
-- User-Selectable 3.3V or 5V I/O Supports Mixed-
Voltage Systems
-- PCI Compatible Outputs
-- Open-Drain Output Option
-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- Unused Product Term Shutdown Saves Power
ispLSI OFFERS THE FOLLOWING ADDED FEATURES
-- Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
-- Reprogram Soldered Devices for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
-- Complete Programmable Device Can Combine Glue
Logic and Structured Designs
-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control to
Minimize Switching Noise
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERTTM LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZERTM
-- PC and UNIX Platforms
Functional Block Diagram
Copyright 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
November 1998
Global Routing Pool (GRP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
CLK 0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
CLK 1
CLK 2
Logic
Array
GLB
D
Q
D
Q
D
Q
D
Q
0139(9A)/2128
C7
C6
C5
C4
C3
C2
C1
C0
D3
D2
D1
D0
D7
D6
D5
D4
B4
B5
B6
B7
B0
B1
B2
B3
A0
A1
A2
A3
A4
A5
A6
A7
Description
The ispLSI 2128E is a High Density Programmable Logic
Device. The device contains 128 Registers, 128 Univer-
sal I/O pins, eight Dedicated Input pins, three Dedicated
Clock Input pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2128E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2128E offers non-volatile reprogrammability of all logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2128E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
The device also has 128 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
Specifications
ispLSI 2128E
2
Functional Block Diagram
Figure 1. ispLSI 2128E Functional Block Diagram
Global
Routing
Pool
(GRP)
0139/2128E
Megablock
RESET
Input Bus
D3
D2
D1
D0
D7
D6
D5
D4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
I/O 127
I/O 126
I/O 125
I/O 124
I/O 123
I/O 122
I/O 121
I/O 120
I/O 119
I/O 118
I/O 117
I/O 116
I/O 115
I/O 114
I/O 113
I/O 112
I/O 111
I/O 110
I/O 109
I/O 108
I/O 107
I/O 106
I/O 105
I/O 104
I/O 103
I/O 102
I/O 101
I/O 100
I/O 99
I/O 98
I/O 97
I/O 96
TDI/IN 7
C7
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP)
O
utput Routing Pool (ORP)
Input Bus
IN 5
IN 4
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 95
I/O 94
I/O 93
I/O 92
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
CLK 0
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
Y0
Y1
Y2
IN 2
IN 3
B4
B5
B6
B7
B0
B1
B2
B3
Output Routing Pool (ORP)
O
utput Routing Pool (ORP)
A0
A1
A2
A3
A4
A5
A6
A7
BSCAN
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 0
I/O 1
I/O 2
I/O 3
GOE 0
GOE 1
CLK 1
CLK 2
Input Bus
TCK/ IN 0
TMS/IN 1
TDO/IN 6
Generic Logic
Blocks (GLBs)
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise. By
connecting the VCCIO pins to a common 5V or 3.3V
power supply, I/O output levels can be matched to 5V or
3.3V compatible voltages. When connected to a 5V
supply, the I/O pins provide PCI-compatible output drive.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2128E device contains four Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2128E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Specifications
ispLSI 2128E
3
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150
C
Case Temp. with Power Applied .............. -55 to 125
C
Max. Junction Temp. (T
J
) with Power Applied ... 150
C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
Capacitance (T
A
=25
C, f=1.0 MHz)
Erase/Reprogram Specification
T
A
= 0
C to +70
C
SYMBOL
Table 2-0005/2128E
V
CC
V
IH
V
IL
PARAMETER
Supply Voltage: Logic Core, Input Buffers
Input High Voltage
Input Low Voltage
MIN.
MAX.
UNITS
4.75
2.0
0
5.25
V
cc
+1
0.8
V
V
CCIO
Supply Voltage: Output Drivers
4.75
5.25
V
3.3V
5V
3.0
3.6
V
V
V
C
SYMBOL
Table 2-0006/2128E
C
PARAMETER
I/O Capacitance
UNITS
TEST CONDITIONS
1
2
Dedicated Input Capacitance
pf
pf
V = 5.0V, V = 2.0V
V = 5.0V, V = 2.0V
CC
CC
I/O
IN
C
Clock Capacitance
8
TYP
8
10
3
pf
V = 5.0V, V = 2.0V
CC
Y
Table 2-0008/2128E
PARAMETER
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
10,000
Cycles
Specifications
ispLSI 2128E
4
Switching Test Conditions
Figure 2. Test Load
TEST CONDITION
R1
R2
CL
A
470
390
35pF
B
390
35pF
470
390
35pF
Active High
Active Low
C
470
390
5pF
390
5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2 - 0004A/2000
Output Load Conditions (see Figure 2)
Input Pulse Levels
Table 2-0003/2128E
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
1.5 ns
V
OL
SYMBOL
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Meaured using eight 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25
C.
4. Unused inputs held at 0.0V.
5. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I
CC
.
Table 2-0007/2128E
V
OH
I
IH
I
IL
PARAMETER
I
IL-PU
I
OS
1
I
CC
3,4
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Operating Power Supply Current
I
OL
= 8 mA
I
OH
= -4 mA
0V
V
IN
V
IL
(Max.)
V
IL
= 0.0V, V
IH
= 3.0V
CONDITION
MIN.
TYP.
3
MAX. UNITS
2.4
0.4
10
-10
10
V
V
A
Input or I/O High Leakage Current
V
CCIO
V
IN
5.25V
(V
CCIO
- 0.2)V
V
IN
V
CCIO
A
A
I/O Active Pull-Up Current
0V
V
IN
2.0V
-10
-250
A
Output Short Circuit Current
V
CCIO
= 5.0V or 3.3V, V
OUT
= 0.5V
-240
mA
165
mA
f
TOGGLE
= 1 MHz
+ 5V
R1
R2
CL
*
Device
Output
Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213A
DC Electrical Characteristics
Over Recommended Operating Conditions
Specifications
ispLSI 2128E
5
t
pd1
UNITS
-180
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/2128E
1
1
tsu2 + tco1
( )
-135
MIN.
MAX.
MAX.
DESCRIPTION
#
2
4
PARAMETER
A
1
Data Prop Delay, 4PT Bypass, ORP Bypass
5.0
7.5
ns
t
pd2
A
2
Data Prop Delay
ns
f
max
A
3
Clk Freq with Internal Feedback
3
180
135
MHz
f
max (Ext.)
4
Clk Freq with External Feedback
MHz
f
max (Tog.)
5
Clk Frequency, Max. Toggle
MHz
t
su1
6
GLB Reg Setup Time before Clk, 4 PT Bypass
ns
t
co1
A
7
GLB Reg Clk to Output Delay, ORP Bypass
ns
t
h1
8
GLB Reg Hold Time after Clk, 4 PT Bypass
0.0
ns
t
su2
9
GLB Reg Setup Time before Clk
5.0
ns
t
co2
10 GLB Reg Clk to Output Delay
ns
t
h2
11 GLB Reg Hold Time after Clk
0.0
ns
t
r1
A
12 External Reset Pin to Output Delay
ns
t
rw1
13 External Reset Pulse Duration
4.0
ns
t
ptoeen
B
14 Input to Output Enable
ns
t
ptoedis
C
15 Input to Output Disable
ns
t
goeen
B
16 Global OE Output Enable
ns
t
goedis
C
17 Global OE Output Disable
ns
t
wh
18 External Synch Clk Pulse Duration, High
2.5
ns
t
wl
19 External Synch Clk Pulse Duration, Low
2.5
ns
125
200
4.0
3.0
3.5
7.0
10.0
10.0
5.0
5.0
7.5
100
143
5.0
0.0
6.0
0.0
5.0
3.5
3.5
10.0
4.0
4.5
10.0
12.0
12.0
7.0
7.0
-100
MIN. MAX.
10.0
100
0.0
8.0
0.0
6.5
5.0
5.0
77.0
100
6.5
5.0
6.0
13.5
15.0
15.0
9.0
9.0
13.0
External Timing Parameters
Over Recommended Operating Conditions