ispLSI

2128VL

2.5V In-System Programmable

SuperFASTTM High Density PLD

2128vL_02

Features

· SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

-- 6000 PLD Gates
-- 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
-- 128 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

-- Small Logic Block Size for Random Logic
-- 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2128V and 2128VE Devices

· 2.5V LOW VOLTAGE 2128 ARCHITECTURE

-- Interfaces with Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)

-- 125 mA Typical Active Current

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 150 MHz Maximum Operating Frequency

pd = 6.0 ns Propagation Delay

-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture
-- Unused Product Term Shutdown Saves Power

· IN-SYSTEM PROGRAMMABLE

-- 2.5V In-System Programmability (ISPTM) Using

Boundary Scan Test Access Port (TAP)

-- Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic

-- Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

-- Reprogram Soldered Devices for Faster Prototyping

· 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

· THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global

Interconnectivity

· ispDesignEXPERTTM LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

Functional Block Diagram*

Description

The ispLSI 2128VL is a High Density Programmable
Logic Device available in 128 and 64 I/O-pin versions.
The device contains 128 Registers, eight Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2128VL fea-
tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2128VL offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2128VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

Global Routing Pool (GRP)

Output Routing Pool (ORP)

utput Routing Pool (ORP)

Output Routing Pool (ORP)

CLK 0

Output Routing Pool (ORP)

utput Routing Pool (ORP)

CLK 1

CLK 2

Logic
Array

GLB

0139A/2128VL

*128 I/O version shown

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

September 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications

ispLSI 2128VL

Functional Block Diagram

Figure 1. ispLSI 2128VL Functional Block Diagram (128-I/O and 64-I/O Versions)

The 128-I/O 2128VL contains 128 I/O cells, while the 64-
I/O version contains 64 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control, and the output
drivers can source 4mA or sink 8mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 3.3V signal levels to support
mixed-voltage systems.

Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
the two or one ORPs. Each ispLSI 2128VL device con-
tains four Megablocks.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 2128VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a

GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2128VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.

Global

Routing

Pool

(GRP)

0139B/2128VL

Megablock

RESET

Input Bus

Output Routing Pool (ORP)

I/O 127

I/O 126

I/O 125

I/O 124

I/O 123

I/O 122

I/O 121

I/O 120

I/O 119

I/O 118

I/O 117

I/O 116

I/O 115

I/O 114

I/O 113

I/O 112

I/O 111

I/O 110

I/O 109

I/O 108

I/O 107

I/O 106

I/O 105

I/O 104

I/O 103

I/O 102

I/O 101

I/O 100

I/O 99

I/O 98

I/O 97

I/O 96

IN 7

Output Routing Pool (ORP)

utput Routing Pool (ORP)

Input Bus

IN 5
IN 4

I/O 91
I/O 90
I/O 89
I/O 88

I/O 87
I/O 86
I/O 85
I/O 84

I/O 83
I/O 82
I/O 81
I/O 80

I/O 79
I/O 78
I/O 77
I/O 76

I/O 75
I/O 74
I/O 73
I/O 72

I/O 71
I/O 70
I/O 69
I/O 68

I/O 67
I/O 66
I/O 65
I/O 64

I/O 95
I/O 94
I/O 93
I/O 92

Output Routing Pool (ORP)

Input Bus

CLK 0

I/O 32

I/O 33

I/O 34

I/O 35

I/O 36

I/O 37

I/O 38

I/O 39

I/O 40

I/O 41

I/O 42

I/O 43

I/O 44

I/O 45

I/O 46

I/O 47

I/O 48

I/O 49

I/O 50

I/O 51

I/O 52

I/O 53

I/O 54

I/O 55

I/O 56

I/O 57

I/O 58

I/O 59

I/O 60

I/O 61

I/O 62

I/O 63

TDO/IN 2

TCK/IN 3

Output Routing Pool (ORP)

utput Routing Pool (ORP)

BSCAN

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8
I/O 9

I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

I/O 16
I/O 17
I/O 18
I/O 19

I/O 20
I/O 21
I/O 22
I/O 23

I/O 24
I/O 25
I/O 26
I/O 27

I/O 28
I/O 29
I/O 30
I/O 31

I/O 0
I/O 1
I/O 2
I/O 3

GOE 0
GOE 1

CLK 1

CLK 2

Input Bus

TDI/IN 0

TMS/IN 1

IN 6

Generic Logic

Blocks (GLBs)

Global

Routing

Pool

(GRP)

0139B/2128VL.64IO

Megablock

RESET

Input Bus

Output Routing Pool (ORP)

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

IN 7*

Output Routing Pool (ORP)

Input Bus

IN 5*
IN 4*

I/O 43
I/O 42
I/O 41
I/O 40

I/O 39
I/O 38
I/O 37
I/O 36

I/O 35
I/O 34
I/O 33
I/O 32

I/O 47
I/O 46
I/O 45
I/O 44

Output Routing Pool (ORP)

Input Bus

CLK 0

TDO/IN 2

TCK/IN 3

Output Routing Pool (ORP)

BSCAN

I/O 4
I/O 5
I/O 6
I/O 7

I/O 8
I/O 9

I/O 10
I/O 11

I/O 12
I/O 13
I/O 14
I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 0
I/O 1
I/O 2
I/O 3

GOE 0
GOE 1

CLK 1

CLK 2

Input Bus

TDI/IN 0

TMS/IN 1

*Not available on 84-PLCC Device

IN 6*

Generic Logic

Blocks (GLBs)

Specifications

ispLSI 2128VL

Absolute Maximum Ratings

Supply Voltage V

................................ -0.5 to +4.05V

Input Voltage Applied ............................. -0.5 to +4.05V

Off-State Output Voltage Applied .......... -0.5 to +4.05V

Storage Temperature ................................ -65 to 150

Case Temp. with Power Applied .............. -55 to 125

Max. Junction Temp. (T

) with Power Applied ... 150

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

Erase Reprogram Specifications

Capacitance (T

=25

C, f=1.0 MHz)

SYMBOL

Table 2-0006/2128VL

PARAMETER

I/O Capacitance

UNITS

TYPICAL

TEST CONDITIONS

Dedicated Input Capacitance

V = 2.5V, V = 0.0V

I/O

Clock and Global Output Enable Capacitance

V = 2.5V, V = 0.0V

Table 2-0008/2128VL

PARAMETER

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10,000

Cycles

= 0

C to + 70

= -40

C to + 85

SYMBOL

Table 2-0005/2128VL

PARAMETER

Supply Voltage

Input High Voltage

Input Low Voltage

MIN.

MAX.

UNITS

2.3

1.7

-0.3

2.7

3.6

0.7

Commercial

Industrial

Specifications

ispLSI 2128VL

Switching Test Conditions

Figure 2. Test Load

Input Pulse Levels

Table 2 - 0003/2128VL

Input Rise and Fall Time

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to V

1.5ns 10% to 90%

See Figure 2

3-state levels are measured 0.15V from
steady-state active level.

DC Electrical Characteristics

Over Recommended Operating Conditions

Output Load Conditions (see Figure 2)

TEST CONDITION

250

218

35pF

218

35pF

250

35pF

Active High

Active Low

250

5pF

218

5pF

Active Low to Z
at V +0.15V

Active High to Z
at V -0.15V

Table 2-0004/2128VL

Device
Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

0213A/2128VL

SYMBOL

1. One output at a time for a maximum duration of one second. V

OUT

= 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at V

= 2.5V and T

= 25

4. Maximum I

varies widely with specific device configuration and operating frequency. Refer to Power Consumption

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I

5. With no pull-up resistors.

Table 2-0007/2128VL

IL-isp

PARAMETER

IL-PU

2, 4

Output Low Voltage

Output High Voltage

Input or I/O High Leakage Current

Input or I/O Low Leakage Current

BSCAN

Input Pull-Up Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

= 100

V (Max.)

V = 2.5V, V = 0.5V

V = 0.0V, V = 2.5V

f = 1 MHz

IN IL

CC OUT

CLK

IL IH

CONDITION

MIN.

TYP.

MAX.

UNITS

2.0

125

0.2

-10

-150

-100

(min)

3.6V

= 8mA

= -1mA

- 0.2

= -100

1.8

= -4mA

0.4

Specifications

ispLSI 2128VL

External Timing Parameters

Over Recommended Operating Conditions

pd1

UNITS

-135

MIN.

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.

Table 2-0030/2128VL

1
tsu2 + tco1

( )

-100

MIN.

MAX.

DESCRIPTION

PARAMETER

Data Propagation Delay, 4PT Bypass, ORP Bypass

7.5

10.0

pd2

Data Propagation Delay

max

Clock Frequency with Internal Feedback

135

100

MHz

max (Ext.)

Clock Frequency with External Feedback

MHz

max (Tog.)

Clock Frequency, Max. Toggle

MHz

su1

GLB Reg. Setup Time before Clock, 4 PT Bypass

co1

GLB Reg. Clock to Output Delay, ORP Bypass

GLB Reg. Hold Time after Clock, 4 PT Bypass

0.0

su2

GLB Reg. Setup Time before Clock

6.0

co2

GLB Reg. Clock to Output Delay

GLB Reg. Hold Time after Clock

0.0

Ext. Reset Pin to Output Delay, ORP Bypass

rw1

Ext. Reset Pulse Duration

5.5

ptoeen

Input to Output Enable

ptoedis

Input to Output Disable

goeen

Global OE Output Enable

goedis

Global OE Output Disable

External Synchronous Clock Pulse Duration, High

3.5

External Synchronous Clock Pulse Duration, Low

3.5

143

5.0

4.5

5.5

8.0

12.0

7.0

10.0

100

6.5

0.0

8.0

0.0

6.5

5.0

13.0

5.0

6.0

13.5

15.0

9.0

-150

MIN. MAX.

6.0

150

0.0

5.0

0.0

5.0

3.0

111

166

4.0

5.0

6.0

10.0

6.0

8.5

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