Specifications
GAL16V8
1996 Data Book
3-65
1
10
11
20
I/CLK
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
5
15
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PIN CONFIGURATION
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
-- 5 ns Maximum Propagation Delay
-- Fmax = 166 MHz
-- 4 ns Maximum from Clock Input to Data Output
-- UltraMOS
Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
-- 75mA Typ Icc on Low Power Device
-- 45mA Typ Icc on Quarter Power Device
ACTIVE PULL-UPS ON ALL PINS
E
2
CELL TECHNOLOGY
-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/Guaranteed 100% Yields
-- High Speed Electrical Erasure (<100ms)
-- 20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
-- Maximum Flexibility for Complex Logic Designs
-- Programmable Output Polarity
-- Also Emulates 20-pin PAL
Devices with Full Func-
tion/Fuse Map/Parametric Compatibility
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-- 100% Functional Testability
APPLICATIONS INCLUDE:
-- DMA Control
-- State Machine Control
-- High Speed Graphics Processing
-- Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
The GAL16V8C, at 5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL16V8 are the PAL
architectures
listed in the table of the macrocell description section. GAL16V8
devices are capable of emulating any of these PAL architectures
with full function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor guarantees 100% field programmability
and functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are guaranteed.
PLCC
GAL
16V8
DIP
GAL16V8
Top View
2
20
I/CLK
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
4
6
8
9
11
13
14
16
18
I/CLK
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
CLK
8
8
8
8
8
8
8
8
OE
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
PROGRAMMABLE
AND-ARRAY
(64 X 32)
I/OE
GAL16V8
High Performance E
2
CMOS PLD
Generic Array LogicTM
Copyright 1996 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, L with Lattice Semiconductor Corp. and L (Stylized) are registered
trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, In-System Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD,
ispGDS, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice
Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
1996 Data Book
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.lattice.com
Specifications
GAL16V8
1996 Data Book
3-66
GAL16V8 ORDERING INFORMATION
Commercial Grade Specifications
Blank = Commercial
I = Industrial
Grade
Package
Power
L = Low Power
Q = Quarter Power
Speed (ns)
XXXXXXXX
XX
X
X X
Device Name
_
P = Plastic DIP
J = PLCC
GAL16V8C
GAL16V8B
PART NUMBER DESCRIPTION
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2
Industrial Grade Specifications
Specifications
GAL16V8
1996 Data Book
3-67
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is ac-
complished by development software/hardware and is completely
transparent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes are illustrated in the following pages. Two global bits, SYN
and AC0, control the mode configuration for all macrocells. The
XOR bit of each macrocell controls the polarity of the output in any
of the three modes, while the AC1 bit of each of the macrocells
controls the input/output configuration. These two global and 16
individual architecture bits define all possible configurations in a
GAL16V8 . The information given on these architecture bits is
only to give a better understanding of the device. Compiler soft-
ware will transparently set these architecture bits from the pin
definitions, so the user should not need to directly manipulate
these architecture bits.
The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.
PAL Architectures
GAL16V8
Emulated by GAL16V8
Global OLMC Mode
16R8
Registered
16R6
Registered
16R4
Registered
16RP8
Registered
16RP6
Registered
16RP4
Registered
16L8
Complex
16H8
Complex
16P8
Complex
10L8
Simple
12L6
Simple
14L4
Simple
16L2
Simple
10H8
Simple
12H6
Simple
14H4
Simple
16H2
Simple
10P8
Simple
12P6
Simple
14P4
Simple
16P2
Simple
COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OLMC
modes as different device types. These device types are listed
in the table below. Most compilers have the ability to automati-
cally select the device type, generally based on the register usage
and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. The different device types listed in the table
can be used to override the automatic device selection by the
software. For further details, refer to the compiler software
manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.
In registered mode pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be
configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
Registered
Complex
Simple
Auto Mode Select
ABEL
P16V8R
P16V8C
P16V8AS
P16V8
CUPL
G16V8MS
G16V8MA
G16V8AS
G16V8
LOG/iC
GAL16V8_R
GAL16V8_C7
GAL16V8_C8
GAL16V8
OrCAD-PLD
"Registered"
1
"Complex"
1
"Simple"
1
GAL16V8A
PLDesigner
P16V8R
2
P16V8C
2
P16V8C
2
P16V8A
TANGO-PLD
G16V8R
G16V8C
G16V8AS
3
G16V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
Specifications
GAL16V8
1996 Data Book
3-68
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/O's are possible in this
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.
Registered outputs have eight product terms per output. I/O's
have seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
D
Q
Q
CLK
OE
XOR
XOR
Specifications
GAL16V8
1996 Data Book
3-69
REGISTERED MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
19
XOR-2048
AC1-2120
XOR-2049
AC1-2121
XOR-2050
AC1-2122
XOR-2051
AC1-2123
XOR-2052
AC1-2124
XOR-2053
AC1-2125
XOR-2054
AC1-2126
XOR-2055
AC1-2127
28
24
20
16
12
8
4
0
PTD
2128
2191
OE
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
SYN-2192
AC0-2193
Specifications
GAL16V8
1996 Data Book
3-70
COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or I/O functions.
Architecture configurations available in this mode are similar to
the common 16L8 and 16P8 devices with programmable polarity
in each macrocell.
Up to six I/O's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 12 & 19) do not have input ca-
pability. Designs requiring eight I/O's can be implemented in the
Registered mode.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
11 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 13 through Pin 18 are configured to this function.
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 12 and Pin 19 are configured to this function.
XOR
XOR
Specifications
GAL16V8
1996 Data Book
3-71
COMPLEX MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
PTD
2128
2191
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
SYN-2192
AC0-2193
XOR-2055
AC1-2127
XOR-2054
AC1-2126
XOR-2053
AC1-2125
XOR-2052
AC1-2124
XOR-2051
AC1-2123
XOR-2050
AC1-2122
XOR-2049
AC1-2121
XOR-2048
AC1-2120
OLMC
OLMC
28
24
20
16
12
8
4
0
Specifications
GAL16V8
1996 Data Book
3-72
SIMPLE MODE
In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.
Architecture configurations available in this mode are similar to
the common 10L8 and 12P6 devices with many permutations of
generic output polarity or input choices.
All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro-
grammable polarity.
Pins 1 and 11 are always available as data inputs into the AND
array. The center two macrocells (pins 15 & 16) cannot be used
as input or I/O pins, and are only available as dedicated outputs.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.
Combinatorial Output with Feedback Configuration
for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
Combinatorial Output Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- Pins 15 & 16 are permanently configured to this
function.
Dedicated Input Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Vcc
XOR
Vcc
XOR
Specifications
GAL16V8
1996 Data Book
3-73
SIMPLE MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
11
12
13
14
15
16
17
18
19
2
3
4
5
6
7
9
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
PTD
2128
2191
8
XOR-2048
AC1-2120
OLMC
XOR-2049
AC1-2121
XOR-2050
AC1-2122
XOR-2051
AC1-2123
XOR-2052
AC1-2124
XOR-2053
AC1-2125
XOR-2054
AC1-2126
XOR-2055
AC1-2127
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
SYN-2192
AC0-2193
28
24
20
16
12
8
4
0
Specifications
GAL16V8
1996 Data Book
3-74
Specifications
GAL16V8C
V
IL
Input Low Voltage
Vss 0.5
--
0.8
V
V
IH
Input High Voltage
2.0
--
Vcc+1
V
I
IL
1
Input or I/O Low Leakage Current
0V
V
IN
V
IL
(MAX.)
--
--
100
A
I
IH
Input or I/O High Leakage Current
3.5V
V
IN
V
CC
--
--
10
A
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.5
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OL
Low Level Output Current
--
--
16
mA
I
OH
High Level Output Current
--
--
3.2
mA
I
OS
2
Output Short Circuit Current
V
CC
= 5V
V
OUT
= 0.5V
T
A
= 25
C
30
--
150
mA
ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING COND.
Commercial Devices:
Ambient Temperature (T
A
) ............................... 0 to 75
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.75 to +5.25V
Supply voltage V
CC
....................................... 0.5 to +7V
Input voltage applied .......................... 2.5 to V
CC
+1.0V
Off-state output voltage applied .......... 2.5 to V
CC
+1.0V
Storage Temperature ................................. 65 to 150
C
Ambient Temperature with
Power Applied ........................................ 55 to 125
C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
3
MAX.
UNITS
COMMERCIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -5/-7
--
75
115
mA
Supply Current
f
toggle
= 15MHz Outputs Open
INDUSTRIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -7
--
75
130
mA
Supply Current
f
toggle
= 15MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and T
A
= 25
C
Industrial Devices:
Ambient Temperature (T
A
) ........................... 40 to 85
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.50 to +5.50V
Specifications
GAL16V8
1996 Data Book
3-75
Specifications
GAL16V8C
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
-7
MIN. MAX.
-7
MIN. MAX.
t
pd
A
Input or I/O to
8 outputs switching
1
5
3
7.5
1
7.5
ns
Comb. Output
1 output switching
--
--
--
7
--
--
ns
t
co
A
Clock to Output Delay
1
4
2
5
1
5
ns
t
cf
2
--
Clock to Feedback Delay
--
3
--
3
--
3
ns
t
su
--
Setup Time, Input or Feedback before Clock
3
--
7
--
7
--
ns
t
h
--
Hold Time, Input or Feedback after Clock
0
--
0
--
0
--
ns
A
Maximum Clock Frequency with
142.8 --
83.3
--
83.3
--
MHz
External Feedback, 1/(tsu + tco)
f
max
3
A
Maximum Clock Frequency with
166
--
100
--
100
--
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
166
--
100
--
100
--
MHz
No Feedback
t
wh
--
Clock Pulse Duration, High
3
--
5
--
5
--
ns
t
wl
--
Clock Pulse Duration, Low
3
--
5
--
5
--
ns
t
en
B
Input or I/O to Output Enabled
1
6
3
9
1
9
ns
B
OE to Output Enabled
1
6
2
6
1
6
ns
t
dis
C
Input or I/O to Output Disabled
1
5
2
9
1
9
ns
C
OE to Output Disabled
1
5
1.5
6
1
6
ns
UNITS
PARAMETER
TEST
COND
1
.
DESCRIPTION
IND
COM
COM
-5
MIN. MAX.
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section. Characterized initially and after any design or process changes that may affect these
parameters.
CAPACITANCE (T
A
= 25
C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
8
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Guaranteed but not 100% tested.
Specifications
GAL16V8
1996 Data Book
3-76
Specifications
GAL16V8B
INDUSTRIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -10/-15/-25
--
75
130
mA
Supply Current
f
toggle
= 15MHz Outputs Open
Q -20/-25
--
45
65
mA
COMMERCIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -7/-10
--
75
115
mA
Supply Current
f
toggle
= 15MHz Outputs Open
L -15/-25
--
75
90
mA
Q -15/-25
--
45
55
mA
ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING COND.
Commercial Devices:
Ambient Temperature (T
A
) ............................... 0 to 75
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.75 to +5.25V
Supply voltage V
CC
....................................... 0.5 to +7V
Input voltage applied .......................... 2.5 to V
CC
+1.0V
Off-state output voltage applied .......... 2.5 to V
CC
+1.0V
Storage Temperature ................................. 65 to 150
C
Ambient Temperature with
Power Applied ........................................ 55 to 125
C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
Industrial Devices:
Ambient Temperature (T
A
) ........................... 40 to 85
C
Supply voltage (V
CC
)
with Respect to Ground ..................... +4.50 to +5.50V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
3
MAX.
UNITS
V
IL
Input Low Voltage
Vss 0.5
--
0.8
V
V
IH
Input High Voltage
2.0
--
Vcc+1
V
I
IL
1
Input or I/O Low Leakage Current
0V
V
IN
V
IL
(MAX.)
--
--
100
A
I
IH
Input or I/O High Leakage Current
3.5V
V
IN
V
CC
--
--
10
A
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.5
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OL
Low Level Output Current
--
--
24
mA
I
OH
High Level Output Current
--
--
3.2
mA
I
OS
2
Output Short Circuit Current
V
CC
= 5V
V
OUT
= 0.5V
T
A
= 25
C
30
--
150
mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and T
A
= 25
C
Specifications
GAL16V8
1996 Data Book
3-77
Specifications
GAL16V8B
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
t
pd
A
Input or I/O to
8 outputs switching
3
7.5
3
10
3
15
3
20
3
25
ns
Comb. Output
1 output switching
--
7
--
--
--
--
--
--
--
--
ns
t
co
A
Clock to Output Delay
2
5
2
7
2
10
2
11
2
12
ns
t
cf
2
--
Clock to Feedback Delay
--
3
--
6
--
8
--
9
--
10
ns
t
su
--
Setup Time, Input or Fdbk before Clk
7
--
10
--
12
--
13
--
15
--
ns
t
h
--
Hold Time, Input or Fdbk after Clk
0
--
0
--
0
--
0
--
0
--
ns
A
Maximum Clock Frequency with
83.3
--
58.8
--
45.5
--
41.6
--
37
--
MHz
External Feedback, 1/(tsu + tco)
f
max
3
A
Maximum Clock Frequency with
100
--
62.5
--
50
--
45.4
--
40
--
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
100
--
62.5
--
62.5
--
50
--
41.6
--
MHz
No Feedback
t
wh
--
Clock Pulse Duration, High
5
--
8
--
8
--
10
--
12
--
ns
t
wl
--
Clock Pulse Duration, Low
5
--
8
--
8
--
10
--
12
--
ns
t
en
B
Input or I/O to Output Enabled
3
9
3
10
--
15
--
20
--
25
ns
B
OE to Output Enabled
2
6
2
10
--
15
--
18
--
20
ns
t
dis
C
Input or I/O to Output Disabled
2
9
2
10
--
15
--
20
--
25
ns
C
OE to Output Disabled
1.5
6
1.5
10
--
15
--
18
--
20
ns
UNITS
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.
-25
MIN.
MAX.
-20
MIN.
MAX.
-15
MIN.
MAX.
-10
MIN.
MAX.
PARAM.
DESCRIPTION
TEST
COND
1
.
-7
MIN.
MAX.
CAPACITANCE (T
A
= 25
C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
8
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Guaranteed but not 100% tested.
COM
COM / IND
COM / IND
IND
COM / IND
Specifications
GAL16V8
1996 Data Book
3-78
SWITCHING WAVEFORMS
Registered Output
Combinatorial Output
OE to Output Enable/Disable
Input or I/O to Output Enable/Disable
f
max with Feedback
Clock Width
COMBINATIONAL
OUTPUT
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATIONAL
OUTPUT
INPUT or
I/O FEEDBACK
t
en
t
dis
CLK
(w/o fb)
1/
f
max
t
wl
t
wh
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
(external fdbk)
t
su
t
co
t
h
1/
f
max
OE
REGISTERED
OUTPUT
t
en
t
dis
CLK
REGISTERED
FEEDBACK
t
cf
t
su
1/
f
max (internal fdbk)
Specifications
GAL16V8
1996 Data Book
3-79
fmax DESCRIPTIONS
f
max with Internal Feedback 1/(
t
su+
t
cf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
f
max with External Feedback 1/(
t
su+
t
co)
Note: fmax with external feedback is calculated from measured
tsu and tco.
f
max with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
SWITCHING TEST CONDITIONS
REGISTER
LOGIC
ARRAY
CLK
t
su +
t
h
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
GAL16V8C Output Load Conditions (see figure)
Test Condition
R
1
R
2
C
L
A
200
200
50pF
B
Active High
200
50pF
Active Low
200
200
50pF
C
Active High
200
5pF
Active Low
200
200
5pF
GAL16V8B Output Load Conditions (see figure)
Test Condition
R
1
R
2
C
L
A
200
390
50pF
B
Active High
390
50pF
Active Low
200
390
50pF
C
Active High
390
5pF
Active Low
200
390
5pF
Input Pulse Levels
GND to 3.0V
Input Rise and
GAL16V8B
2 3ns 10% 90%
Fall Times
GAL16V8C
1.5ns 10% 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
Specifications
GAL16V8
1996 Data Book
3-80
ELECTRONIC SIGNATURE
An electronic signature is provided in every GAL16V8 device. It
contains 64 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision num-
bers, or inventory control. The signature data is always available
to the user independent of the state of the security cell.
NOTE: The electronic signature is included in checksum calcu-
lations. Changing the electronic signature will alter the checksum.
SECURITY CELL
A security cell is provided in the GAL16V8 devices to prevent un-
authorized copying of the array patterns. Once programmed, this
cell prevents further read access to the functional bits in the de-
vice. This cell can only be erased by re-programming the device,
so the original configuration can never be examined once this cell
is programmed. The Electronic Signature is always available to
the user, regardless of the state of this control cell.
LATCH-UP PROTECTION
GAL16V8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential of latch-up caused by negative input undershoots.
Additionally, outputs are designed with n-channel pull-ups instead
of the traditional p-channel pull-ups in order to eliminate latch-up
due to output overshoots.
DEVICE PROGRAMMING
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.
GAL16V8 devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing text
vectors perform output register preload automatically.
INPUT BUFFERS
GAL16V8 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar
TTL devices.
The GAL16V8 input and I/O pins have built-in active pull-ups. As
a result, unused inputs and I/O's will float to a TTL "high" (logi-
cal "1"). Lattice Semiconductor recommends that all unused
inputs and tri-stated I/O pins be connected to another active input,
V
CC
, or Ground. Doing this will tend to improve noise immunity
and reduce I
CC
for the device.
Typical Input Pull-up Characteristic
1 . 0
2 . 0
3 . 0
4 . 0
5 . 0
- 6 0
0
- 2 0
- 4 0
0
In p u t V o lt ag e ( V o lt s)
I
nput
C
u
r
r
e
nt
(
u
A
)
Specifications
GAL16V8
1996 Data Book
3-81
Typ. Vref = 3.2V
Typical Output
Typ. Vref = 3.2V
Typical Input
INPUT/OUTPUT EQUIVALENT SCHEMATICS
POWER-UP RESET
Circuitry within the GAL16V8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (
t
pr, 1
s MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
conditions must be met to guarantee a valid power-up reset of the
device. First, the V
CC
rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of
t
pr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Specifications
GAL16V8
1996 Data Book
3-82
GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-1
-0.75
-0.5
-0.25
0
1
2
3
4
5
6
7
8
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-1
-0.75
-0.5
-0.25
0
1
2
3
4
5
6
7
8
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
0
50
100
150
200
250
300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
0
50
100
150
200
250
300
RISE
FALL
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Specifications
GAL16V8
1996 Data Book
3-83
GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Iol (mA)
Vol (V)
0
0.5
1
1.5
2
0.00
20.00
40.00
60.00
80.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00
10.00
20.00
30.00
40.00
50.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.25
3.5
3.75
4
4.25
0.00
1.00
2.00
3.00
4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
4.50
4.75
5.00
5.25
5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
0
25
50
75
100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
2
4
6
8
10
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
5
10
15
20
25
30
35
40
45
-2.00
-1.50
-1.00
-0.50
0.00
Specifications
GAL16V8
1996 Data Book
3-84
GAL 16V8B-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
10
0
50
100
150
200
250
300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
10
0
50
100
150
200
250
300
RISE
FALL
Specifications
GAL16V8
1996 Data Book
3-85
GAL 16V8B-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Iol (mA)
Vol (V)
0
0.25
0.5
0.75
1
0.00
20.00
40.00
60.00
80.00
100.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00
10.00
20.00
30.00
40.00
50.00
60.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.5
3.75
4
4.25
4.5
0.00
1.00
2.00
3.00
4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
4.50
4.75
5.00
5.25
5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
-55
-25
0
25
50
75
100
125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
1.30
0
25
50
75
100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
2
4
6
8
10
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
70
80
90
100
-2.00
-1.50
-1.00
-0.50
0.00
Specifications
GAL16V8
1996 Data Book
3-86
GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
Specifications
GAL16V8
1996 Data Book
3-87
GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Iol (mA)
Vol (V)
0
0.5
1
1.5
2
0.00
20.00
40.00
60.00
80.00
100.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00
10.00
20.00
30.00
40.00
50.00
60.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.25
3.5
3.75
4
4.25
0.00
1.00
2.00
3.00
4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
4.50
4.75
5.00
5.25
5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
-55
-25
0
25
50
75
100
125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
1.30
1.40
0
25
50
75
100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
2
4
6
8
10
12
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
70
80
90
100
-2.00
-1.50
-1.00
-0.50
0.00
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