GAL20XV10
High-Speed E
2
CMOS PLD
Generic Array LogicTM
1
2
28
NC
I/CLK
I
I
I
I
I
I
I
I
NC
NC
NC
GND
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q
I/O/Q
I/OE
4
5
7
9
11
12
14
16
18
19
21
23
25
26
1
12
13
24
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
6
18
Description
The GAL20XV10 combines a high performance CMOS process
with electrically erasable (E
2
) floating gate technology to provide
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides
a substantial savings in power when compared to bipolar counter-
parts. E
2
CMOS technology offers high speed (<100ms) erase
times providing the ability to reprogram, reconfigure or test the de-
vices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL20XV10 are the PAL
architectures
listed in the macrocell description section of this document. The
GAL20XV10 is capable of emulating these PAL architectures with
full function and parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
GAL20XV10
Top View
PLCC
DIP
Features
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
-- 10 ns Maximum Propagation Delay
-- Fmax = 100 MHz
-- 7 ns Maximum from Clock Input to Data Output
-- TTL Compatible 16 mA Outputs
-- UltraMOS
Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
-- 90mA Maximum Icc
-- 75mA Typical Icc
ACTIVE PULL-UPS ON ALL PINS
E
2
CELL TECHNOLOGY
-- Reconfigurable Logic
-- Reprogrammable Cells
-- 100% Tested/100% Yields
-- High Speed Electrical Erasure (<100 ms)
-- 20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
-- XOR Gate Capability on all Outputs
-- Full Function and Parametric Compatibility with
PAL12L10, 20L10, 20X10, 20X8, 20X4
-- Registered or Combinatorial with Polarity
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
APPLICATIONS INCLUDE:
-- High Speed Counters
-- Graphics Processing
-- Comparators
ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL
20XV10
PROGRAMMABLE
AND-ARRAY
(40 X 40)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/CLK
I
I
I
I
I
I
I
I
I
I
4
4
4
4
4
4
4
4
4
4
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I/OE
Copyright 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
July 1997
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
20xv10_02
Functional Block Diagram
Pin Configuration
Specifications
GAL20XV10
2
)
s
n
(
d
p
T
)
s
n
(
u
s
T
)
s
n
(
o
c
T
)
A
m
(
c
c
I
#
g
n
i
r
e
d
r
O
e
g
a
k
c
a
P
0
1
6
7
0
9
P
L
0
1
-
B
0
1
V
X
0
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
4
2
J
L
0
1
-
B
0
1
V
X
0
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
5
1
8
8
0
9
P
L
5
1
-
B
0
1
V
X
0
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
4
2
J
L
5
1
-
B
0
1
V
X
0
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
0
2
0
1
0
1
0
9
P
L
0
2
-
B
0
1
V
X
0
2
L
A
G
P
I
D
c
i
t
s
a
l
P
n
i
P
-
4
2
J
L
0
2
-
B
0
1
V
X
0
2
L
A
G
C
C
L
P
d
a
e
L
-
8
2
Blank = Commercial
Grade
Package
Power
L = Low Power
Speed (ns)
XXXXXXXX
XX
X
X X
Device Name
_
P = Plastic DIP
J = PLCC
GAL20XV10B
GAL20XV10 Ordering Information
Commercial Grade Specifications
Part Number Description
Specifications
GAL20XV10
3
The following discussion pertains to configuring the Output Logic
Macrocell. It should be noted that actual implementation is
accomplished by development software/hardware and is com-
pletely transparent to the user.
The GAL20XV10 has two global architecture configurations that
allow it to emulate PAL architectures. The Input mode emulates
combinatorial PAL devices, with the I/CLK and I/OE pins used as
inputs. The Feedback mode emulates registered PAL devices with
the I/CLK pin used as the register clock and the I/OE pin as an
output enable for all registers. The following is a list of PAL archi-
tectures that the GAL20XV10 can emulate. It also shows the
global architecture mode used to emulate the PAL architecture.
PAL12L10
PAL20L10
PAL20X10
PAL20X8
PAL20X4
Input Mode
Feedback Mode
Feedback Mode
Feedback Mode
Input Mode
PAL Architectures Emulated by
GAL20XV10
GAL20XV10 Global
OLMC Mode
INPUT MODE
The Input mode architecture is defined when the global
architecture bit SYN = 1. In this mode, the I/CLK pin becomes an
input to the AND array and also provides the clock source for
all registers. The I/OE pin becomes an input into the AND array
and provides the output enable control for any macrocell config-
ured as an Exclusive-OR function. Feedback into the AND array
is provided from macrocells 2 through 9 only. In this mode,
macrocells 1 and 10 have no feedback into the AND array.
FEEDBACK MODE
The Feedback mode architecture is defined when the global
architecture bit SYN = 0. In this mode the I/CLK pin becomes a
dedicated clock source for all registers. The I/OE pin is a dedi-
cated output enable control for any macrocell configured as an
Exclusive-OR function. The I/CLK and I/OE pins are not avail-
able to the AND array in this mode. Feedback into the AND array
is provided on all macrocells 1 through 10.
FEATURES
Each Output Logic Macrocell has four possible logic function
configurations controlled by architecture control bits AC0 and AC1.
Four product terms are fed into each macrocell.
XOR REGISTERED CONFIGURATION
The Macrocell is set to the Exclusive-OR Registered configuration
when AC0 = 0 and AC1 = 0. The four product terms are seg-
mented into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed into a D-type
register. The register is clocked by the low-to-high transition of the
I/CLK pin. The inverting output buffer is enabled by the
I/OE pin, which is an active low output enable common to all
Exclusive-OR macrocells. In Feedback mode, the state of the
register is available to the AND array via an internal feedback
path on all macrocells. In Input mode, the state of the register
is available to the AND array via an internal feedback path on
macrocells 2 through 9 only, macrocells 1 and 10 have no feedback
into the AND array.
REGISTERED CONFIGURATION
The Macrocell is set to Registered configuration when AC0 = 1 and
AC1 = 0. Three of the four product terms are used as sum-of-
product terms for the D input of the register. The inverting output
buffer is enabled by the fourth product term. The output is en-
abled while this product term is true. The XOR bit controls the po-
larity of the output. The register is clocked by the low-to-high tran-
sition of the I/CLK. In Feedback mode, the state of the register
is available to the AND array via an internal feedback path on
all macrocells. In Input mode, the state of the register is available
to the AND array via an internal feedback path on macrocells
2 through 9 only, macrocells 1 and 10 have no feedback into the
AND array.
XOR COMBINATORIAL CONFIGURATION
The Macrocell is set to the Exclusive-OR Combinatorial configu-
ration when AC0 = 0 and AC1 = 1. The four product terms are seg-
mented into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed to an output
buffer. The inverting output buffer is enabled by the I/OE pin,
which is an active low output enable that is common to all XOR
macrocells. In Feedback mode, the state of the I/O pin is avail-
able to the AND array via an internal feedback path on all
macrocells. In Input mode, the state of the I/O pin is available to
the AND array via an input buffer path on macrocells 2 through
9 only, macrocells 1 and 10 have no input into the AND array.
COMBINATORIAL CONFIGURATION
The Macrocell is set to Combinatorial mode when AC0 = 1 and
AC1 = 1. Three of the four product terms are used as sum-of-
product terms for the combinatorial output. The XOR bit controls
the polarity of the output. The inverting output buffer is enabled
by the fourth product term. The output is enabled while this product
term is true. In Feedback mode, the state of the I/O pin is avail-
able to the AND array via an internal feedback path on all
macrocells. In Input mode, the state of the I/O pin is available
to the AND array via an input buffer path on macrocells 2 through
9 only, macrocells 1 and 10 have no input into the AND array.
Output Logic Macrocell (OLMC)
Specifications
GAL20XV10
4
XOR Registered Configuration
- SYN = 1.
- AC0 = 0.
- AC1 = 0.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 1(2) can be CLK and/or Input.
- Pin 13(16) can be OE and/or Input.
Combinatorial Configuration
- SYN = 1.
- AC0 = 1.
- AC1 = 1.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OLMC 1 and OLMC10 do not have the
feedback path.
- OE controlled by product term.
XOR Combinatorial Configuration
- SYN = 1.
- AC0 = 0.
- AC1 = 1.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 13(16) can be OE and/or Input.
Registered Configuration
- SYN = 1.
- AC0 = 1.
- AC1 = 0.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 1(2) can be CLK and/or Input.
- OE controlled by product term.
OE
CLK
D
Q
Q
CLK
D
Q
Q
XOR
XOR
OE
Input Mode
Specifications
GAL20XV10
5
SYN - 1630
DIP (PLCC) Package Pinouts
40-USER ELECTRONIC SIGNATURE FUSES
1631, 1632, .... .... 1669, 1670
Byte4 Byte3 .... .... Byte1 Byte0
120
0
160
280
320
440
480
600
640
760
800
920
960
1080
1120
1240
1440
1560
28
12
16
20
24
32
36
0
4
8
1280
1400
AC0 - 1619
AC1 - 1629
AC0 - 1618
AC1 - 1628
AC0 - 1610
AC1 - 1620
AC1 - 1621
AC0 - 1611
OLMC
OLMC
AC1 - 1622
AC0 - 1612
OLMC
AC1 - 1623
AC0 - 1613
OLMC
AC1 - 1624
AC0 - 1614
OLMC
AC1 - 1625
AC1 - 1626
AC0 - 1616
OLMC
OLMC
AC1 - 1627
OLMC
OLMC
OLMC
1(2)
2(3)
3(4)
4(5)
5(6)
6(7)
7(9)
8(10)
9(11)
10(12)
11(13)
13(16)
14(17)
15(18)
16(19)
17(20)
19(23)
20(24)
21(25)
22(26)
XOR - 1600
XOR - 1601
XOR - 1602
XOR - 1603
XOR - 1604
XOR - 1606
AC0 - 1617
XOR - 1607
XOR - 1608
XOR - 1609
18(21)
23(27)
XOR - 1605
AC0 - 1615
Input Mode Logic Diagram
Specifications
GAL20XV10
6
XOR Registered Configuration
- SYN = 0.
- AC0 = 0.
- AC1 = 0.
- Dedicated CLK input on Pin 1(2).
- Dedicated OE input on Pin 13(16).
Registered Configuration
- SYN = 0.
- AC0 = 1.
- AC1 = 0.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- Dedicated CLK input on Pin 1(2).
- OE controlled by product term.
- Pin 13(16) is not connected to this configura-
tion.
XOR Combinatorial Configuration
- SYN = 0.
- AC0 = 0.
- AC1 = 1.
- Dedicated OE input on Pin 13(16).
- Pin 1(2) is not connected to this configura-
tion.
Combinatorial Configuration
- SYN = 0.
- AC0 = 1.
- AC1 = 1.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OE controlled by product term.
- Both pin1(2) and pin 13(16) are not con -
nected to this configuration.
OE
CLK
D
Q
Q
CLK
D
Q
Q
XOR
XOR
OE
Feedback Mode
Specifications
GAL20XV10
7
DIP (PLCC) Package Pinouts
40-USER ELECTRONIC SIGNATURE FUSES
1631, 1632, .... .... 1669, 1670
Byte4 Byte3 .... .... Byte1 Byte0
SYN - 1630
120
0
160
280
320
440
480
600
640
760
800
920
960
1080
1120
1240
1280
1400
1440
1560
AC0 - 1610
AC1 - 1620
AC1 - 1621
AC0 - 1611
AC1 - 1622
AC0 - 1612
AC1 - 1623
AC0 - 1613
OLMC
OLMC
OLMC
OLMC
AC1 - 1624
AC1 - 1625
AC0 - 1615
OLMC
OLMC
AC1 - 1626
AC0 - 1616
AC1 - 1627
OLMC
OLMC
AC1 - 1628
AC0 - 1618
AC1 - 1629
AC0 - 1619
OLMC
OLMC
1(2)
2(3)
3(4)
4(5)
5(6)
6(7)
7(9)
8(10)
9(11)
10(12)
11(13)
13(16)
14(17)
15(18)
16(19)
17(20)
18(21)
19(23)
20(24)
21(25)
22(26)
23(27)
XOR - 1600
XOR - 1601
XOR - 1602
XOR - 1603
AC0 - 1614
XOR - 1604
XOR - 1605
XOR - 1606
AC0 - 1617
XOR - 1607
XOR - 1608
XOR - 1609
28
12
16
20
24
32
36
0
4
8
Feedback Mode Logic Diagram
Specifications
GAL20XV10
8
V
IL
Input Low Voltage
V
SS
0.5
--
0.8
V
V
IH
Input High Voltage
2.0
--
V
CC
+1
V
I
IL
1
Input or I/O Low Leakage Current
0V
V
IN
V
IL
(MAX.)
--
--
100
A
I
IH
Input or I/O High Leakage Current
3.5V
V
IN
V
CC
--
--
10
A
V
OL
Output Low Voltage
I
OL
= MAX. Vin = V
IL
or V
IH
--
--
0.5
V
V
OH
Output High Voltage
I
OH
= MAX. Vin = V
IL
or V
IH
2.4
--
--
V
I
OL
Low Level Output Current
--
--
16
mA
I
OH
High Level Output Current
--
--
3.2
mA
I
OS
2
Output Short Circuit Current
V
CC
= 5V
V
OUT
= 0.5V T
A
= 25
C
50
--
150
mA
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (
T
A
) ............................. 0 to +75
C
Supply voltage (
V
CC
)
with Respect to Ground ..................... +4.75 to +5.25V
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
3
MAX.
UNITS
1) The leakage current is due to the internal pull-up on all input and I/O pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at V
CC
= 5V and T
A
= 25
C
COMMERCIAL
I
CC
Operating Power
V
IL
= 0.5V V
IH
= 3.0V
L -10/-15/-20
--
75
90
mA
Supply Current
f
toggle
= 15MHz Outputs Open
Absolute Maximum Ratings
(1)
Supply voltage Vcc ....................................... 0.5 to+7V
Input voltage applied .......................... 2.5 to
V
CC
+1.0V
Off-state output voltage applied ......... 2.5 to
V
CC
+1.0V
Storage Temperature ............................... 65 to 150
C
Ambient Temperature with
Power Applied .......................................... 55 to 125
C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while pro-
gramming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
Specifications
GAL20XV10
9
COM
t
pd
A
Input or I/O to Combinatorial Output
3
10
3
15
3
20
ns
t
co
A
Clock to Output Delay
2
7
2
8
2
10
ns
t
cf
2
--
Clock to Feedback Delay
--
4
--
4
--
4
ns
t
su
--
Setup Time, Input or Feedback before Clock
6
--
8
--
10
--
ns
t
h
--
Hold Time, Input or Feedback after Clock
0
--
0
--
0
--
ns
A
Maximum Clock Frequency with
76.9
--
62.5
--
50
--
MHz
External Feedback, 1/(tsu + tco)
A
Maximum Clock Frequency with
100
--
83.3
--
71.4
--
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
100
--
83.3
--
71.4
--
MHz
No Feedback
t
wh
--
Clock Pulse Duration, High
4
--
6
--
7
--
ns
t
wl
--
Clock Pulse Duration, Low
4
--
6
--
7
--
ns
B
Input or I/O to Output Enabled
3
10
3
15
3
20
ns
B
OE to Output Enabled
2
9
2
10
2
15
ns
C
Input or I/O to Output Disabled
3
9
3
15
3
20
ns
C
OE to Output Disabled
2
9
2
10
2
15
ns
PARAMETER
UNITS
-20
MIN. MAX.
TEST
COND.
1
DESCRIPTION
-15
MIN. MAX.
f
max
3
t
en
t
dis
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
-10
MIN. MAX.
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 5.0V, V
I
= 2.0V
C
I/O
I/O Capacitance
8
pF
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested
COM
COM
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (T
A
= 25
C, f = 1.0 MHz)
Specifications
GAL20XV10
10
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATORIAL
OUTPUT
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
s u
t
c o
t
h
(external fdbk)
1 /
f
m a x
Registered Output
Combinatorial Output
OE
OUTPUT
t
en
t
dis
OE
OE
OE
OE
OE
to Output Enable/Disable
CLK
(w/o fdbk)
1 /
f
m a x
t
w l
t
w h
Clock Width
(Vref Typical = 3.2V)
(Vref Typical = 3.2V)
Typical Input
Typical Output
CLK
REGISTERED
FEEDBACK
t
cf
t
su
1/
f
max (internal fdbk)
fmax with Feedback
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
Input or I/O Feedback to Enable/Disable
Switching Waveforms
Input/Output Equivalent Schematics
Specifications
GAL20XV10
11
f
max with Internal Feedback 1/(
t
su+
t
cf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
f
max with External Feedback 1/(
t
su+
t
co)
Note: fmax with external feedback is calculated from measured
tsu and tco.
REGISTER
LOGIC
ARRAY
CLK
t
su +
t
h
f
max with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns 10% 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
R
1
R
2
C
L
300
390
50pF
Active High
390
50pF
Active Low
300
390
50pF
Active High
390
5pF
Active Low
300
390
5pF
C
B
A
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
f
max Descriptions
Switching Test Conditions
Specifications
GAL20XV10
12
Electronic Signature
An electronic signature word is provided in every GAL20XV10
device. It contains 40 bits of reprogrammable memory that con-
tains user defined data. Some uses include user ID codes, revi-
sion numbers, pattern identification or inventory control codes. The
signature data is always available to the user independent of the
state of the security cell.
NOTE: The electronic signature bits, if programmed to any value
other then zero(0) will alter the checksum of the device.
Security Cell
A security cell is provided in every GAL20XV10 device as a deter-
rent to unauthorized copying of the device pattern. Once pro-
grammed, this cell prevents further read access of the device
pattern information. This cell can be only be reset by reprogram-
ming the device. The original pattern can never be examined once
this cell is programmed. The Electronic Signature is always avail-
able regardless of the security cell state.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers. Complete programming of the device takes less than a
second. Erasing of the device is transparent to the user, and is done
automatically as part of the programming cycle.
Latch-Up Protection
GAL20XV10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
Input Buffers
GAL20XV10 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than bi-
polar TTL devices.
GAL20XV10 input buffers have active pull-ups within their input
structure. This pull-up will cause any un-terminated input or
I/O to float to a TTL high (logical 1). Lattice Semiconductor
recommends that all unused inputs and tri-stated I/O pins be
connected to another active input, Vcc, or GND. Doing this will tend
to improve noise immunity and reduce Icc for the device.
Typical Input Pull-up Characteristic
1.0
2.0
3.0
4.0 5.0
-60
0
-20
-40
0
Input Voltage (Volts)
Input Current (
A)
Circuitry within the GAL20XV10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q outputs
set low after a specified time (
t
pr, 1
s MAX). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature
of system power-up, some conditions must be met to provide a valid
power-up reset of the GAL20XV10. First, the V
CC
rise must be
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of
t
pr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Power-Up Reset
Specifications
GAL20XV10
13
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
4.50
4.75
5.00
5.25
5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
9
10
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-2
-1.5
-1
-0.5
0
1
2
3
4
5
6
7
8
9
10
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-2
0
2
4
6
8
10
12
0
50
100
150
200
250
300
RISE
FALL
Typical AC and DC Characteristic Diagrams
Specifications
GAL20XV10
14
Vol vs Iol
Iol (mA)
Vol (V)
0
0.5
1
1.5
2
2.5
3
0.00
20.00
40.00
60.00
80.00
100.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
1
2
3
4
5
0.00
10.00
20.00
30.00
40.00
50.00
60.00
Voh vs Ioh
Ioh(mA)
Voh (V)
3.5
3.75
4
4.25
4.5
0.00
1.00
2.00
3.00
4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.80
0.90
1.00
1.10
1.20
4.50
4.75
5.00
5.25
5.50
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.8
0.9
1
1.1
1.2
-55
-25
0
25
50
75
100
125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
0
25
50
75
100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
2
4
6
8
10
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
20
40
60
80
100
120
-2.00
-1.50
-1.00
-0.50
0.00
Typical AC and DC Characteristic Diagrams
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