ispLSI

2032VL

2.5V In-System Programmable

SuperFASTTM High Density PLD

2032vl_02

Features

· SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC
-- 1000 PLD Gates
-- 32 I/O Pins, Two Dedicated Inputs
-- 32 Registers
-- High Speed Global Interconnect
-- Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

-- Small Logic Block Size for Random Logic
-- 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2032V and 2032VE Devices

· 2.5V LOW VOLTAGE 2032 ARCHITECTURE

-- Interfaces With Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)

-- 45 mA Typical Active Current

· HIGH PERFORMANCE E

CMOS

TECHNOLOGY

max = 180 MHz Maximum Operating Frequency

pd = 5.0 ns Propagation Delay

-- Electrically Erasable and Reprogrammable
-- Non-Volatile
-- 100% Tested at Time of Manufacture
-- Unused Product Term Shutdown Saves Power

· IN-SYSTEM PROGRAMMABLE

-- 2.5V In-System Programmability (ISPTM) Using

Boundary Scan Test Access Port (TAP)

-- Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic

-- Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

-- Reprogram Soldered Devices for Faster Prototyping

· 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

· THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
-- Synchronous and Asynchronous Clocks
-- Programmable Output Slew Rate Control
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global

Interconnectivity

· ispDesignEXPERTTM LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
-- Superior Quality of Results
-- Tightly Integrated with Leading CAE Vendor Tools
-- Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZERTM

-- PC and UNIX Platforms

Functional Block Diagram

Global Routing Pool

(GRP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

GLB

Logic

Array

D Q

0139Bisp/2000

Description

The ispLSI 2032VL is a High Density Programmable
Logic Device containing 32 Registers, 32 Universal I/O
pins, two Dedicated Input Pins, three Dedicated Clock
Input Pins, one dedicated Global OE input pin and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2032VL features in-system programmability
through the Boundary Scan Test Access Port (TAP) and
is 100% IEEE 1149.1 Boundary Scan Testable. The
ispLSI 2032VL offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.

The basic unit of logic on the ispLSI 2032VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

September 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications

ispLSI 2032VL

Functional Block Diagram

Figure 1. ispLSI 2032VL Functional Block Diagram

The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control, and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 3.3 Volt signal levels
to support mixed-voltage systems.

Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORPs. Each
ispLSI 2032VL device contains one Megablock.

The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.

Clocks in the ispLSI 2032VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the
outputs of the ispLSI 2032VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.

Global Routing Pool

(GRP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

CLK 0

CLK 1

CLK 2

GOE 0

Note: *Y1 and RESET are multiplexed on the same pin

I/O 0
I/O 1

I/O 2

I/O 3

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13
I/O 14

I/O 15

I/O 31

I/O 30

I/O 29
I/O 28

I/O 27

I/O 26
I/O 25

I/O 24

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 18

I/O 17

I/O 16

TDI/IN 0

TDO/IN 1

I/O 4

I/O 5

Y1*

TCK/Y2

BSCAN

TMS/NC

0139B/2032VL

Generic Logic

Blocks (GLBs)

Specifications

ispLSI 2032VL

Absolute Maximum Ratings

Supply Voltage V

................................ -0.5 to +4.05V

Input Voltage Applied ............................. -0.5 to +4.05V

Off-State Output Voltage Applied .......... -0.5 to +4.05V

Storage Temperature .............................. -65 to +150

Case Temp. with Power Applied .............. -55 to 125

Max. Junction Temp. (T

) with Power Applied ... 150

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).

SYMBOL

Table 2-0006/2032VL

PARAMETER

I/O Capacitance

UNITS

TYPICAL

TEST CONDITIONS

Dedicated Input Capacitance

V = 2.5V, V = 0.0V

I/O

Clock Capacitance

V = 2.5V, V = 0.0V

= 0

C to + 70

= -40

C to + 85

SYMBOL

Table 2-0005/2032VL

PARAMETER

Supply Voltage

Input High Voltage

Input Low Voltage

MIN.

MAX.

UNITS

2.3

1.7

-0.3

2.7

3.6

0.7

Commercial

Industrial

Erase Reprogram Specifications

Table 2-0008A/2032VL

PARAMETER

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10,000

Cycles

Capacitance (T

=25

C, f=1.0 MHz)

DC Recommended Operating Condition

Specifications

ispLSI 2032VL

Switching Test Conditions

Input Pulse Levels

Table 2-0003/2032VL

Input Rise and Fall Time
10% to 90%

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to V

See Figure 2

3-state levels are measured 0.15V from
steady-state active level.

1.5 ns

Output Load Conditions (see Figure 2)

Figure 2. Test Load

Device
Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

0213A/2032VL

TEST CONDITION

250

218

35pF

218

35pF

250

35pF

Active High

Active Low

250

5pF

218

5pF

Active Low to Z
at V +0.15V

Active High to Z
at V -0.15V

Table 2-0004A/2032VL

SYMBOL

1. One output at a time for a maximum duration of one second. V

OUT

= 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using two 16-bit counters.
3. Typical values are at V

= 2.5V and T

= 25

4. Maximum I

varies widely with specific device configuration and operating frequency. Refer to Power Consumption

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I

5. With no pull-up resistors.

Table 2-0007/2032VL

IL-isp

PARAMETER

IL-PU

2, 4

Output Low Voltage

Output High Voltage

Input or I/O High Leakage Current

Input or I/O Low Leakage Current

BSCAN

Input Pull-Up Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

= 100

V (Max.)

V = 2.5V, V = 0.5V

V = 0.0V, V = 2.5V

f = 1 MHz

IN IL

CC OUT

CLK

IL IH

CONDITION

MIN.

TYP.

MAX.

UNITS

2.0

0.2

-10

-150

-100

(min)

3.6V

= 8mA

= -1mA

- 0.2

= -100

1.8

= -4mA

0.4

DC Electrical Characteristics

Over Recommended Operating Conditions

Specifications

ispLSI 2032VL

External Timing Parameters

Over Recommended Operating Conditions

pd1

UNITS

-135

MIN.

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.

Table 2-0030B/2032VL

1
tsu2 + tco1

( )

-110

MIN.

MAX.

DESCRIPTION

PARAMETER

Data Propagation Delay, 4PT Bypass, ORP Bypass

7.5

10.0

pd2

Data Propagation Delay

max

Clock Frequency with Internal Feedback

135

110

MHz

max (Ext.)

Clock Frequency with External Feedback

MHz

max (Tog.)

Clock Frequency, Max. Toggle

MHz

su1

GLB Reg. Setup Time before Clock, 4 PT Bypass

co1

GLB Reg. Clock to Output Delay, ORP Bypass

GLB Reg. Hold Time after Clock, 4 PT Bypass

0.0

su2

GLB Reg. Setup Time before Clock

5.5

co2

GLB Reg. Clock to Output Delay

GLB Reg. Hold Time after Clock

0.0

Ext. Reset Pin to Output Delay, ORP Bypass

rw1

Ext. Reset Pulse Duration

5.0

ptoeen

Input to Output Enable

ptoedis

Input to Output Disable

goeen

Global OE Output Enable

goedis

Global OE Output Disable

External Synchronous Clock Pulse Duration, High

3.0

External Synchronous Clock Pulse Duration, Low

3.0

100

167

4.0

4.5

5.5

8.0

12.0

6.0

10.0

80.0

125

5.5

0.0

7.5

0.0

6.5

4.0

13.0

5.0

6.0

12.5

14.5

7.0

-180

MIN. MAX.

5.0

180

118

200

3.0

0.0

4.5

0.0

4.0

2.5

7.5

4.0

5.0

6.0

10.0

5.0

Specifications

ispLSI 2032VL

Internal Timing Parameters

Over Recommended Operating Conditions

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.

Table 2-0036B/2032VL

Inputs

UNITS

-135

MIN.

-110

MIN.

MAX.

DESCRIPTION

PARAMETER

20 Input Buffer Delay

0.9

din

21 Dedicated Input Delay

2.7

grp

22 GRP Delay

1.8

GLB

1ptxor

25 1 Product Term/XOR Path Delay

5.7

20ptxor

26 20 Product Term/XOR Path Delay

5.7

xoradj

27 XOR Adjacent Path Delay

5.7

gbp

28 GLB Register Bypass Delay

1.0

gsu

29 GLB Register Setup Time before Clock

1.2

30 GLB Register Hold Time after Clock

4.3

gco

31 GLB Register Clock to Output Delay

0.3

gro

32 GLB Register Reset to Output Delay

2.8

ptre

33 GLB Product Term Reset to Register Delay

8.9

ptoe

34 GLB Product Term Output Enable to I/O Cell Delay

6.9

ptck

35 GLB Product Term Clock Delay

2.3

4.3

ORP

38 Output Buffer Delay

1.8

39 Output Slew Limited Delay Adder

2.0

0.5

1.7

GRP

1.2

4ptbpc

23 4 Product Term Bypass Path Delay (Combinatorial)

4.7

4ptbpr

24 4 Product Term Bypass Path Delay (Registered)

3.7

4.7

0.5

3.7

3.2

1.2

2.8

0.3

1.1

7.1

6.3

2.1

5.0

orp

36 ORP Delay

1.8

orpbp

37 ORP Bypass Delay

0.8

1.5

0.5

Outputs

1.6

2.0

oen

40 I/O Cell OE to Output Enabled

4.9

odis

41 I/O Cell OE to Output Disabled

4.9

4.0

goe

42 Global Output Enable

2.1

2.0

gy0

43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

2.1

gy1/2

44 Clock Delay, Y1 or Y2 to Global GLB Clock Line

2.3

Clocks

2.1

2.3

45 Global Reset to GLB

7.1

Global Reset

4.8

-180

MIN. MAX.

0.5

1.1

0.6

2.9

0.0

1.7

1.3

0.3

0.1

5.3

5.4

1.1

4.1

1.8

2.0

1.4

1.7

0.7

3.5

1.5

1.2

1.4

3.4

Specifications

ispLSI 2032VL

ispLSI 2032VL Timing Model

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

Reg 4 PT Bypass

20 PT

XOR Delays

Control
PTs

I/O Pin

(Input)

Y0,1,2

GRP

GLB Reg Bypass

ORP Bypass

RST

I/O Delay

I/O Cell

ORP

GLB

GRP

I/O Cell

#24

#25, 26, 27

#33, 34,

#43, 44

#36

Reset

Ded. In

#21

#20

#28

#29, 30,

31, 32

#38,

GOE 0

#42

#40, 41

0491/2032VL

#22

Comb 4 PT Bypass #23

#37

#45

Derivations of

su,

h and

co from the Product Term Clock

=
=
=
=

3.5ns

2.5ns

9.0ns

Logic + Reg su - Clock (min)
(

io +

grp +

20ptxor) + (

gsu) - (

io +

grp +

ptck(min))

(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.6 + 2.9) + (1.7) - (0.5 + 0.6 + 1.1)

=
=
=
=

Clock (max) + Reg h - Logic
(

io +

grp +

ptck(max)) + (

gh) - (

io +

grp +

20ptxor)

(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.6 + 4.1) + (1.3) - (0.5 + 0.6 + 2.9)

=
=
=
=

Clock (max) + Reg co + Output
(

io +

grp +

ptck(max)) + (

gco) + (

orp +

ob)

(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.6 + 4.1) + (0.3) + (1.7 + 1.8)

Table 2-0042/2032VL

Note: Calculations are based on timing specifications for the ispLSI 2032VL-180L.

Specifications

ispLSI 2032VL

Power Consumption

Power consumption in the ispLSI 2032VL device de-
pends on two primary factors: the speed at which the
device is operating and the number of product terms

used. Figure 3 shows the relationship between power
and operating speed.

Figure 3. Typical Device Power Consumption vs fmax

0127A/2032VL

ICC can be estimated for the ispLSI 2032VL using the following equation:

ICC(mA)

= 6 + (# of PTs * 0.63) + (# of nets * Max freq * 0.002)

Where:
# of PTs = Number of product terms used in design
# of nets = Number of signals used in device
Max freq = Highest clock frequency to the device (in MHz)

The ICC estimate is based on typical conditions (VCC = 2.5V, room temperature) and an assumption of two

GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to

operating conditions and the program in the device, the actual ICC should be verified.

Notes: Configuration of two 16-bit counters

Typical current at 2.5V, 25

120

150

180

max (MHz)

CC (mA)

ispLSI 2032VL

Specifications

ispLSI 2032VL

Signal Descriptions

GOE 0

Global Output Enable Pin

Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the
device.

RESET

/Y1

This pin performs two functions: (1) Dedicated clock input. This clock input is brought into the Clock
Distribution Network and can optionally be routed to any GLB and/or I/O cell on the device. (2) Active
Low (0) Reset pin which resets all of the GLB and I/O registers in the device.

BSCAN

Input Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.

TDI/IN 0

Input This pin performs two functions. When

BSCAN

is logic low, it functions as an input pin to load

programming data into the device. When

BSCAN

is high, it functions as a dedicated input pin.

TMS/NC

Input When

BSCAN

is logic low, this pin functions as a mode control pin for the Boundary Scan State

Machine.

TDO/IN 1

Output/Input This pin performs two functions. When

BSCAN

is logic low, it functions as an output pin

pin to read serial shift register data. When

BSCAN

is high, it functions as a dedicated input pin.

TCK/Y2

Input This pin performs two functions. When

BSCAN

is logic low, it functions as a clock pin for the

Serial Shift Register. When

BSCAN

is high, it functions as a dedicated clock input. This clock input is

brought into the Clock Distribution Network and can optionally be routed to any GLB.

GND

Ground (GND)

VCC

Vcc

No Connect

I/O

Input/Output pins These are the general purpose I/O pins used by the logic array.

Signal Name Description

GOE 0

RESET

/Y1

BSCAN

TDI/IN 0

TMS/NC

TDO/IN 1

TCK/Y2

GND

17, 39

1, 23

18, 42

C4, E4

VCC

6, 28

12, 34

6, 30

D3, D5

12, 24, 36, 48

A1, A7, D4, G1, G7

Signal

44-Pin TQFP

44-Pin PLCC

48-Pin TQFP

49-Ball caBGA

1. NC pins are not to be connected to any active signals, VCC or GND.

Signal Locations

I/O Locations

Signal

44-Pin TQFP

44-Pin PLCC

48-Pin TQFP

49-Ball caBGA

I/O 0 - I/O 6

9, 10, 11, 12, 13, 14, 15

15, 16, 17, 18, 19, 20, 21

9, 10, 11, 13, 14, 15, 16

E1, F2, F1, E3, F3, G2, F4

I/O 7 - I/O 13

16, 19, 20, 21, 22, 23, 24

22, 25, 26, 27, 28, 29, 30

17, 20, 21, 22, 23, 25, 26

G3, F5, G5, F6, G6, E5, E6

I/O 14 - I/O 20

25, 26, 31, 32, 33, 34, 35

31, 32, 37, 38, 39, 40, 41

27, 28, 33, 34, 35, 37, 38

F7, D6, C7, B6, B7, C5, B5

I/O 21 - I/O 27

36, 37, 38, 41, 42, 43, 44

42, 43, 44, 3, 4, 5, 6

39, 40, 41, 44, 45, 46, 47

A6, B4, A5, B3, A3, B2, A2

I/O 28 - I/O 31

1, 2, 3, 4

7, 8, 9, 10

1, 2, 3, 4

C3, C2, B1, D2

Specifications

ispLSI 2032VL

Pin Configuration

ispLSI 2032VL 44-Pin PLCC Pinout Diagram

Pin Configuration

ispLSI 2032VL 44-Pin TQFP Pinout Diagram

I/O 18

I/O 17

I/O 16

TMS/NC

RESET/Y1

VCC

TCK/Y2

I/O 15

I/O 14

I/O 13

I/O 12

I/O 28

I/O 29

I/O 30

I/O 31

VCC

BSCAN

TDI/IN 0

I/O 0

I/O 1

I/O 2

I/O 27

I/O 26

I/O 25

I/O 24

GOE 0

GND

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

GND

TDO/IN 1

I/O 8

I/O 9

I/O 10

I/O 11

1. NC pins are not to be connected to any active signals, VCC or GND.

ispLSI 2032VL

Top View

0123/2032VL

I/O 18

I/O 17

I/O 16

TMS/NC

RESET/Y1

VCC

TCK/Y2

I/O 15

I/O 14

I/O 13

I/O 12

I/O 28

I/O 29

I/O 30

I/O 31

VCC

BSCAN

TDI/IN 0

I/O 0

I/O 1

I/O 2

I/O 27

I/O 26

I/O 25

I/O 24

GOE 0

GND

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

GND

TDO/IN 1

I/O 8

I/O 9

I/O 10

I/O 11

ispLSI 2032VL

Top View

0851/2032VL

1. NC pins are not to be connected to any active signals, VCC or GND.

Specifications

ispLSI 2032VL

Signal Configuration

ispLSI 2032VL 49-Ball caBGA Signal Diagram

I/O

TMS/

TCK/

I/O

GND

I/O

TDO/

IN1

I/O

1. NCs are not to be connected to any active signals, VCC or GND.

Note: Ball A1 indicator dot on top side of package.

I/O

49-BGA/2032VL

RESET

VCC

I/O

TDI/

IN0

GOE

BSCAN

I/O

GND

Bottom View

ispLSI 2032VL

Pin Configuration

ispLSI 2032VL 48-Pin TQFP Pinout Diagram

I/O 18

I/O 17

I/O 16

TMS/NC

RESET/Y1

VCC

TCK/Y2

I/O 15

I/O 14

I/O 13

I/O 12

I/O 28

I/O 29

I/O 30

I/O 31

VCC

BSCAN

TDI/IN 0

I/O 0

I/O 1

I/O 2

I/O 27

I/O 26

I/O 25

I/O 24

GOE 0

GND

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

GND

TDO/IN 1

I/O 8

I/O 9

I/O 10

I/O 11

ispLSI 2032VL

Top View

48TQFP/2032VL

1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, V

or GND.

Specifications

ispLSI 2032VL

Part Number Description

ispLSI 2032VL Ordering Information

Device Number
2032VL

ispLSI 2032VL XXX

XXX

Grade
Blank = Commercial
I = Industrial

Speed
180 = 180 MHz

max

135 = 135 MHz

max

110 = 110 MHz

max

Power
L = Low

Package
T44 = 44-Pin TQFP
T48 = 48-Pin TQFP
J44 = 44-Pin PLCC
B49 = 49-Ball caBGA

Device Family

0212A/2032VL

135

44-Pin TQFP

7.5

ispLSI 2032VL-135LT44

135

48-Pin TQFP

7.5

ispLSI 2032VL-135LT48

135

44-Pin PLCC

7.5

ispLSI 2032VL-135LJ44

135

49-Ball caBGA

7.5

ispLSI 2032VL-135LB49

110

44-Pin PLCC

ispLSI 2032VL-110LJ44

110

49-Ball caBGA

ispLSI 2032VL-110LB49

110

44-Pin TQFP

ispLSI 2032VL-110LT44

110

48-Pin TQFP

ispLSI 2032VL-110LT48

Table 2-0041A/2032VL

180

5.0

44-Pin PLCC

ispLSI 2032VL-180LJ44

180

5.0

49-Ball caBGA

ispLSI 2032VL-180LB49

ispLSI

180

44-Pin TQFP

5.0

ispLSI 2032VL-180LT44

180

48-Pin TQFP

5.0

ispLSI 2032VL-180LT48

FAMILY

fmax (MHz)

ORDERING NUMBER

PACKAGE

tpd (ns)

COMMERCIAL

Table 2-0041A/2032VL

ispLSI

135

44-Pin TQFP

7.5

ispLSI 2032VL-135LT44I

FAMILY

fmax (MHz)

ORDERING NUMBER

PACKAGE

tpd (ns)

INDUSTRIAL

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ispLSI2032VL-135LT48

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ispLSI2032VL-135LT48

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ispLSI2032VL-135LT48