www.latticesemi.com
1
clk5600_01
November 2004
Preliminary Data Sheet
2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
ispClock 5600 Family
In-System Programmable, Zero-Delay Clock Generator
with Universal Fan-Out Buffer
TM
Features
10MHz to 320MHz Input/Output Operation
Low Output to Output Skew (<50ps)
Low Jitter Peak-to-Peak (<60ps)
Up to 20 Programmable Fan-out Buffers
Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS,
LVPECL
Programmable output impedance
- 40 to 70
in 5
increments
Programmable slew rate
Up to 10 banks with individual V
CCO
and GND
- 1.5V, 1.8V, 2.5V, 3.3V
Fully Integrated High-Performance PLL
Programmable lock detect
Multiply and divide ratio controlled by
- Input divider (5 bits)
- Feedback divider (5 bits)
- Five output dividers (5 bits)
Programmable On-chip Loop Filter
Precision Programmable Phase Adjustment
(Skew) Per Output
16 settings; minimum step size 195ps
- Locked to VCO frequency
Up to +/- 12ns skew range
Coarse and fine adjustment modes
Up to Five Clock Frequency Domains
Flexible Clock Reference and External
Feedback Inputs
Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL
Clock A/B selection multiplexer
Feedback A/B selection multiplexer
Programmable termination
Four User-programmable Profiles Stored in
E
2
CMOS
Memory
Supports both test and multiple operating
configurations
Full JTAG Boundary Scan Test In-System
Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0 to 70C) and Industrial
(-40 to 85C) Temperature Ranges
100-pin and 48-pin TQFP Packages
Applications
Circuit board common clock generation and
distribution
PLL-based frequency generation
High fan-out clock buffer
Zero-delay clock buffer
Product Family Block Diagram
VCO
OUTPUT
DRIVERS
SKEW
CONTROL
CL
O
C
K O
U
T
P
U
T
S
RE
F
E
RE
NC
E
IN
P
U
TS
JTAG
INTERFACE
&
E
2
CMOS
MEMORY
LOCK DETECT
FILTER
PHASE/
FREQUENCY
DETECTOR
1
0
2
3
Multiple Profile
Management Logic
INTERNAL FEEDBACK PATH
PLL CORE
OUTPUT
ROUTING
MATRIX
V0
V1
V2
V3
V4
OUTPUT
DIVIDERS
*
*
* Input Available only on ispClock5620
BYPASS
MUX
FE
E
D
B
A
C
K
IN
P
U
TS
Internal/External
Feedback
Select
M
N
Lattice Semiconductor
ispClock5600 Family Data Sheet
2
General Description and Overview
The ispClock5610 and ispClock5620 are in-system-programmable high-fanout PLL-based clock drivers designed
for use in high performance communications and computing applications. The ispClock5610 provides up to 10 sin-
gle-ended or five differential clock outputs, while the ispClock5620 provides up to 20 single-ended or 10 differential
clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS,
LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro-
grammable control of termination, slew-rate, and timing skew. All configuration information is stored on-chip in non-
volatile E
2
CMOS memory.
The ispClock5600's PLL and divider systems supports the synthesis of clock frequencies differing from that of the
reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-divid-
ers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feedback
may be taken internally from the output of any of the five V-dividers, or externally through FBKA+/- or FBKB+/- pins.
The core functions of all members of the ispClock5600 family are identical, the differences between devices being
restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional
block diagrams of the ispClock5610 and ispClock5620.
Table 1. ispClock5600 Family Members
Figure 1. ispClock5610 Functional Block Diagram
Device
Ref. Input Pairs
Feedback Input Pairs
Clock Outputs
ispClock5610
1
1
10
ispClock5620
2
2
20
VCO
LOOP
FILTER
PHASE
DETECT
LOCK
DETECT
M
N
INPUT
DIVIDER
FEEDBACK
SKEW ADJUST
1
0
FEEDBACK
DIVIDER
GOE
OEX
LOCK
PLL_BYPASS
JTAG INTERFACE
OEY
TDI
TMS
TCK
TDO
SGATE
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_5A
BANK_5B
BANK_7A
BANK_7B
OUTPUT
DIVIDERS
OUTPUT ROUTING
MATRIX
RESET
V1
V2
V0
V3
V4
BANK_0A
BANK_0B
BANK_2A
BANK_2B
BANK_4A
BANK_4B
PS0
PS1
Profile Select
Control
0
1
2
3
OUTPUT ENABLE CONTROLS
(1-32)
(1-32)
(2-64)
(2-64)
(2-64)
(2-64)
(2-64)
REFA+
REFA-
REFVTT
FBKA+
FBKA -
FBKVTT
E
2
Configuration
Lattice Semiconductor
ispClock5600 Family Data Sheet
4
Absolute Maximum Ratings
ispClock5600V
Core Supply Voltage V
CCD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
PLL Supply Voltage V
CCA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
JTAG Supply Voltage V
CCJ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Output Driver Supply Voltage V
CCO
. . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Output Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C
Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130C
1. When applied to an output when in high-Z condition
Recommended Operating Conditions
Recommended Operating Conditions V
CCO
vs. Logic Standard
E
2
CMOS Memory Write/Erase Characteristics
Symbol
Parameter
Conditions
ispClock5600V
Units
Min.
Max.
V
CCD
Core Supply Voltage
3.0
3.6
V
V
CCJ
JTAG I/O Supply Voltage
1.62
3.6
V
V
CCA
Analog Supply Voltage
3.0
3.6
V
V
CCXSLEW
V
CC
Turn-on Ramp Rate
All supply pins
--
0.33
V/s
T
JOP
Operating Junction Temperature
Commercial
0
100
C
Industrial
-40
115
T
A
Ambient Operating Temperature
Commercial
0
70
1
C
Industrial
-40
85
1
1. Device power dissipation may also limit maximum ambient operating temperature.
V
CCO
(V)
V
REF
(V)
V
TT
(V)
Logic Standard
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
LVTTL
3.0
3.3
3.6
--
--
--
--
--
--
LVCMOS 1.8V
1.71
1.8
1.89
--
--
--
--
--
--
LVCMOS 2.5V
2.375
2.5
2.625
--
--
--
--
--
--
LVCMOS 3.3V
3.0
3.3
3.6
--
--
--
--
--
--
SSTL2 Class 1
2.375
2.5
2.625
1.15
1.25
1.35
V
REF
- 0.04
--
V
REF
+ 0.04
SSTL3 Class 1
3.0
3.3
3.6
1.30
1.50
1.70
V
REF
- 0.05
V
REF
V
REF
+ 0.05
HSTL Class 1
1.425
1.5
1.575
0.68
0.75
0.90
--
0.5 x V
CCO
--
LVPECL (Differential)
3.0V
3.3V
3.6V
--
--
--
--
--
--
LVDS
V
CCO
= 2.5V
2.375
2.5V
2.625
--
--
--
--
--
--
V
CCO
= 3.3V
3.0
3.3
3.6
--
--
--
--
--
--
Note: `--' denotes V
REF
or V
TT
not applicable to this logic standard
Parameter
Conditions
Min.
Typ.
Max.
Units
Erase/Reprogram Cycles
1000
--
--
Lattice Semiconductor
ispClock5600 Family Data Sheet
5
Performance Characteristics Power Supply
DC Electrical Characteristics Single-ended Logic
DC Electrical Characteristics LVDS
Symbol
Parameter
Conditions
Typ.
Max.
Units
I
CCD
Core Supply Current
f
VCO
= 640MHz
150
160
mA
I
CCA
Analog Supply Current
f
VCO
= 640MHz
5.5
7
mA
I
CCO
Output Driver Supply Current
(per Bank)
V
CCO
= 1.8V
1
, LVCMOS
V
CCO
= 2.5V
1
, LVCMOS
V
CCO
= 3.3V
1
, LVCMOS
V
CCO
= 3.3V
2
, LVDS
13
18
24
7.5
15
24
35
8
mA
I
CCJ
JTAG I/O Supply Current (static)
V
CCJ
= 1.8V
V
CCJ
= 2.5V
V
CCJ
= 3.3V
200
300
300
300
400
400
A
1. Supply current consumed by each bank, both outputs active, 18pF load, 320MHz output frequency.
2. Supply current consumed by each bank, 100
, 5pf differential load, 320MHz output frequency.
Logic Standard
V
IL
(V)
V
IH
(V)
V
OL
Max. (V) V
OH
Min. (V)
I
OL
(mA)
I
OH
(mA)
Min.
Max.
Min.
Max.
LVTTL/LVCMOS 3.3V
-0.3
0.8
2
3.6
0.4
V
CCO
- 0.4
4
1
-4
1
LVCMOS 1.8V
-0.3
0.35V
CCO
0.65V
CCO
3.6
0.4
V
CCO
- 0.4
4
1
-4
1
LVCMOS 2.5V
-0.3
0.7
1.7
3.6
0.4
V
CCO
- 0.4
4
1
-4
1
SSTL2 Class 1
-0.3
V
REF
- 0.18 V
REF
+ 0.18
3.6
0.54
2
V
CCO
- 0.81
2
7.6
-7.6
SSTL3 Class 1
-0.3
V
REF
- 0.2
V
REF
+ 0.2
3.6
0.9
2
V
CCO
- 1.3
2
8
-8
HSTL Class 1
-0.3
V
REF
- 0.1
V
REF
+ 0.1
3.6
0.4
3
V
CCO
- 0.4
3
8
-8
1. Specified for 50
internal series output termination.
2. Specified for 40
internal series output termination.
3. Specified for
20
internal series output termination.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
V
ICM
Common Mode Input Voltage
0.05
--
2.35
V
V
THD
Differential Input Threshold
100
--
--
mV
V
IN
Input Voltage
0
--
2.4
V
V
OH
Output High Voltage
R
T
= 100
--
1.375
1.60
V
V
OL
Output Low Voltage
R
T
= 100
0.9
1.03
--
V
V
OD
Output Voltage Differential
R
T
= 100
250
400
480
mV
V
OD
Change in V
OD
between H and L
--
--
50
mV
V
OS
Output Voltage Offset
Common Mode Output Voltage
1.125
1.20
1.375
V
V
OS
Change in V
OS
Between H and L
--
--
50
mV
I
SA
Output Short Circuit Current
V
OD
= 0V, Outputs Shorted to GND
--
--
24
mA
I
SAB
Output Short Circuit Current
V
OD
= 0V, Outputs Shorted to Each Other
--
--
12
mA
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