www.latticesemi.com
1
xpga_09
ispXPGA
Family
July 2004
Preliminary Data Sheet
2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Includes
High-
Performanc
e,
Low-Cost
"E-Series"
Non-volatile, Infinitely Reconfigurable
Instant-on - Powers up in microseconds via
on-chip E
2
CMOS
based memory
No external configuration memory
Excellent design security, no bit stream to intercept
Reconfigure SRAM based logic in milliseconds
High Logic Density for System-level
Integration
139K to 1.25M system gates
160 to 496 I/O
1.8V, 2.5V, and 3.3V V
CC
operation
Up to 414Kb sysMEMTM embedded memory
High Performance Programmable Function
Unit (PFU)
Four LUT-4 per PFU supports wide and narrow
functions
Dual flip-flops per LUT-4 for extensive pipelining
Dedicated logic for adders, multipliers, multiplex-
ers, and counters
Flexible Memory Resources
Multiple sysMEM Embedded RAM Blocks
Single port, Dual port, and FIFO operation
64-bit distributed memory in each PFU
Single port, Double port, FIFO, and Shift
Register operation
Flexible Programming, Reconfiguration,
and Testing
Supports IEEE 1532 and 1149.1
Microprocessor configuration interface
Program E
2
CMOS while operating from SRAM
Eight sysCLOCKTM Phase Locked Loops
(PLLs) for Clock Management
True PLL technology
10MHz to 320MHz operation
Clock multiplication and division
Phase adjustment
Shift clocks in 250ps steps
sysIOTM for High System Performance
High speed memory support through SSTL and
HSTL
Advanced buses supported through PCI, GTL+,
LVDS, BLVDS, and LVPECL
Standard logic supported through LVTTL,
LVCMOS 3.3, 2.5 and 1.8
5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
Programmable drive strength for series termination
Programmable bus maintenance
Two Options Available
High-performance sysHSI (standard part number)
Low-cost, no sysHSI ("E-Series")
sysHSITM Capability for Ultra Fast Serial
Communications
Up to 800Mbps performance
Up to 20 channels per device
Built in Clock Data Recovery (CDR) and
Serialization and De-serialization (SERDES)
Table 1. ispXPGA Family Selection Guide
ispXPGA 125/E
ispXPGA 200/E
ispXPGA 500/E
ispXPGA 1200/E
System Gates
139K
210K
476K
1.25M
PFUs
484
676
1764
3844
LUT-4s
1936
2704
7056
15376
Logic FFs
3.8K
5.4K
14.1K
30.7K
sysMEM Memory
92K
111K
184K
414K
Distributed Memory
30K
43K
112K
246K
EBR
20
24
40
90
sysHSI Channels
1
4
8
12
20
User I/O
160/176
160/208
336
496
Packaging
256 fpBGA
516 fpBGA
2
256 fpBGA
516 fpBGA
2
516 fpBGA
2
900 fpBGA
680 fpSBGA
2
900 fpBGA
1. "E-Series" does not support sysHSI.
2. Thermally enhanced package.
Lattice Semiconductor
ispXPGA Family Data Sheet
2
ispXPGA Family Overview
The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that
are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either re-
programmable or non-volatile. This family couples this capability with a mainstream architecture containing the fea-
tures required for today's system-level design.
The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost "E-Series" supports the same high-performance FPGA fabric without the
sysHSI Block.
Electrically Erasable CMOS (E
2
CMOS) memory cells provide the ispXPGA family with non-volatile capability.
These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-
tions. This capability also means that expensive external configuration memories are not required and that designs
can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if
desired. Both the SRAM and E
2
CMOS cells can be programmed and verified through the IEEE 1532 industry stan-
dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIGTM peripheral port.
The family spans the density and I/O range required for the majority of today's logic designs, 139K to 1.25M system
gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, provid-
ing easy integration into the overall system.
System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO
advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are sup-
ported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization
(SERDES).
The ispLEVERTM design tool from Lattice allows easy implementation of designs using the ispXPGA product. Syn-
thesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these
common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor
planning and the management of other constraints within the device. The tool also provides outputs to common
timing analysis tools for timing analysis.
To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the
ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using
pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces,
and memory controllers.
Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-
ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.
Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly
used by logic designers.
Table 2. ispXPGA Speed Performance for Typical Building Blocks
Function
Performance
8:1 Asynch MUX
150 MHz
1:32 Asynch Demultiplexer
125 MHz
8 x 8 2-LL Pipelined Multiplier
225 MHz
32-bit Up/Down Counter
290 MHz
32-bit Shift Register
360 MHz
Lattice Semiconductor
ispXPGA Family Data Sheet
3
Architecture Overview
The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units
(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-
uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO
blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the
sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-
ily implement their designs, since any logic function can be placed in any section of the device.
The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are
optimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently.
The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered
quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic
elements for fast access to combinatorial functions.
The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other stor-
age types. They are designed to facilitate both single and dual-port memory for high-speed applications.
These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing
array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional
routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.
The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers can
be configured to interface with 16 different I/O standards. This allows the ispXPGA to interface with other devices
without the need for external transceivers.
The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to
800Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery
(CDR) logic.
The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased
performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for
each global clock tree in the device.
Lattice Semiconductor
ispXPGA Family Data Sheet
4
Figure 1. ispXPGA Block Diagram
Programmable Function Unit
The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are
arranged in rows and columns in the device with PFU (1,1) referring to (row 1, column 1). Each PFU consists of
four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Gen-
erator (WLG). By utilizing these components, the PFU can implement a variety of functions. Table 3 lists some of
the function capabilities of the PFU.
There are 57 inputs to each PFU and nine outputs. The PFU uses 20 inputs for logic, and 37 inputs drive the con-
trol logic from which six control signals are derived for the PFU.
Table 3. Function Capability of ispXPGA PFU
Function
Capability
Look-up table
LUT-4, LUT-5, LUT-6
Wide logic functions
Up to 20 input logic functions
Multiplexing
2:1, 4:1, 8:1
Arithmetic logic
Dedicated carry chain and booth multiplication logic
Single-port RAM
16X1, 16X2, 16X4, 32X1, 32X2, 64X1
Double-port RAM
16X1, 16X2, 32X1
Shift register
8-bit shift registers (up to 32-bit shift capability)
PFU
PIC
sysHSI Block
sysCLOCK PLL
sysIO Buffer
sysMEM Block
Lattice Semiconductor
ispXPGA Family Data Sheet
5
Figure 2. ispXPGA PFU
Control
Logic
LUT-4
COUT
LUT-4 SUM
CCG
IN
WIN0
OE
PFUCLK0
PFUCLK1
CEB0
CEB1
SR
WIN1
WIN2
WIN3
SEL0
LUT-4
COUT
LUT-4 SUM
CCG
IN
4B
S2
SEL1
SEL0
W0
OE
W1
LUT-4
COUT
LUT-4 SUM
CCG
IN
4C
S1
SEL2
LUT-4
COUT
LUT-4 SUM
CCG
IN
4D
S0
SEL3
COUT
WLGW0
WLGW1
4A
S3
SEL0
SEL1
SEL2
XIN0
XIN1
XIN2
XIN3
YIN0
YIN1
YIN2
YIN3
ZIN0
ZIN1
ZIN2
ZIN3
WIN2
WIN3
XIN2
XIN3
YIN2
YIN3
ZIN2
ZIN3
SEL3
COUT(r,c)
CIN(r,c) from
COUT(r-1,c)
D
S Q
R
CLK/LE
CE
D
S Q
R
CLK/LE
CE
X0
X1
WLGX0
WLGX1
D
S Q
R
CLK/LE
CE
D
S Q
R
CLK/LE
CE
D
S Q
R
CLK/LE
CE
Y0
Y1
WLGY0
WLGY1
SYNC/ASYNC
D
S Q
R
CLK/LE
CE
D
S Q
R
CLK/LE
CE
Z0
Z1
WLGZ0
WLGZ1
D
S Q
R
CLK/LE
CE
D
S Q
R
CLK/LE
CE
D
S Q
R
CLK/LE
CE
D
S Q
R
CLK/LE
CE
CLE0
CLE1
Wide Logic Generator
CLE2
CLE3
CSE0
CSE1
CSE2
CSE3
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
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