1
LTC1406
Low Power, 8-Bit, 20Msps,
Sampling A/D Converter
The LTC
1406 is a 20Msps, 8-bit, sampling A/D converter
which draws only 150mW from a single 5V supply. This
easy-to-use device includes a high dynamic range sample-
and-hold with a 250MHz bandwidth.
The LTC1406's full-scale input range is
1V. The inputs
can be driven differentially or one input can be tied to a
fixed voltage and the other input driven with a
1V bipolar
input. Maximum DC specifications include
1LSB DNL
and INL over temperature. Outstanding AC performance
includes 48.5dB S/(N + D) and 62dB THD with a 1MHz
input; 47.5dB S/(N + D) and 59dB THD at the Nyquist input
frequency of 10MHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 250MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
The ADC has an 8-bit parallel output port with separate
power supply and ground allowing easy interface to 3V
digital systems. The pipelined architecture has five clock
cycles of data latency.
DESCRIPTIO
N
U
FEATURES
s
Low Power, 8-Bit, 20Msps ADC
s
250MHz Internal Sample-and-Hold
s
7 Effective Bits at 70MHz Input Frequency
s
1LSB DNL and INL Max
s
Single 5V Supply and 150mW Dissipation
s
Power Down to 1
A
s
True Differential Inputs Reject Common Mode Noise
s
Accepts Single-Ended or Differential Input Signals
s
1V Differential or 2V Single-Ended Input Span
s
Analog Inputs Common Mode to V
DD
and GND
s
24-Pin Narrow SSOP Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
N
U
Low Power, 20MHz, 8-Bit Sampling ADC
INPUT FREQUENCY (Hz)
EFFECTIVE BITS
S/(N + D) (dB)
2
4
6
100k
1M
10M
100M
1406 TA02
0
3
5
7
1
8
50
44
38
32
Effective Bits and Signal-to-Noise + Distortion
vs Input Frequency
APPLICATIO
N
S
U
s
Telecommunications
s
Wireless Communications
s
Digital Cellular Telephones
s
CCDs and Image Scanners
s
Video Digitizing and Digital Television
s
Digital Color Copiers
s
High Speed Undersampling
s
Personal Computer Video
s
High Speed Data Acquisition
TRACK-AND-
HOLD AMP
DIGITAL
DATA
8-BIT
PIPELINE
ADC
2.5k
AV
DD
V
BIAS
V
REF
OV
DD
DV
DD
OGND
AGND
AGND
SHDN
1.95k
2.2V
OUTPUT
DRIVERS
OF/UF
D7
D6
D5
D4
D3
D2
D1
D0
1406 BD
CLOCK
CIRCUITRY
CLK
A
IN
+
7
8
9
4
10
3
5
6
1
23
2
11
12
22
21
20
19
18
17
16
15
24
A
IN
DGND
2
LTC1406
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
PACKAGE/ORDER I
N
FOR
M
ATIO
N
W
U
U
AV
DD
= OV
DD
= DV
DD
= V
DD
(Notes 1, 2)
Supply Voltage (V
DD
) ................................................. 6V
Analog Input Voltage (Note 3) .... 0.3V to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) .................. 0.3V to 10V
Digital Output Voltage ................. 0.3V to (V
DD
+ 0.3V)
Power Dissipation .............................................. 500mW
Ambient Operation Temperature Range
LTC1406C................................................ 0
C to 70
C
LTC1406I ............................................ 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
ORDER PART
NUMBER
Consult factory for Military grade parts.
LTC1406CGN
LTC1406IGN
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
GN PACKAGE
24-LEAD PLASTIC SSOP
24
23
22
21
20
19
18
17
16
15
14
13
OGND
OV
DD
SHDN
V
BIAS
V
REF
AGND
A
IN
+
A
IN
AV
DD
AGND
DGND
DV
DD
CLK
OF/UF
D7
D6
D5
D4
D3
D2
D1
D0
NC
NC
T
JMAX
= 110
C,
JA
= 85
C/ W
C
C
HARA TERISTICS
CO
U
VERTER
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
q
8
Bits
Integral Linearity Error
(Note 7)
q
0.5
1
LSB
Differential Linearity Error
q
0.25
1
LSB
Offset Error
(Note 8)
q
1
8
LSB
Gain Error
With External 2.5V Reference
1
5
LSB
(Notes 5, 6)
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
C.
PUT
U
I
A
A
U
LOG
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Analog Input Span [(A
IN
+
) (A
IN
)] (Note 9)
4.75V
V
DD
5.25V
q
1
V
Input (A
IN
+
or A
IN
) Range
Voltage On Either A
IN
+
or A
IN
q
0
V
DD
V
I
IN
Analog Input Leakage Current
CLK = 0
q
5
A
C
IN
Analog Input Capacitance
CLK = 1
4
pF
CLK = 0
2
pF
Input Bandwidth
250
MHz
t
AP
Sample-and-Hold Aperture Delay Time
3
ns
t
jitter
Sample-and-Hold Aperture Delay Time Jitter
5
ps
RMS
CMRR
Analog Input Common Mode Rejection Ratio
2.5V < (A
IN
= A
IN
+
) < 2.5V
60
dB
V
BIAS
Internal Bias Voltage
No Load
2.2
V
3
LTC1406
ACCURACY
IC
DY
U
W
A
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D) Signal-to-Noise Plus Distortion Ratio
1MHz Input Signal
48.5
dB
10MHz Input Signal
47.5
dB
THD
Total Harmonic Distortion
1MHz Input Signal, First 5 Harmonics
62
dB
10MHz Input Signal, First 5 Harmonics
59
dB
SFDR
Spurious Free Dynamic Range
1MHz Input Signal
63
dB
10MHz Input Signal
60
dB
IMD
Intermodulation Distortion
f
IN1
= 3.500977MHz, f
IN2
= 3.598633MHz
60
dB
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AV
DD
Analog Positive Supply Voltage
(Note 10)
4.75
5.25
V
DV
DD
Digital Positive Supply Voltage
(Note 10)
4.75
5.25
V
OV
DD
Output Positive Supply Voltage
(Note 10)
2.7
5.25
V
V
BIAS
Internal Bias Voltage
When Externally Driven (Note 10)
1.9
2.2
2.5
V
V
REF
Reference Voltage
(Note 10)
2
2.5
3
V
OGND
Output Ground
(Note 10)
0
2
V
I
DD
Positive Supply Current
AV
DD
= DV
DD
= OV
DD
= 5V, f
SMPL
= 20MHz (Note 13)
q
30
45
mA
P
D
Power Dissipation
q
150
225
mW
Power Down Positive Supply Current
SHDN = 0V, CLK = V
DD
or 0
1
10
A
Power Down Power Dissipation
SHDN = 0V, CLK = V
DD
or 0
5
50
W
(Note 5)
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
C.
DIGITAL I PUTS A
N
D OUTPUTS
U
U
(Note 5)
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
C.
POWER REQUIRE E TS
W
U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
DD
= 5.25V
q
2.4
V
V
IL
Low Level Input Voltage
V
DD
= 4.75V
q
0.8
V
I
IN
Digital Input Current
V
IN
= 0V to V
DD
q
5
A
C
IN
Digital Input Capacitance
5
pF
V
OH
High Level Output Voltage
V
DD
= 4.75V, I
O
= 10
A
4.5
V
V
DD
= 4.75V, I
O
= 200
A
q
4.0
V
V
OL
Low Level Output Voltage
V
DD
= 4.75V, I
O
= 160
A
0.05
V
V
DD
= 4.75V, I
O
= 1.6mA
q
0.10
0.4
V
I
SOURCE
Output Source Current
V
OUT
= 0V
20
mA
I
SINK
Output Sink Current
V
OUT
= V
DD
30
mA
4
LTC1406
TI I G CHARACTERISTICS
W U
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
SMPL(MAX)
Maximum Sampling Frequency
q
20
MHz
t
1
Clock Period
(Notes 11, 12)
q
50
ns
t
2
Pulse Width High
(Notes 11, 12)
q
25
ns
t
3
Pulse Width Low
(Notes 11, 12)
q
25
ns
t
4
Output Delay
C
L
= 15pF
15
25
ns
t
5
Pipeline Delay
5
Cycles
t
6
Aperture Delay
3
ns
Aperture Jitter
5
ps
RMS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above V
DD
,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below ground or above V
DD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle input currents up to
100mA below ground without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, f
SMPL
= 20MHz and t
r
= t
f
= 2ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended A
IN
+
input with A
IN
tied to V
REF
= 2.5V.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from 0.5LSB
when the output code flickers between 0111 1111 and 1000 0000.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CLK edge starts a conversion.
Note 12: At the maximum conversion rate, deviation from a 50% duty
cycle results in interstage settling times < 25ns and performance may
be affected.
Note 13: V
IN
= Full Scale.
Distortion vs Input Frequency
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
INPUT FREQUENCY (Hz)
100k
S/(N + D) (dB)
52
48
44
40
36
32
28
24
20
16
12
8
4
0
1M
10M
100M
1406 G01
S/(N + D) vs Input Frequency
INPUT FREQUENCY (Hz)
100k
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
10
20
30
40
50
60
70
80
1M
10M
100M
1406 G03
THD
3RD HARMONIC
2ND HARMONIC
Signal-to-Noise Ratio vs
Input Frequency
INPUT FREQUENCY (Hz)
100k
SIGNAL-TO-NOISE RATIO (dB)
52
48
44
40
36
32
28
24
20
16
12
8
4
0
1M
10M
100M
1406 G02
5
LTC1406
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
OUTPUT CODE
0
INL EOC ERROR (LSB)
256
1406 G07
64
128
192
1.0
0.5
0
0.5
1.0
32
96
160
224
Supply Current vs
Sampling Frequency
SAMPLING FREQUENCY (Hz)
100k
SUPPLY CURRENT (mA)
35
30
25
20
15
10
5
0
1M
10M
1406 G09
20M
INPUT FREQUENCY (Hz)
100k
SPURIOUS-FREE DYNAMIC RANGE (dB)
70
60
50
40
30
20
10
0
1M
10M
100M
1406 G04
Intermodulation Distortion Plot
FREQUENCY (MHz)
0
10
20
30
40
50
60
70
80
90
100
AMPLITUDE (dB)
1406 G05
0
1
2
3
4
5
6
7
8
9
10
f
SAMPLE
= 20MHz
f
IN1
= 3.500977MHz
f
IN2
= 3.598633MHz
Differential Nonlinearity
vs Output Code
OUTPUT CODE
0
DNL EOC ERROR (LSB)
256
1406 G06
64
128
192
1.0
0.5
0
0.5
1.0
32
96
160
224
INPUT FREQUENCY (Hz)
100k
COMMON MODE REJECTION (dB)
70
60
50
40
30
20
10
0
1M
10M
100M
1406 G08
Input Common Mode Rejection
vs Input Frequency
Integral Nonlinearity
vs Output Code
Spurious-Free Dynamic Range
vs Input Frequency
PI
N
FU
N
CTIO
N
S
U
U
U
OGND (Pin 1): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OV
DD
(Pin 2): Digital Data Output Supply. Normally tied to
5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10
F tantalum in parallel with 0.1
F or 10
F
ceramic.
SHDN (Pin 3): Power Shutdown Input. Logic low selects
shutdown.
V
BIAS
(Pin 4): Internal Bias Voltage. Internally set to 2.2V.
Bypass to analog ground plane with 10
F tantalum in par-
allel with 0.1
F or 10
F ceramic.
V
REF
(Pin 5): External 2.5V Reference Input. Bypass to
analog ground plane with 10
F tantalum in parallel with
0.1
F or 10
F ceramic.
AGND (Pin 6): Analog Ground. Tie to analog ground plane.
A
IN
+
(Pin 7):
1V Input. The maximum output code
occurs when [(A
IN
+
) (A
IN
)] = 1V. The minimum output
code occurs when [(A
IN
+
) (A
IN
)] = 1V.
A
IN
(Pin 8):
1V Input. The maximum output code
occurs when [(A
IN
+
) (A
IN
)] = 1V. The minimum output
code occurs when [(A
IN
+
) (A
IN
)] = 1V. For single-
ended operation, tie A
IN
to a DC voltage (e.g., V
REF
).
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