1
LTC1407-1/LTC1407A-1
14071f
Serial 12-Bit/14-Bit, 3Msps
Simultaneous Sampling
ADCs with Shutdown
s
3Msps Sampling ADC with Two Simultaneous
Differential Inputs
s
1.5Msps Throughput per Channel
s
Low Power Dissipation: 14mW (Typ)
s
3V Single Supply Operation
s
1.25V Differential Input Range
s
Pin Compatible 0V to 2.5V Input Range Version
(LTC1407/LTC1407A)
s
2.5V Internal Bandgap Reference with External
Overdrive
s
3-Wire Serial Interface
s
Sleep (10
W) Shutdown Mode
s
Nap (3mW) Shutdown Mode
s
80dB Common Mode Rejection at 100kHz
s
Tiny 10-Lead MS Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
Telecommunications
s
Data Acquisition Systems
s
Uninterrupted Power Supplies
s
Multiphase Motor Control
s
I & Q Demodulation
s
Industrial Radio
The LTC
1407-1/LTC1407A-1 are 12-bit/14-bit, 3Msps
ADCs with two 1.5Msps simultaneously sampled differen-
tial inputs. The devices draw only 4.7mA from a single 3V
supply and come in a tiny 10-lead MS package. A Sleep
shutdown feature lowers power consumption to 10
W.
The combination of speed, low power and tiny package
makes the LTC1407-1/LTC1407A-1 suitable for high speed,
portable applications.
The LTC1407-1/LTC1407A-1 contain two separate differ-
ential inputs that are sampled simultaneously on the rising
edge of the CONV signal. These two sampled inputs are
then converted at a rate of 1.5Msps per channel.
The 80dB common mode rejection allows users to elimi-
nate ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert 1.25V to 1.25V bipolar inputs differ-
entially. The absolute voltage swing for CH0
+
, CH0
, CH1
+
and CH1
extends from ground to the supply voltage.
The serial interface sends out the two conversion results in
32 clocks for compatibility with standard serial interfaces.
+
1
2
7
3
6
S & H
+
4
5
S & H
GND
11
EXPOSED PAD
V
REF
10
F
CH0
CH0
+
CH1
CH1
+
3V
10
F
LTC1407A-1
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
MUX
2.5V
REFERENCE
TIMING
LOGIC
V
DD
SDO
CONV
SCK
1407A1 BD
3Msps
14-BIT ADC
14-BIT LA
TCH
14-BIT LA
TCH
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
BLOCK DIAGRA
W
THD, 2nd and 3rd vs Input
Frequency for Differential
Input Signals
FREQUENCY (MHz)
0.1
80
THD, 2nd, 3rd (dB)
74
68
62
56
1
10
20
14071 G22
86
92
98
104
50
44
THD
3rd
2nd
U.S. patent numbers 6084440, 6522187
2
LTC1407-1/LTC1407A-1
14071f
(Notes 1, 2)
Supply Voltage (V
DD
) ................................................. 4V
Analog Input Voltage
(Note 3) ................................... 0.3V to (V
DD
+ 0.3V)
Digital Input Voltage .................... 0.3V to (V
DD
+ 0.3V)
Digital Output Voltage .................. 0.3V to (V
DD
+ 0.3V)
Power Dissipation .............................................. 100mW
Operation Temperature Range
LTC1407C-1/LTC1407AC-1 ..................... 0
C to 70
C
LTC1407I-1/LTC1407AI-1 .................. 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
ORDER PART
NUMBER
MSE PART MARKING
LTBGT
LTBGV
LTBGW
LTBGX
LTC1407CMSE-1
LTC1407IMSE-1
LTC1407ACMSE-1
LTC1407AIMSE-1
T
JMAX
= 125
C,
JA
= 150
C/ W
EXPOSED PAD IS GND (PIN 11)
MUST BE SOLDERED TO PCB
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. With internal reference, V
DD
= 3V.
LTC1407-1
LTC1407A-1
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
q
12
14
Bits
Integral Linearity Error
(Notes 5, 17)
q
2
0.25
2
4
0.5
4
LSB
Offset Error
(Notes 4, 17)
q
10
1
10
20
2
20
LSB
Offset Match from CH0 to CH1
(Note 17)
5
0.5
5
10
1
10
LSB
Gain Error
(Notes 4, 17)
q
30
5
30
60
10
60
LSB
Gain Match from CH0 to CH1
(Note 17)
5
1
5
10
2
10
LSB
Gain Tempco
Internal Reference (Note 4)
15
15
ppm/
C
External Reference
1
1
ppm/
C
The
q
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. With internal reference, V
DD
= 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Analog Differential Input Range (Notes 3, 8, 9)
2.7V
V
DD
3.3V
1.25 to 1.25
V
V
CM
Analog Common Mode + Differential
0 to V
DD
V
Input Range (Note 10)
I
IN
Analog Input Leakage Current
q
1
A
C
IN
Analog Input Capacitance
(Note 18)
13
pF
t
ACQ
Sample-and-Hold Acquisition Time
(Note 6)
q
39
ns
t
AP
Sample-and-Hold Aperture Delay Time
1
ns
t
JITTER
Sample-and-Hold Aperture Delay Time Jitter
0.3
ps
t
SK
Sample-and-Hold Aperture Skew from CH0 to CH1
200
ps
CMRR
Analog Input Common Mode Rejection Ratio
f
IN
= 1MHz, V
IN
= 0V to 3V
60
dB
f
IN
= 100MHz, V
IN
= 0V to 3V
15
dB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
CO VERTER CHARACTERISTICS
U
A ALOG I PUT
U
U
1
2
3
4
5
CH0
+
CH0
V
REF
CH1
+
CH1
10
9
8
7
6
CONV
SCK
SDO
V
DD
GND
TOP VIEW
11
MSE PACKAGE
10-LEAD PLASTIC MSOP
3
LTC1407-1/LTC1407A-1
14071f
I TER AL REFERE CE CHARACTERISTICS
U
U
U
The
q
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. With internal reference, V
DD
= 3V. Single ended signal drive CH0
+
/CH1
+
with
CHO
/CH1
= 1.5V DC. Differential signals drive both inputs of each channel with V
CM
= 1.5V DC.
LTC1407-1
LTC1407A-1
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
SINAD
Signal-to-Noise Plus
100kHz Input Signal (Note 19)
70.5
73.5
dB
Distortion Ratio
750kHz Input Signal (Note 19)
q
68
70.5
70
73.5
dB
100kHz Input Signal, External V
REF
= 3.3V,
72.0
76.3
dB
V
DD
3.3V (Note 19)
750kHz Input Signal, External V
REF
= 3.3V,
72.0
76.3
dB
V
DD
3.3V (Note 19)
THD
Total Harmonic
100kHz First 5 Harmonics (Note 19)
87
90
dB
Distortion
750kHz First 5 Harmonics (Note 19)
q
83
77
86
80
dB
SFDR
Spurious Free
100kHz Input Signal (Note 19)
87
90
dB
Dynamic Range
750kHz Input Signal (Note 19)
83
86
dB
IMD
Intermodulation
0.625V
P-P
1.4MHz Summed with 0.625V
P-P
, 1.56MHz
82
82
dB
Distortion
into CH0
+
and Inverted into CHO
. Also Applicable
to CH1
+
and CH1
Code-to-Code
V
REF
= 2.5V (Note 17)
0.25
1
LSB
RMS
Transition Noise
Full Power Bandwidth
V
IN
= 2.5V
P-P
, SDO = 11585LSB
P-P
(3dBFS) (Note 15)
50
50
MHz
Full Linear Bandwidth
S/(N + D)
68dB
5
5
MHz
T
A
= 25
C. V
DD
= 3V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
REF
Output Voltage
I
OUT
= 0
2.5
V
V
REF
Output Tempco
15
ppm/
C
V
REF
Line Regulation
V
DD
= 2.7V to 3.6V, V
REF
= 2.5V
600
V/V
V
REF
Output Resistance
Load Current = 0.5mA
0.2
V
REF
Settling Time
2
ms
The
q
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25
C. V
DD
= 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
DD
= 3.3V
q
2.4
V
V
IL
Low Level Input Voltage
V
DD
= 2.7V
q
0.6
V
I
IN
Digital Input Current
V
IN
= 0V to V
DD
q
10
A
C
IN
Digital Input Capacitance
5
pF
V
OH
High Level Output Voltage
V
DD
= 3V, I
OUT
= 200
A
q
2.5
2.9
V
V
OL
Low Level Output Voltage
V
DD
= 2.7V, I
OUT
= 160
A
0.05
V
V
DD
= 2.7V, I
OUT
= 1.6mA
q
0.10
0.4
V
I
OZ
Hi-Z Output Leakage D
OUT
V
OUT
= 0V to V
DD
q
10
A
C
OZ
Hi-Z Output Capacitance D
OUT
1
pF
I
SOURCE
Output Short-Circuit Source Current
V
OUT
= 0V, V
DD
= 3V
20
mA
I
SINK
Output Short-Circuit Sink Current
V
OUT
= V
DD
= 3V
15
mA
DY
A
IC ACCURACY
U
W
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
U
4
LTC1407-1/LTC1407A-1
14071f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency per Channel
q
1.5
MHz
(Conversion Rate)
t
THROUGHPUT
Minimum Sampling Period (Conversion + Acquisiton Period)
q
667
ns
t
SCK
Clock Period
(Note 16)
q
19.6
10000
ns
t
CONV
Conversion Time
(Note 6)
32
34
SCLK cycles
t
1
Minimum Positive or Negative SCLK Pulse Width
(Note 6)
2
ns
t
2
CONV to SCK
Setup Time
(Notes 6, 10)
3
ns
t
3
SCK
Before CONV
(Note 6)
0
ns
t
4
Minimum Positive or Negative CONV Pulse Width
(Note 6)
4
ns
t
5
SCK
to Sample Mode
(Note 6)
4
ns
t
6
CONV to Hold Mode
(Notes 6, 11)
1.2
ns
t
7
32nd SCK
to CONV
Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t
8
Minimum Delay from SCK
to Valid Bits 0 Through 11
(Notes 6, 12)
8
ns
t
9
SCK to Hi-Z at SDO
(Notes 6, 12)
6
ns
t
10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t
12
V
REF
Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
2
ms
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. With internal reference, V
DD
= 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
Supply Voltage
2.7
3.6
V
I
DD
Supply Current
Active Mode, f
SAMPLE
= 1.5Msps
q
4.7
7.0
mA
Nap Mode
q
1.1
1.5
mA
Sleep Mode (LTC1407)
2.0
15
A
Sleep Mode (LTC1407A)
2.0
10
A
PD
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
12
mW
POWER REQUIRE E TS
W
U
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. V
DD
= 3V.
TI I G CHARACTERISTICS
U
W
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4: Offset and range specifications apply for a single-ended CH0
+
or
CH1
+
input with CH0
or CH1
grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CH0
+
and CH0
or CH1
+
and CH1
. Performance is specified with
CHO
= 1.5V DC while driving CHO
+
and with CH1
= 1.5V DC while
driving CH1
+
.
Note 9: The absolute voltage at CH0
+
,
CH0
, CH1
+
and CH1
must be
within this range.
Note 10: If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10
F capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
P-P
input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A-1 is measured and specified with 14-bit
Resolution (1LSB = 152
V) and the LTC1407-1 is measured and specified
with 12-bit Resolution (1LSB = 610
V).
Note 18: The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
Note 19: Full-scale sinewaves are fed into the noninverting inputs while
the inverting inputs are kept at 1.5V DC.
5
LTC1407-1/LTC1407A-1
14071f
ENOBs and SINAD
vs Input Sinewave Frequency
SNR vs Input Frequency
V
DD
= 3V, T
A
= 25
C. Single ended signals drive
+CH0/+CH1 with CH0/CH1 = 1.5V DC, differential signals drive both inputs with V
CM
= 1.5V DC (LTC1407A-1)
THD, 2nd and 3rd
vs Input Frequency
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
FREQUENCY (MHz)
0.1
10.0
ENOBs (BITS)
SINAD (dB)
11.0
12.0
1
10
100
14071 G01
9.0
9.5
10.5
11.5
8.5
8.0
62
68
74
56
59
65
71
53
50
FREQUENCY (MHz)
0.1
80
THD, 2nd, 3rd (dB)
74
68
62
56
1
10
100
14071 G02
86
92
98
104
50
44
THD
3rd
2nd
FREQUENCY (MHz)
0.1
68
SFDR (dB)
56
44
1
10
100
14071 G03
80
74
62
50
86
92
98
104
FREQUENCY (MHz)
0.1
62
SNR (dB)
56
50
1
10
100
14071 G04
68
65
59
53
71
74
ENOBs and SINAD vs Input
Sinewave Frequency for
Differential Input Signals
FREQUENCY (MHz)
0.1
10.0
ENOBs (BITS)
SINAD (dB)
11.0
12.0
1
10
100
14071 G21
9.0
9.5
10.5
11.5
8.5
8.0
62
68
74
56
59
65
71
53
50
THD, 2nd and 3rd vs Input
Frequency for Differential Input
Signals
FREQUENCY (MHz)
0.1
80
THD, 2nd, 3rd (dB)
74
68
62
56
1
10
20
14071 G22
86
92
98
104
50
44
THD
3rd
2nd
SFDR vs Input Frequency
SFDR vs Input Frequency for
Differential Input Signals
748kHz Sine Wave 4096 Point
FFT Plot
98kHz Sine Wave 4096 Point
FFT Plot
FREQUENCY (kHz)
MAGNITUDE (dB)
60
30
20
14071 G05
70
80
120
100
0
10
40
50
90
110
0
200
400
100
300
600
500
700
FREQUENCY (kHz)
0
MAGNITUDE (dB)
60
30
20
14071 G06
70
80
120
200
400
100
300
600
500
700
100
0
10
40
50
90
110
FREQUENCY (MHz)
0.1
68
SFDR (dB)
56
44
1
10
100
14071 G23
80
74
62
50
86
92
98
104
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