1
LTC1418
Low Power, 14-Bit, 200ksps
ADC with Serial and Parallel I/O
OUTPUT CODE
4096
0
1.0
INL (LSBs)
0.5
0
0.5
1.0
8192
1418 TA02
12288
16384
Typical INL Curve
The LTC
1418 is a low power, 200ksps, 14-bit A/D
converter. Data output is selectable for 14-bit parallel or
serial format. This versatile device can operate from a
single 5V or
5V supply. An onboard high performance
sample-and-hold, a precision reference and internal tim-
ing minimize external circuitry requirements. The low
15mW power dissipation is made even more attractive
with two user selectable power shutdown modes.
The LTC1418 converts 0V to 4.096V unipolar inputs from
a single 5V supply and
2.048V bipolar inputs from
5V
supplies. DC specs include
1.25LSB INL,
1LSB DNL
and no missing codes over temperature. Outstanding AC
performance includes 82dB S/(N + D) and 94dB THD at the
Nyquist input frequency of 100kHz.
The flexible output format allows either parallel or serial I/O.
The SPI/MICROWIRE
TM
compatible serial I/O port can oper-
ate as either master or slave and can support clock frequen-
cies from DC to 10MHz. A separate convert start input and
a data ready signal (BUSY) allow easy control of conversion
start and data transfer.
DESCRIPTIO
N
U
FEATURES
s
Single Supply 5V or
5V Operation
s
Sample Rate: 200ksps
s
1.25LSB INL and
1LSB DNL Max
s
Power Dissipation: 15mW (Typ)
s
Parallel or Serial Data Output
s
No Missing Codes Over Temperature
s
Power Shutdown: Nap and Sleep
s
External or Internal Reference
s
Differential High Impedance Analog Input
s
Input Range: 0V to 4.096V or
2.048V
s
81.5dB S/(N + D) and 94dB THD at Nyquist
s
28-Pin Narrow PDIP and SSOP Packages
TYPICAL APPLICATIO
N
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
s
Remote Data Acquisition
s
Battery Operated Systems
s
Digital Signal Processing
s
Isolated Data Acquisition Systems
s
Audio and Telecom Processing
s
Medical Instrumentation
APPLICATIO
N
S
U
S/H
14
BUFFER
8k
10
F
10
F
REFCOMP
A
IN
A
IN
+
V
REF
4.096V
5V
LTC1418
14-BIT ADC
SELECTABLE
SERIAL/
PARALLEL
PORT
D13
DGND
1418 TA01
V
SS
(0V OR 5V)
AGND
SER/PAR
D5
D4 (EXTCLKIN)
D3 (SCLK)
D2 (CLKOUT)
D1 (D
OUT
)
D0 (EXT/INT)
V
DD
TIMING AND
LOGIC
2.5V
REFERENCE
BUSY
CS
RD
CONVST
SHDN
1
F
Low Power, 200kHz, 14-Bit Sampling A/D Converter
2
LTC1418
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
(Notes 1, 2)
Supply Voltage (V
DD
) ................................................. 6V
Negative Supply Voltage (V
SS
)
Bipolar Operation Only ........................... 6V to GND
Total Supply Voltage (V
DD
to V
SS
)
Bipolar Operation Only ....................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation .................. 0.3V to (V
DD
+ 0.3V)
Bipolar Operation........... (V
SS
0.3V) to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4)
Unipolar Operation ................................ 0.3V to 10V
Bipolar Operation.........................(V
SS
0.3V) to 10V
Digital Output Voltage
Unipolar Operation .................. 0.3V to (V
DD
+ 0.3V)
Bipolar Operation........... (V
SS
0.3V) to (V
DD
+ 0.3V)
Power Dissipation .............................................. 500mW
Operation Temperature Range
LTC1418C................................................ 0
C to 70
C
LTC1418I ............................................ 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
PACKAGE/ORDER I
N
FOR
M
ATIO
N
W
U
U
ORDER PART
NUMBER
Consult factory for Military grade parts.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
N PACKAGE
28-LEAD NARROW PDIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
IN
+
A
IN
V
REF
REFCOMP
AGND
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
DGND
V
DD
V
SS
BUSY
CS
CONVST
RD
SHDN
SER/PAR
D0 (EXT/INT)
D1 (D
OUT
)
D2 (CLKOUT)
D3 (SCLK)
D4 (EXTCLKIN)
D5
LTC1418ACG
LTC1418ACN
LTC1418AIG
LTC1418AIN
LTC1418CG
LTC1418CN
LTC1418IG
LTC1418IN
C
C
HARA TERISTICS
CO
U
VERTER
LTC1418
LTC1418A
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
q
13
14
Bits
Integral Linearity Error
(Note 7)
q
0.8
2
0.5
1.25
LSB
Differential Linearity Error
q
0.7
1.5
0.35
1
LSB
Offset Error
(Note 8)
q
5
20
2
10
LSB
Full-Scale Error
Internal Reference
10
60
20
60
LSB
External Reference = 2.5V
5
30
5
15
LSB
Full-Scale Tempco
I
OUT(REF)
= 0, Internal Reference, Commercial
q
15
10
45
ppm/
C
I
OUT(REF)
= 0, Internal Reference, Industrial
20
ppm/
C
I
OUT(REF)
= 0, External Reference
5
1
ppm/
C
With internal reference (Notes 5, 6) unless otherwise noted.
PUT
U
I
A
A
U
LOG
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Analog Input Range (Note 9)
4.75V
V
DD
5.25V (Unipolar)
q
0 to 4.096
V
4.75V
V
DD
5.25V, 5.25V
V
SS
4.75V (Bipolar)
q
2.048
V
I
IN
Analog Input Leakage Current
CS = High
q
1
A
C
IN
Analog Input Capacitance
Between Conversions (Sample Mode)
25
pF
During Conversions (Hold Mode)
5
pF
t
ACQ
Sample-and-Hold Acquisition Time
Commercial
q
300
1000
ns
Industrial
q
300
1000
ns
(Note 5)
T
JMAX
= 110
C,
JA
= 95
C/ W (G)
T
JMAX
= 110
C,
JA
= 100
C/ W (N)
3
LTC1418
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D) Signal-to-Noise Plus Distortion Ratio
97.5kHz Input Signal
q
79
81.5
dB
THD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
q
94
86
dB
SFDR
Spurious Free Dynamic Range
100kHz Input Signal
q
86
95
dB
IMD
Intermodulation Distortion
f
IN1
= 97.7kHz, f
IN2
= 104.2kHz
90
dB
Full Power Bandwidth
5
MHz
Full Linear Bandwidth
S/(N + D)
77dB
0.5
MHz
ACCURACY
IC
DY
U
W
A
(Note 5)
I TER AL REFERE CE CHARACTERISTICS
U
U
U
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
REF
Output Voltage
I
OUT
= 0
2.480
2.500
2.520
V
V
REF
Output Tempco
I
OUT
= 0, Commercial
q
10
45
ppm/
C
I
OUT
= 0, Industrial
20
ppm/
C
V
REF
Line Regulation
4.75V
V
DD
5.25V
0.05
LSB/ V
5.25V
V
SS
4.75V
0.05
LSB/ V
V
REF
Output Resistance
0.1mA
I
OUT
0.1mA
8
k
(Note 5)
DIGITAL I PUTS A
N
D OUTPUTS
U
U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
DD
= 5.25V
q
2.4
V
V
IL
Low Level Input Voltage
V
DD
= 4.75V
q
0.8
V
I
IN
Digital Input Current
V
IN
= 0V to V
DD
q
10
A
C
IN
Digital Input Capacitance
1.4
pF
V
OH
High Level Output Voltage
V
DD
= 4.75V, I
O
= 10
A
4.74
V
V
DD
= 4.75V, I
O
= 200
A
q
4.0
V
V
OL
Low Level Output Voltage
V
DD
= 4.75V, I
O
= 160
A
0.05
V
V
DD
= 4.75V, I
O
= 1.6mA
q
0.10
0.4
V
I
OZ
Hi-Z Output Leakage D13 to D0
V
OUT
= 0V to V
DD
, CS High
q
10
A
C
OZ
Hi-Z Output Capacitance D13 to D0
CS High (Note 9)
q
15
pF
I
SOURCE
Output Source Current
V
OUT
= 0V
10
mA
I
SINK
Output Sink Current
V
OUT
= V
DD
10
mA
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
Positive Supply Voltage (Notes 10, 11)
4.75
5.25
V
V
SS
Negative Supply Voltage (Note 10)
Bipolar Only (V
SS
= 0V for Unipolar)
4.75
5.25
V
I
DD
Positive Supply Current
Unipolar, RD High (Note 5)
q
3.0
4.3
mA
Bipolar, RD High (Note 5)
q
3.9
4.5
mA
Nap Mode
SHDN = 0V, CS = 0V (Note 12)
570
A
Sleep Mode
SHDN = 0V, CS = 5V (Note 12)
2
A
I
SS
Negative Supply Current
Bipolar, RD High (Note 5)
q
1.4
1.8
mA
Nap Mode
SHDN = 0V, CS = 0V (Note 12)
0.1
A
Sleep Mode
SHDN = 0V, CS = 5V (Note 12)
0.1
A
P
DIS
Power Dissipation
Unipolar
q
15.0
21.5
mW
Bipolar
q
26.5
31.5
mW
(Note 5)
POWER REQUIRE E TS
W
U
4
LTC1418
TI I G CHARACTERISTICS
W U
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency
q
200
kHz
t
CONV
Conversion Time
q
3.4
4
s
t
ACQ
Acquisition Time
q
0.3
1
s
t
ACQ
+ t
CONV
Acquisition Plus Conversion Time
q
3.7
5
s
t
1
CS to RD Setup Time
(Notes 9, 10)
q
0
ns
t
2
CS
to CONVST
Setup Time
(Notes 9, 10)
q
40
ns
t
3
CS
to SHDN
Setup Time to Ensure Nap Mode
(Notes 9, 10)
q
40
ns
t
4
SHDN
to CONVST
Wake-Up Time from Nap Mode
(Note 10)
500
ns
t
5
CONVST Low Time
(Notes 10, 11)
q
40
ns
t
6
CONVST to BUSY Delay
CL = 25pF
q
35
70
ns
t
7
Data Ready Before BUSY
20
35
ns
q
15
ns
t
8
Delay Between Conversions
(Note 10)
q
500
ns
t
9
Wait Time RD
After BUSY
q
5
ns
t
10
Data Access Time After RD
C
L
= 25pF
15
30
ns
q
40
ns
C
L
= 100pF
20
40
ns
q
55
ns
t
11
Bus Relinquish Time
8
20
ns
Commercial
q
25
ns
Industrial
q
30
ns
t
12
RD Low Time
q
t
10
ns
t
13
CONVST High Time
40
ns
t
14
Delay Time, SCLK
to D
OUT
Valid
C
L
= 25pF (Note 9)
q
35
70
ns
t
15
Time from Previous Data Remain Valid After SCLK
C
L
= 25pF (Note 9)
q
15
25
ns
f
SCLK
Shift Clock Frequency
(Notes 9, 10)
0
12.5
MHz
f
EXTCLKIN
External Conversion Clock Frequency
(Notes 9, 10)
0.03
4.5
MHz
t
dEXTCLKIN
Delay Time, CONVST
to External Conversion Clock Input
(Notes 9, 10)
533
s
t
H SCLK
SCLK High Time
(Notes 9, 10)
10
ns
t
L SCLK
SCLK Low Time
(Notes 9, 10)
20
ns
t
H EXTCLKIN
EXTCLKIN High Time
(Notes 9, 10)
250
ns
t
L EXTCLKIN
EXTCLKIN Low Time
(Notes 9, 10)
250
ns
The
q
denotes specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25
C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
CC
without latchup.
Note 4: When these pin voltages are taken below V
SS
they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, V
SS
= 0V or 5V, f
SAMPLE
= 200kHz, t
r
= t
f
= 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended input with A
IN
grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1
s after the conversion starts or after BUSY rises.
Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.
5
LTC1418
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
FREQUENCY (kHz)
0
120
AMPLITUDE (dB)
100
80
60
40
20
50
70
100
1418 G05
20
0
10
30 40
60
80
90
f
SAMPLE
= 200kHz
f
IN1
= 97.65625kHz
f
IN2
= 104.248046kHz
Intermodulation Distortion Plot
FREQUENCY (kHz)
0
10
30
50
70
90
AMPLITUDE (dB)
0
20
40
60
80
100
120
20
40
60
80
1418 F02a
100
f
SAMPLE
= 200kHz
f
IN
= 9.9609375kHz
SFDR = 99.32
SINAD = 82.4
Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
INPUT FREQUENCY (Hz)
10k
SPURIOUS-FREE DYNAMIC RANGE (dB)
100k
1M
1418 G04
0
20
40
60
80
100
120
S/(N + D) vs Input Frequency
and Amplitude
INPUT FREQUENCY (Hz)
SIGNAL/(NOISE + DISTORTION) (dB)
90
80
70
60
50
40
30
20
10
0
1k
100k
1M
1418 G01
10k
V
IN
= 60dB
V
IN
= 0dB
V
IN
= 20dB
FREQUENCY (kHz)
0
10
30
50
70
90
AMPLITUDE (dB)
0
20
40
60
80
100
120
20
40
60
80
1418 F02b
100
f
SAMPLE
= 200kHz
f
IN
= 97.509765kHz
SFDR = 94.29
SINAD = 81.4
Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
Typical INL Curve
OUTPUT CODE
4096
0
1.0
INL (LSBs)
0.5
0
0.5
1.0
8192
1418 TA02
12288
16384
OUTPUT CODE
0
1.0
DNL ERROR (LSBs)
0.5
0
0.5
1.0
4096
8192
1418 G06
12288
16384
Differential Nonlinearity
vs Output Code
INPUT FREQUENCY (Hz)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
20
40
60
80
100
120
1418 G03
1k
100k
1M
10k
THD
2ND
3RD
Distortion vs Input Frequency
Spurious-Free Dynamic Range
vs Input Frequency
Signal-to-Noise Ratio
vs Input Frequency
INPUT FREQUENCY (Hz)
SIGNAL-TO -NOISE RATIO (dB)
1k
0
90
80
70
60
50
40
30
20
10
1418 G02
100k
1M
10k
6
LTC1418
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
FREQUENCY (Hz)
1k
DISTORTION (dB)
10k
100k
1418 G08
1M
10M
0
20
40
60
80
100
120
V
SS
V
DD
DGND
Power Supply Feedthrough
vs Ripple Frequency
V
DD
Supply Current vs
Temperature (Unipolar Mode)
V
DD
Supply Current vs Sampling
Frequency (Bipolar Mode)
SAMPLING FREQUENCY (kHz)
0
V
DD
SUPPLY CURRENT (mA)
50
100
150
200
1418 G15
250
300
5
4
3
2
1
0
INPUT FREQUENCY (Hz)
1
10
COMMON MODE REJECTION (dB)
10k
100k
90
80
70
60
50
40
30
20
10
0
1418 G09
100
1k
1M
Input Common Mode Rejection
vs Input Frequency
Input Offset Voltage Shift
vs Source Resistance
INPUT SOURCE RESISTANCE (
)
CHANGE IN OFFSET VOLTAGE (LSB)
10
9
8
7
6
5
4
3
2
1
0
10
1k
10k
1M
1418 G10
100
100k
TEMPERATURE (
C)
75
V
DD
SUPPLY CURRENT (mA)
75
1418 G12
50
150
25
0
25
50
100 125
5
4
3
2
1
0
V
DD
Supply Current vs
Temperature (Bipolar Mode)
V
SS
Supply Current vs
Temperature (Bipolar Mode)
SAMPLING FREQUENCY (kHz)
0
V
SS
SUPPLY CURRENT (mA)
50
100
150
200
1418 G16
250
300
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
SS
Supply Current vs Sampling
Frequency (Bipolar Mode)
TEMPERATURE (
C)
75
V
SS
SUPPLY CURRENT (mA)
75
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1418 G13
50
150
25
0
25
50
100 125
V
DD
Supply Current vs Sampling
Frequency (Unipolar Mode)
SAMPLING FREQUENCY (kHz)
0
V
DD
SUPPLY CURRENT (mA)
50
100
150
200
1418 G14
250
300
5
4
3
2
1
0
TEMPERATURE (
C)
75
V
DD
SUPPLY CURRENT (mA)
75
5
4
3
2
1
0
1418 G11
50
150
25
0
25
50
100 125
7
LTC1418
PI
N
FU
N
CTIO
N
S
U
U
U
A
IN
+
(Pin 1): Positive Analog Input.
A
IN
(Pin 2): Negative Analog Input.
V
REF
(Pin 3): 2.50V Reference Output. Bypass to AGND
with 1
F.
REFCOMP (Pin 4): 4.096V Reference Bypass Pin.
Bypass to AGND with 10
F tantalum in parallel with 0.1
F
ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs
(Parallel). D13 is the most significant bit.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 (Pin 15): Three-State Data Output (Parallel).
D4 (EXTCLKIN) (Pin 16): Three-State Data Output
(Parallel). Conversion clock input (serial) when Pin 20
(EXT/INT) is tied high.
D3 (SCLK) (Pin 17): Three-State Data Output (Parallel).
Data clock input (serial).
D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel).
Conversion clock output (serial).
D1 (D
OUT
) (Pin 19): Three-State Data Output (Parallel).
Serial data output (serial).
D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel).
Conversion clock selector (serial). An input low enables
the internal conversion clock. An input high indicates an
external conversion clock will be assigned to Pin 16
(EXTCLKIN).
SER/PAR (Pin 21): Data Output Mode.
SHDN (Pin 22): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for nap
mode and CS = 1 for sleep mode.
RD (Pin 23): Read Input. This enables the output drivers
when CS is low.
CONVST (Pin 24): Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
CS (Pin 25): Chip Select. This input must be low for the
ADC to recognize the CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and SHDN
low select the quick wake-up nap mode. CS high and
SHDN low select sleep mode.
BUSY (Pin 26): The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
V
SS
(Pin 27): Negative Supply, 5V for Bipolar Operation.
Bypass to AGND with 10
F tantalum in parallel with 0.1
F
ceramic. Analog ground for unipolar operation.
V
DD
(Pin 28): 5V Positive Supply. Bypass to AGND with
10
F tantalum in parallel with 0.1
F ceramic.
TEST CIRCUITS
1k
C
L
DBN
DGND
A) HI-Z TO V
OH
AND V
OL
TO V
OH
C
L
DBN
1k
5V
B) HI-Z TO V
OL
AND V
OH
TO V
OL
DGND
1418 TC01
Load Circuits for Access Timing
Load Circuits for Output Float Delay
1k
30pF
DBN
A) V
OH
TO HI-Z
30pF
DBN
1k
5V
B) V
OL
TO HI-Z
1418 TC02
8
LTC1418
FU
N
CTIO
N
AL BLOCK DIAGRA
U
U
W
14-BIT CAPACITIVE DAC
COMP
REF AMP
2.5V REF
8k
REFCOMP
4.096V
2.5V
C
SAMPLE
C
SAMPLE
D13
D0
BUSY
CONTROL LOGIC
D2/(CLKOUT)
INTERNAL
CLOCK
SHDN
D0 (EXT/INT)
D4 (EXTCLKIN)
CONVST RD CS
ZEROING SWITCHES
D1/(D
OUT
)
NOTE: PIN NAMES IN PARENTHESES
REFER TO SERIAL MODE
D3/(SCLK)
V
DD
: 5V
V
SS
: 0V FOR UNIPOLAR MODE
5V FOR BIPOLAR MODE
A
IN
+
A
IN
V
REF
AGND
DGND
14
1418 BD
+
SUCCESSIVE APPROXIMATION
REGISTER
SHIFT
REGISTER
SER/PAR
MUX
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
CONVERSION DETAILS
The LTC1418 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel or serial output. The ADC
is complete with a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs (please refer to Digital Interface
section for the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
1418 F01
OUTPUT
LATCH
SAR
C
DAC
+
C
DAC
V
DAC
V
DAC
+
+
COMP
D13
D0
14
HOLD
HOLD
HOLD
A
IN
+
A
IN
ZEROING SWITCHES
C
SAMPLE
C
SAMPLE
+
HOLD
SAMPLE
SAMPLE
Figure 1. Simplified Block Diagram
9
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Referring to Figure 1, the A
IN
+
and A
IN
inputs are con-
nected to the sample-and-hold capacitors (C
SAMPLE
) dur-
ing the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 1
s will provide enough time for the sample-and-
hold capacitors to acquire the analog signal. During the
convert phase the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the C
SAMPLE
capacitors to ground, transferring
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the A
IN
+
and A
IN
input charges. The
SAR contents (a 14-bit data word) which represent the
difference of A
IN
+
and A
IN
are loaded into the 14-bit
output latches.
DYNAMIC PERFORMANCE
The LTC1418 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC's frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC's spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1418 FFT plot.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2a shows a typical spectral content with
a 200kHz sampling rate and a 10kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 100kHz.
FREQUENCY (kHz)
0
10
30
50
70
90
AMPLITUDE (dB)
0
20
40
60
80
100
120
20
40
60
80
1418 F02a
100
f
SAMPLE
= 200kHz
f
IN
= 9.9609375kHz
SFDR = 99.32
SINAD = 82.4
Figure 2a. LTC1418 Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
FREQUENCY (kHz)
0
10
30
50
70
90
AMPLITUDE (dB)
0
20
40
60
80
100
120
20
40
60
80
1418 F02b
100
f
SAMPLE
= 200kHz
f
IN
= 97.509765kHz
SFDR = 94.29
SINAD = 81.4
Figure 2b. LTC1418 Nonaveraged, 4096 Point FFT,
Input Frequency = 97.5kHz
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 200kHz the LTC1418 maintains near ideal ENOBs
up to the Nyquist input frequency of 100kHz (refer to
Figure 3).
10
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
shown in Figure 4. The LTC1418 has good distortion
performance up to the Nyquist frequency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa
nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magni-
tude, the value (in decibels) of the 2nd order IMD products
can be expressed by the following formula:
IMD fa
fb
Log
Amplitude
+
( )
=
( )
20
at fa + fb
Amplitude at fa
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD
Log
V
V
V
Vn
V
=
+
+
+
20
2
3
4
1
2
2
2
2
...
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
Figure 4. Distortion vs Input Frequency
INPUT FREQUENCY (Hz)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
20
40
60
80
100
120
1418 G03
1k
100k
1M
10k
THD
2ND
3RD
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
FREQUENCY (kHz)
0
120
AMPLITUDE (dB)
100
80
60
40
20
50
70
100
1418 G05
20
0
10
30 40
60
80
90
f
SAMPLE
= 200kHz
f
IN1
= 97.65625kHz
f
IN2
= 104.248046kHz
Figure 5. Intermodulation Distortion Plot
INPUT FREQUENCY (Hz)
1k
EFECTIVE BITS
14
13
12
11
10
9
8
7
6
5
4
3
2
10k
100k
1M
1418 F03
11
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1418 has been designed to optimize input band-
width, allowing the ADC to undersample input signals with
frequencies above the converter's Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1418 are easy to
drive. The inputs may be driven differentially or as a single-
ended input (i.e., the A
IN
input is grounded). The A
IN
+
and
A
IN
inputs are sampled at the same instant. Any
unwanted signal that is common mode to both inputs will
be reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low then the LTC1418
inputs can be driven directly. As source impedance
increases so will acquisition time (see Figure 6). For
minimum acquisition time, with high source impedance, a
buffer amplifier must be used. The only requirement is that
the amplifier driving the analog input(s) must settle after
the small current spike before the next conversion starts --
1
s for full throughput rate.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, choose an amplifier that
has a low output impedance (<100
) at the closed-loop
bandwidth frequency. For example, if an amplifier is used
in a gain of 1 and has a closed-loop bandwidth of 10MHz,
then the output impedance at 10MHz must be less than
100
. The second requirement is that the closed-loop
bandwidth must be greater than 5MHz to ensure adequate
small-signal settling for full throughput rate. If slower op
amps are used, more settling time can be provided by
increasing the time between conversions.
The best choice for an op amp to drive the LTC1418 will
depend on the application. Generally, applications fall into
two categories: AC applications where dynamic specifica-
tions are most critical and time domain applications where
DC accuracy and settling time are most critical. The
following list is a summary of the op amps that are suitable
for driving the LTC1418. More detailed information is
available in the Linear Technology Databooks and on the
LinearView
TM
CD-ROM.
LT
1354: 12MHz, 400V/
s Op Amp. 1.25mA maximum
supply current. Good AC and DC specifications. Suitable
for dual supply application.
LT1357: 25MHz, 600V/
s Op Amp. 2.5mA maximum
supply current. Good AC and DC specifications. Suitable
for dual supply application.
LT1366/LT1367: Dual/Quad Precision Rail-to-Rail Input
and Output Op Amps. 375
A supply current per amplifier.
1.8V to
15V supplies. Low input offset voltage: 150
V.
Good for low power and single supply applications with
sampling rates of 20ksps and under.
LT1498/LT1499: 10MHz, 6V/
s, Dual/Quad Rail-to-Rail
Input and Output Op Amps. 1.7mA supply current per
Figure 6. t
ACQ
vs Source Resistance
SOURCE RESISTANCE (
)
1
ACQUISITION TIME (
s)
10
1
100
1k
10k
1418 F06
0.1
10
100
100k
LinearView is a trademark of Linear Technology Corporation.
12
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
amplifier. 2.2V to
15V supplies. Good AC performance,
input noise voltage = 12nV/
Hz (typ).
LT1630/LT1631: 30MHz, 10V/
s, Dual/Quad Rail-to-Rail
Input and Output Precision Op Amps. 3.5mA supply
current per amplifier. 2.7V to
15V supplies. Best AC
performance, input noise voltage = 6nV/
Hz (typ),
THD = 86dB at 100kHz.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1418 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 5MHz. Any noise or
distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 7 shows a 2000pF
capacitor from + A
IN
to ground and a 100
source resistor
to limit the input bandwidth to 800kHz. The 2000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors can
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Input Range
The
2.048V and 0V to 4.096V input ranges of the
LTC1418 are optimized for low noise and low distortion.
Most op amps also perform well over these ranges,
allowing direct coupling to the analog inputs and eliminat-
ing the need for special translation circuitry.
Some applications may require other input ranges. The
LTC1418 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
INTERNAL REFERENCE
The LTC1418 has an on-chip, temperature compensated,
curvature corrected, bandgap reference which is factory
trimmed to 2.500V. It is internally connected to a reference
amplifier and is available at Pin 3. A 8k resistor is in series
with the output so that it can be easily overdriven in
applications where an external reference is required, see
Figure 8. The reference amplifier compensation pin
(REFCOMP, Pin 4) must be connected to a capacitor to
ground. The reference is stable with capacitors of 1
F or
greater. For the best noise performance, a 10
F in parallel
with a 0.1
F ceramic is recommended.
The V
REF
pin can be driven with a DAC or other means
to provide input span adjustment. The reference should
be kept in the range of 2.25V to 2.75V for specified
linearity.
LTC1418
A
IN
+
A
IN
V
REF
REFCOMP
AGND
ANALOG INPUT
100
1418 F07
1
2
3
4
5
2000pF
10
F
Figure 7. RC Input Filter
ANALOG
INPUT
5V
1418 F08
10
F
0.1
F
V
IN
V
OUT
LT1460
1
2
3
4
5
LTC1418
5V
A
IN
+
A
IN
V
REF
REFCOMP
AGND
V
DD
Figure 8. Using the LT1460 as an External Reference
13
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Figure 9a. LTC1418 Unipolar Transfer Characteristics
ANALOG INPUT
1418 F10a
5V
R4
100
R2
50k
R3
24k
R7
48k
R6
24k
R1
50k
R5
47k
0.1
F
10
F
R8
100
1
2
3
4
5
LTC1418
A
IN
+
A
IN
V
REF
REFCOMP
AGND V
SS
V
DD
Figure 10a. Offset and Full-Scale Adjust Circuit
If 5V Is Not Available
UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT
Figure 9a shows the ideal input/output characteristics for
the LTC1418. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, ... FS 1.5LSB). The output code is natural binary
with 1LSB = FS/16384 = 4.096V/16384 = 250
V. Figure 9b
shows the input/output transfer characteristics for the
bipolar mode in two's complement format.
Unipolar Offset and Full-Scale Error Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figures
10a and 10b show the extra components required for full-
scale error adjustment. Zero offset is achieved by adjust-
ing the offset applied to the A
IN
input. For zero offset
error apply 125
V (i.e., 0.5LSB) at the input and adjust
the offset at the A
IN
input until the output code flickers
between 0000 0000 0000 00 and 0000 0000 0000 01. For
full-scale adjustment, an input voltage of 4.095625V
(FS 1.5LSBs) is applied to A
IN
+
and R2 is adjusted until
the output code flickers between 1111 1111 1111 10 and
1111 1111 1111 11.
Bipolar Offset and Full-Scale Error Adjustment
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Again, bipolar offset error
must be adjusted before full-scale error. Bipolar offset
Figure 9b. LTC1418 Bipolar Transfer Characteristics
Figure 10b. Offset and Full-Scale Adjust Circuit
If 5V Is Available
INPUT VOLTAGE (V)
0V
OUTPUT CODE
1
LSB
1418 F9b
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 1LSB
FS/2
FS = 4.096V
1LSB = FS/16384
ANALOG INPUT
1418 F10b
5V
5V
5V
1N5817
R4
100
R2
50k
R3
24k
R6
24k
R1
50k
R5
47k
0.1
F
*
*ONLY NEEDED IF V
SS
GOES
ABOVE GROUND
10
F
1
2
3
4
5
LTC1418
A
IN
+
A
IN
V
REF
REFCOMP
AGND V
SS
V
DD
INPUT VOLTAGE (V)
0V
OUTPUT CODE
FS 1LSB
1418 F9a
111...111
111...110
111...101
111...100
000...000
000...001
000...010
000...011
1
LSB
UNIPOLAR
ZERO
1LSB =
FS
16384
4.096V
16384
=
14
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
nected to this analog ground plane. Low impedance ana-
log and digital power supply common returns are essential
to low noise operation of the ADC and the foil width for
these tracks should be as wide as possible. In applications
where the ADC data outputs and control signals are
connected to a continuously active microprocessor bus, it
is possible to get errors in the conversion results. These
errors are due to feedthrough from the microprocessor to
the successive approximation comparator. The problem
can be eliminated by forcing the microprocessor into a
wait state during conversion or by using three-state buff-
ers to isolate the ADC data bus. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
The LTC1418 has differential inputs to minimize noise
coupling. Common mode noise on the A
IN
+
and A
IN
leads
will be rejected by the input CMRR. The A
IN
input can be
used as a ground sense for the A
IN
+
input; the LTC1418 will
hold and convert the difference voltage between A
IN
+
and
A
IN
. The leads to A
IN
+
(Pin 1) and A
IN
(Pin 2) should be
kept as short as possible. In applications where this is not
possible, the A
IN
+
and A
IN
traces should be run side by
side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10
F bypass
capacitors should be used at the V
DD
and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10
F tantalum capacitors
in parallel with 0.1
F ceramic capacitors can be used.
error adjustment is achieved by adjusting the offset
applied to the A
IN
input. For zero offset error apply
125
V (i.e., 0.5LSB) at A
IN
+
and adjust the offset
at the A
IN
input until the output code flickers between
0000 0000 0000 00 and 1111 1111 1111 11. For
full-scale adjustment, an input voltage of 2.047625V
(FS 1.5LSBs) is applied to A
IN
+
and R2 is adjusted until
the output code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1418, a printed circuit board
with ground plane is required. The ground plane under the
ADC area should be as free of breaks and holes as
possible, such that a low impedance path between all ADC
grounds and all ADC decoupling capacitors is provided. It
is critical to prevent digital noise from being coupled to the
analog input, reference or analog power supply lines.
Layout should ensure that digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND) and Pin 14 (DGND) and all other analog
grounds should be connected to this single analog ground
plane. The REFCOMP bypass capacitor and the V
DD
by-
pass capacitor should also be connected to this analog
ground plane. No other digital grounds should be con-
1418 F11
DIGITAL
SYSTEM
ANALOG
INPUT
CIRCUITRY
5
4
2
27
28
14
1
10
F
3
1
F
10
F
10
F
ANALOG GROUND PLANE
+
A
IN
+
AGND
REFCOMP
V
SS
V
REF
V
DD
LTC1418
DGND
A
IN
Figure 11. Power Supply Grounding Practice
15
LTC1418
Figure 12a. Suggested Evaluation Circuit Schematic
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
V
LOGIC
+
+V
IN
GND
A
+
A
AGND
DGND
GND
V
CC
V
CC
V
CC
V
CC
V
SS
JP4
V
LOGIC
R14
20
0.125W
U4
L
TC1418
B[00:13]
U5
74HC574
U6
74HC574
13
12
7
14
51
13
19
6
20
7
EN1
EN2
DGND
HEADER
6-PIN
HC14
HC14
U7F
74HC244
98
HC14
U7D
J6-13
J6-14
J6-11
J6-12
J6-9
J6-10
J6-7
J6-8
J6-5
J6-6
J6-3
J6-4
J6-1
J6-2
J6-15
J6-16
J6-17
J6-18
D13
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D13
RDY
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D13
RDY
DGND
DGND
LED
JP1
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D[00:13]
R0, 1k
R1
R2
R3
R4
R5
R6
R8
R7
R9
R10
R11
R12
R13
HEADER
18-PIN
11
10
HC14
R21
1k
V
LOGIC
V
LOGIC
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D12
D11
D10
D09
D08
D07
D06
D00
D01
D02
D03
D04
D05
D13
19
18
17
16
15
14
13
12
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
0E
0E
DA
T
A
READY
DUAL
SUPPL
Y SELECT
SINGLE
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR V
ALUES IN OHMS, 1/10W
, 5%
2. ALL CAP
ACITOR V
ALUES IN
F
,
25V
, 20% AND IN pF
, 50V
, 10%
V
CC
V
SS
CLK
J7
V
IN
U2
L
T1121-5
D15
SS12
R17
10k
R18
10k
R19
51
R16
51
R15
51
R22
1M
JP5C
CS
SER/P
AR
SHDN
HC14
HC14
C11
1000pF
C8
1
F
16V
C13
10
F
16V
C9
10
F
16V
JP6
JP7
C6
15pF
C5
10
F
16V
C2
22
F
10V
C10
10
F
10V
C1
22
F
10V
C12
0.1
F
C14
0.1
F
GND
T
ABGND
1
24
3
C4
0.1
F
C3
0.1
F
U3
L
T1363
V
V
+
2
3
1
23
4
6
7
8
1
4
J3
7V TO
15V
J4
JP2
J5
JP3
V
OUT
V
OUT
J2
1
2
3
4
25
24
23
22
21
28
26
27
5
14
6
7
8
9
10
11
12
13
15
16
17
18
19
20
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
B00
B01
B02
B03
B04
B05
B13
B12
B11
B10
B09
B08
B07
B06
1
11
2
3
4
5
6
7
8
9
1
11
2
3
4
5
6
7
8
9
JP5B
JP5A
V
LOGIC
4
18
15
17
16
2
J8-5
J8-4
J8-3
J8-1
J8-2
J8-6
5
U8B
74HC244
74HC244
74HC244
1
9
B00
B01
B02
B03
B04
EXT/INT
D
OUT
CLKOUT
SCLK
EXTCLKIN
U8E
U8H
74HC244
74HC244
U8G
74HC244
C7
0.1
F
C15
0.1
F
+
+
V
SS
J1
7V TO
15V
D14
SS12
V
IN
2
4
1
3
U1
L
T1175-5
+
1418 F12a
R20
19k
V
IN
V
OUT
TA
B
GND
U7C
U7G
HC14
U8F
U8A
12
8
U8D
14
6
74HC244
U8C
R23
100k
U7B
U7A
U7E
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+A
IN
A
IN
V
REF
REFCOMP
CS
CONVST
RD
SHDN
SER/P
AR
V
DD
BUSY
V
SS
AGND
DGND
16
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Figure 12b. Suggested Evaluation Circuit Board-- Component Side Top Silkscreen
Figure 12c. Suggested Evaluation Circuit Board--Top Layer
1418 F12b
1418 F12c
17
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Figure 12d. Suggested Evaluation Circuit Board--Solder Side Layout
1418 F12d
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
Example Layout
Figures 12a, 12b, 12c and 12d show the schematic and
layout of a suggested evaluation board. The layout demon-
strates the proper use of decoupling capacitors and ground
plane with a 2-layer printed circuit board.
DIGITAL INTERFACE
The LTC1418 can operate in serial or parallel mode. In
parallel mode the ADC is designed to interface with micro-
processors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. In serial mode only four digital interface lines
are required, SCLK, CONVST, EXTCLKIN and D
OUT
. SCLK,
the serial data shift clock can be an external input or
supplied by the LTC1418 internal clock.
Internal Clock
The ADC has an internal clock. In parallel output mode the
internal clock is always used as the conversion clock. In
serial output mode either the internal clock or an external
clock may be used as the conversion clock (see Figure 20).
The internal clock is factory trimmed to achieve a typical
conversion time of 3.4
s and a maximum conversion time
over the full operating temperature range of 4
s. No exter-
nal adjustments are required, and with the guaranteed maxi-
mum acquisition time of 1
s, throughput performance of
200ksps is assured.
Power Shutdown
The LTC1418 provides two power shutdown modes, nap
and sleep, to save power during inactive periods. The nap
mode reduces the power by 80% and leaves only the
digital logic and reference powered up. The wake-up time
from nap to active is 500ns (see Figure 13a). In sleep
mode all bias currents are shut down and only leakage
current remains-- about 2
A. Wake-up time from sleep
18
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Figure 14. CS to CONVST Set-Up Timing
t
2
t
1
CS
CONVST
RD
1418 F14
mode is much slower since the reference circuit must
power up and settle to 0.005% for full 14-bit accuracy.
Sleep mode wake-up time is dependent on the value of
the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 30ms with the recommended 10
F
capacitor. Shutdown is controlled by Pin 22 (SHDN); the
ADC is in shutdown when it is low. The shutdown mode
is selected with Pin 25 (CS); low selects nap (see Figure
13b), high selects sleep.
t
4
SHDN
CONVST
1418 F13a
Figure 13a. SHDN to CONVST Wake-Up Timing
t
3
CS
SHDN
1418 F13b
Figure 13b. CS to SHDN Timing
Conversion Control
Conversion start is controlled by the CS and CONVST
inputs. A falling edge of CONVST pin will start a conversion
after the ADC has been selected (i.e., CS is low, see Figure
14). Once initiated, it cannot be restarted until the conver-
sion is complete. Converter status is indicated by the
BUSY output. BUSY is low during a conversion.
Data Output
The data format is controlled by the SER/PAR input pin;
logic low selects parallel output format. In parallel mode
the 14-bit data output word D0 to D13 is updated at the end
of each conversion on Pins 6 to 13 and Pins 15 to 20. A
logic high applied to SER/PAR selects the serial formatted
data output and Pins 16 to 20 assume their serial function,
Pins 6 to 13 and 15 are in the Hi-Z state. In either parallel
or serial data formats, outputs will be active only when CS
and RD are low. Any other combination of CS and RD will
three-state the output. In unipolar mode (V
SS
= 0V) the
data will be in straight binary format (corresponding to the
unipolar input range). In bipolar mode (V
SS
= 5V), the
data will be in two's complement format (corresponding to
the bipolar input range).
Parallel Output Mode
Parallel mode is selected with a logic 0 applied to the
SER/PAR pin. Figures 15 through 19 show different modes
of parallel output operation. In modes 1a and 1b (Figures
15 and 16) CS and RD are both tied low. The falling edge
of CONVST starts the conversion. The data outputs are
always enabled and data can be latched with the BUSY
rising edge. Mode 1a shows operation with a narrow logic
low CONVST pulse. Mode 1b shows a narrow logic high
CONVST pulse.
In mode 2 (Figure 17) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared databus.
In slow memory and ROM modes (Figures 18 and 19), CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode the processor takes RD (= CONVST)
low and starts the conversion. BUSY goes low forcing the
processor into a wait state. The previous conversion result
appears on the data outputs. When the conversion is
complete, the new conversion results appear on the data
19
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Figure 15. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
Figure 16. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
DATA (N 1)
DB13 TO DB0
CONVST
BUSY
1418 F16
t
CONV
t
5
t
6
t
13
t
7
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA
CS = RD = 0
t
6
t
8
DATA (N 1)
DB13 TO DB0
CONVST
CS = RD = 0
BUSY
1418 F15
t
5
t
CONV
(SAMPLE N)
t
6
t
8
t
7
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA
CONVST
CS = 0
(SAMPLE N)
BUSY
1418 F17
t
5
t
CONV
t
8
t
12
t
6
t
9
t
12
DATA N
DB13 TO DB0
t
11
t
10
RD
DATA
Figure 17. Mode 2. CONVST Starts a Conversion. Data is Read by RD
20
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
RD = CONVST
CS = 0
BUSY
1418 F18
t
CONV
(SAMPLE N)
t
6
DATA (N 1)
DB13 TO DB0
DATA
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA N
DB13 TO DB0
t
11
t
8
t
10
t
7
Figure 18. Slow Memory Mode Timing
Figure 19. ROM Mode Timing
RD = CONVST
CS = 0
(SAMPLE N)
BUSY
1418 F19
t
CONV
t
6
DATA (N 1)
DB13 TO DB0
DATA
DATA N
DB13 TO DB0
t
10
t
11
t
8
outputs; BUSY goes high releasing the processor and the
processor takes RD (= CONVST) back high and reads the
new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
Serial Output Mode
Serial output mode is selected when the SER/PAR input
pin is high. In this mode, Pins 16 to 20, D0 (EXT/INT), D1
(D
OUT
), D2 (CLKOUT), D3 (SCLK) and D4 (EXTCLKIN)
assume their serial functions as shown in Figure 20.
(During this discussion these pins will be referred to by
their serial function names: EXT/INT, D
OUT
, CLKOUT,
SCLK and EXTCLKIN.) As in parallel mode, conversions
are started by a falling CONVST edge with CS low. After a
conversion is completed and the output shift register has
been updated, BUSY will go high and valid data will be
available on D
OUT
(Pin 19). This data can be clocked out
either before the next conversion starts or it can be clocked
out during the next conversion. To enable the serial data
output buffer and shift clock, CS and RD must be low.
Figure 20 shows a function block diagram of the LTC1418
in serial mode. There are two pieces to this circuitry: the
conversion clock selection circuit (EXT/INT, EXTCLKIN
and CLKOUT) and the serial port (SCLK, D
OUT
, CS and RD).
Conversion Clock Selection (Serial Mode)
In Figure 20, the conversion clock controls the internal
ADC operation. The conversion clock can be either inter-
nal or external. By connecting EXT/INT low, the internal
clock is selected. This clock generates 16 clock cycles
which feed into the SAR for each conversion.
To select an external conversion clock, tie EXT/INT high
and apply an external conversion clock to EXTCLKIN (Pin
16). (When an external shift clock (SCLK) is used during
a conversion, the SCLK should be used as the external
conversion clock to avoid the noise generated by the
21
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
THREE
STATE
BUFFER
THREE
STATE
BUFFER
23
RD
17
SCLK*
CS
25
EXTCLKIN*
16
EXT/INT*
BUSY
*PINS 16 TO 20 ARE LABELED WITH THEIR SERIAL FUNCTIONS
1418 F20
20
D
OUT
*
19
CLKOUT*
18
26
SHIFT
REGISTER
INTERNAL
CLOCK
16 CONVERSION CLOCK CYCLES
EOC
DATA
IN
14
DATA
OUT
CLOCK
INPUT
SAR
Figure 20. Functional Block Diagram for Serial Mode (SER/PAR = High)
asynchronous clocks. To maintain accuracy the external
conversion clock frequency must be between 30kHz and
4.5MHz.) The SAR sends an end of conversion signal,
EOC, that gates the external conversion clock so that only
16 clock cycles can go into the SAR, even if the external
clock, EXTCLKIN, contains more than 16 cycles.
When CS and RD are low, these 16 cycles of conversion
clock (whether internally or externally generated) will
appear on CLKOUT during each conversion and then
CLKOUT will remain low until the next conversion. If
desired, CLKOUT can be used as a master clock to drive
the serial port. Because CLKOUT is running during the
conversion, it is important to avoid excessive loading that
can cause large supply transients and create noise. For
the best performance, limit CLKOUT loading to 20pF.
Serial Port
The serial port in Figure 20 is made up of a 16-bit shift
register and a three-state output buffer that are con-
trolled by three inputs: SCLK, RD and CS. The serial port
has one output, D
OUT
, that provides the serial output
data.
The SCLK is used to clock the shift register. Data may be
clocked out with the internal conversion clock operating
as a master by connecting CLKOUT (Pin 18) to SCLK (Pin
17) or with an external data clock applied to D3 (SCLK).
The minimum number of SCLK cycles required to
transfer a data word is 14. Normally, SCLK contains 16
clock cycles for a word length of 16 bits; 14 bits with MSB
first, followed by two trailing zeros.
A logic high on RD disables SCLK and three-states D
OUT
.
In case of using a continuous SCLK, RD can be controlled
to limit the number of shift clocks to the desired number
(i.e., 16 cycles) and to three-state D
OUT
after the data
transfer.
A logic high on CS three-states the D
OUT
output buffer. It
also inhibits conversion when it is tied high. In power
shutdown mode (SHDN = low), a high CS selects sleep
mode while a low CS selects nap mode. For normal serial
port operation, CS can be grounded.
D
OUT
outputs the serial data; 14 bits, MSB first, on the
falling edge of each SCLK (see Figures 21 and 22). If 16
SCLKs are provided, the 14 data bits will be followed by
22
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Figure 22. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
two zeros. The MSB (D13) will be valid on the first rising
and the first falling edge of the SCLK. D12 will be valid on
the second rising and the second falling edge as will all
the remaining bits. The data may be captured on either
edge. The largest hold time margin is achieved if data is
captured on the rising edge of SCLK.
BUSY gives the end of conversion indication. When the
LTC1418 is configured as a master serial device, BUSY
can be used as a framing pulse and to three-state the
t
15
t
14
SCLK
V
IL
V
OH
V
OL
D
OUT
1418 F21
Figure 21. SCLK to D
OUT
Delay
LTC1418
BUSY (= RD)
CLKOUT ( = SCLK)
BUSY
CONVST
CONVST
RD
SCLK
CLKOUT
EXT/INT
D
OUT
26
24
23
17
18
20
25
19
D
OUT
CS
1418 F22a
P OR DSP
(CONFIGURED
AS SLAVE)
OR
SHIFT
REGISTER
D12
D11
D11
D12
CAPTURE ON
RISING CLOCK
D13
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FILL
ZEROS
D13
1
t
5
t
6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
D13
D13
D12
D11
Hi-Z
Hi-Z
DATA N
DATA (N 1)
(SAMPLE N)
(SAMPLE N + 1)
D
OUT
CS = EXT/INT = 0
CLKOUT (= SCLK)
CONVST
t
13
t
CONV
t
8
SAMPLE
HOLD
HOLD
t
10
t
7
t
11
1418 F22b
BUSY (= RD)
t
15
t
14
CLKOUT
(= SCLK)
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
23
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
clock and the SCLK. The internal clock has been optimized
for the fastest conversion time, consequently this mode
can provide the best overall speed performance. To select
an internal conversion clock, tie EXT/INT (Pin 20) low. The
internal clock appears on CLKOUT (Pin 18) which can be
tied to SCLK (Pin 17) to supply the SCLK.
Using External Clock for Conversion and Data Transfer.
In Figure 23, data from the previous conversion is output
during the conversion with an external clock providing
both the conversion clock and the shift clock. To select an
external conversion clock, tie EXT/INT high and apply the
Figure 23. External Conversion Clock Selected. Data Transferred During Conversion Using
the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
serial port after transferring the serial output data by
tying it to the RD pin.
Figures 22 to 25 show several serial modes of operation,
demonstrating the flexibility of the LTC1418 serial port.
Serial Data Output During a Conversion
Using Internal Conversion Clock for Conversion and
Data Transfer. Figure 22 shows data from the previous
conversion being clocked out during the conversion with
the LTC1418 internal clock providing both the conversion
D12
D11
D11
D12
CAPTURE ON
RISING CLOCK
D13
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FILL
ZEROS
D13
1
t
5
t
6
t
10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
D13
D13
D12
D11
Hi-Z
Hi-Z
DATA N
DATA (N 1)
(SAMPLE N)
(SAMPLE N + 1)
D
OUT
CS = 0, EXT/INT = 5
EXTCLKIN (= SCLK)
CONVST
t
13
t
CONV
t
8
SAMPLE
HOLD
HOLD
t
dEXTCLKIN
t
7
t
11
1418 F23b
BUSY (= RD)
t
15
t
14
t
LEXTCLKIN
t
HEXTCLKIN
EXTCLKIN
(= SCLK)
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
LTC1418
BUSY (= RD)
EXTCLKIN ( = SCLK)
BUSY
CONVST
CONVST
RD
EXTCLKIN
SCLK
EXT/INT
D
OUT
D
OUT
CS
5V
25
20
19
26
24
17
16
23
1418 F23a
P OR DSP
24
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
clock to EXTCLKIN. The same clock is also applied to SCLK
to provide a data shift clock. To maintain accuracy the
conversion clock frequency must be between 30kHz and
4.5MHz.
It is not recommended to clock data with an external clock
during a conversion that is running on an internal clock
because the asynchronous clocks may create noise.
Serial Data Output After a Conversion
Using Internal Conversion Clock and External Data Clock.
In this mode, data is output after the end of each conver-
sion but before the next conversion is started (Figure 24).
The internal clock is used as the conversion clock and an
external clock is used for the SCLK. This mode is useful in
applications where the processor acts as a master serial
device. This mode is SPI and MICROWIRE compatible. It
LTC1418
BUSY
CONVST
26
24
19
20
25
23
17
CONVST
RD
SCLK
EXT/INT
D
OUT
CS
1418 F24a
P OR DSP
INT
C0
SCK
MISO
12 11 10 9
8
7
6
5
4
3
2
1
0
FILL
ZEROS
D13
t
5
t
6
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Hi-Z
DATA N
Hi-Z
(SAMPLE N)
D
OUT
CS = EXT/INT = 0
CONVST
t
13
t
CONV
t
8
HOLD
SAMPLE
t
9
t
10
1418 F24b
t
11
BUSY
SCLK
RD
D11
D12
CAPTURE ON
RISING CLOCK
D13
t
15
t
14
t
LSCLK
t
HSCLK
SCLK
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
Figure 24. Internal Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY
Indicates End of Conversion
25
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
also allows operation when the SCLK frequency is very low
(less than 30kHz). To select the internal conversion clock
tie EXT/INT low. The external SCLK is applied to SCLK. RD
can be used to gate the external SCLK, such that data will
clock only after RD goes low and to three-state D
OUT
after
data transfer. If more than 16 SCLKs are provided, more
zeros will be filled in after the data word indefinitely.
LTC1418
BUSY
CONVST
CONVST
RD
EXTCLKIN
SCLK
EXT/INT
D
OUT
CS
5V
25
16
24
23
17
26
19
20
1418 F25a
P OR DSP
CLKOUT
INT
C0
SCK
MISO
t
5
t
6
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
CS = 0, EXT/INT = 5
CONVST
EXTCLKIN
t
13
t
dEXTCLKIN
t
8
HOLD
SAMPLE
t
9
t
7
t
11
BUSY
SCLK
RD
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
1
2
3
4
12 11 10 9
8
7
6
5
4
3
2
1
0
FILL
ZEROS
D13
Hi-Z
DATA N
Hi-Z
(SAMPLE N)
D
OUT
t
CONV
t
10
1418 F25b
D11
D12
CAPTURE ON
RISING CLOCK
D13
t
15
t
14
SCLK
V
IL
V
OH
V
OL
D
OUT
CAPTURE ON
FALLING CLOCK
t
LSCLK
t
HSCLK
Figure 25. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY
Indicates End of Conversion
Using External Conversion Clock and External Data
Clock. In Figure 25, data is also output after each conver-
sion is completed and before the next conversion is
started. An external clock is used for the conversion clock
and either another or the same external clock is used for
the SCLK. This mode is identical to Figure 24 except that
an external clock is used for the conversion. This mode
26
LTC1418
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
G28 SSOP 0694
0.005 0.009
(0.13 0.22)
0
8
0.022 0.037
(0.55 0.95)
0.205 0.212**
(5.20 5.38)
0.301 0.311
(7.65 7.90)
1
2 3
4
5
6 7 8
9 10 11 12
14
13
0.397 0.407*
(10.07 10.33)
25
26
22 21 20 19 18 17 16 15
23
24
27
28
0.068 0.078
(1.73 1.99)
0.002 0.008
(0.05 0.21)
0.0256
(0.65)
BSC
0.010 0.015
(0.25 0.38)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
allows the user to synchronize the A/D conversion to an
external clock either to have precise control of the internal
bit test timing or to provide a precise conversion time. As in
Figure 24, this mode works when the SCLK frequency is
very low (less than 30kHz). However, the external conver-
sion clock must be between 30kHz and 4.5MHz to maintain
accuracy. If more than 16 SCLKs are provided, more zeros
will be filled in after the data word indefinitely. To select the
external conversion clock tie EXT/INT high. The external
SCLK is applied to SCLK. RD can be used to gate the external
SCLK such that data will clock only after RD goes low.
27
LTC1418
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
N Package
28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
N28 1197
0.255
0.015*
(6.477
0.381)
1.370*
(34.789)
MAX
3
4
5
6
7
8
9
10
11
12
21
13
14
15
16
18
17
19
20
22
23
24
25
26
2
27
1
28
0.020
(0.508)
MIN
0.125
(3.175)
MIN
0.130
0.005
(3.302
0.127)
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.018
0.003
(0.457
0.076)
0.005
(0.127)
MIN
0.100
0.010
(2.540
0.254)
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
28
LTC1418
LINEAR TECHNOLOGY CORPORATION 1998
1418f LT/TP 0798 4K PRINTED IN USA
TYPICAL APPLICATIO
N
U
Single 5V Supply, 200kHz, 14-Bit Sampling A/D Converter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
IN
+
A
IN
V
REF
REFCOMP
AGND
D13(MSB)
D12
D11
D10
D9
D8
D7
D6
DGND
V
DD
V
SS
BUSY
CS
CONVST
RD
SHDN
SER/PAR
(EXT/INT)D0
(D
OUT
)D1
(CLKOUT)D2
(SCLK)D3
(EXTCLKIN )D4
D5
LTC1418
10
F
1
F
DIFFERENTIAL
ANALOG INPUT
(0V TO 4.096V)
10
F
1N5817*
*REQUIRED ONLY IF V
SS
CAN BECOME
POSITIVE WITH RESPECT TO GROUND
5V
14-BIT
PARALLEL
BUS
P CONTROL
LINES
1418 TA03
V
REF
OUTPUT
2.5V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADCs
LTC1274/LTC1277
Low Power, 12-Bit, 100ksps ADCs
10mW Power Dissipation, Parallel/Byte Interface
LTC1412
12-Bit, 3Msps Sampling ADC
Best Dynamic Performance, SINAD = 72dB at Nyquist
LTC1415
Single 5V, 12-Bit, 1.25Msps ADC
55mW Power Dissipation, 72dB SINAD
LTC1416
Low Power, 14-Bit, 400ksps ADC
70mW Power Dissipation, 80.5dB SINAD
LTC1419
Low Power, 14-Bit, 800ksps ADC
True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LTC1604
16-Bit, 333ksps Sampling ADC
2.5V Input, SINAD = 90dB, THD = 100dB
LTC1605
Single 5V, 16-Bit, 100ksps ADC
Low Power,
10V Inputs, Parallel/Byte Interface
DACs
LTC1595
16-Bit CMOS Multiplying DAC in SO-8
1LSB Max INL/DNL, 1nV sec Glitch, DAC8043 Upgrade
LTC1596
16-Bit CMOS Multiplying DAC
1LSB Max INL/DNL, DAC8143/AD7543 Upgrade
Reference
LT1019-2.5
Precision Bandgap Reference
0.05% Max, 5ppm/
C Max
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
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