LTC1546

Software-Selectable

Multiprotocol Transceiver

with Termination

December 1999

, LTC and LT are registered trademarks of Linear Technology Corporation.

Complete DTE or DCE Multiprotocol Serial Interface with DB-25 Connector

Data Networking

CSU and DSU

Data Routers

Software-Selectable Transceiver Supports:
RS232, RS449, EIA530, EIA530-A, V.35, V.36, X.21

TUV Telecom Services Inc. Certified NET1,
NET2 and TBR2 Compliant

On-Chip Cable Termination

Pin Compatible with LTC1543

Complete DTE or DCE Port with LTC1544

Operates from Single 5V Supply

Small Footprint

The LTC

1546 is a 3-driver/3-receiver multiprotocol trans-

ceiver with on-chip cable termination. When combined with
the LTC1544, this chip set forms a complete software-
selectable DTE or DCE interface port that supports the
RS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21
protocols. All necessary cable termination is provided inside
the LTC1546. In most applications, the LTC1546 replaces
both an LTC1543 and an LTC1344A without any changes to
the PC board.

The LTC1546 runs from a single 5V supply using an internal
charge pump that requires only five space-saving surface
mounted capacitors. The LTC1546 is available in a 28-lead
SSOP surface mount package.

Final Electrical Specifications

LTC1544

RTS

DTR

DSR

DCD

CTS

LTC1546

TXD

SCTE

TXC

RXC

RXD

1546 TA01

SCTE B

SCTE A (113)

TXD B

TXD A (103)

RXC A (115)

RXC B

RXD A (104)

RXD B

RTS A (105)

RTS B

DTR A (108)

DTR B

CTS A (106)

CTS B

LL A (141)

SG (102)

SHIELD (101)

DB-25 CONNECTOR

TXC A (114)

DCD A (107)

DCD B

DSR A (109)

DSR B

TXC B

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

LTC1546

ORDER PART

NUMBER

(Note 1)

Supply Voltage ....................................................... 6.5V
Input Voltage

Transmitters ........................... 0.3V to (V

+ 0.3V)

Receivers ............................................... 18V to 18V
Logic Pins .............................. 0.3V to (V

+ 0.3V)

Output Voltage

Transmitters ................. (V

0.3V) to (V

+ 0.3V)

Receivers ................................ 0.3V to (V

+ 0.3V)

........................................................ 10V to 0.3V

....................................................... 0.3V to 10V

Short-Circuit Duration

Transmitter Output ..................................... Indefinite
Receiver Output .......................................... Indefinite
V

.................................................................. 30 sec

Operating Temperature Range

LTC1546C ............................................... 0

C to 70

LTC1546I ........................................... 40

C to 85

Storage Temperature Range ................ 65

C to 150

Lead Temperature (Soldering, 10 sec)................. 300

LTC1546CG
LTC1546IG

Consult factory for Military grade parts.

JMAX

= 150

= 90

C/ W*

TOP VIEW

DCE/DTE

GND

D1 A

D1 B

D2 A

D2 B

D3/R1 A

D3/R1 B

R2 A

R2 B

R3 A

R3 B

CHARGE PUMP

G PACKAGE

28-LEAD PLASTIC SSOP

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 5V (Notes 2, 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supplies

Supply Current (DCE Mode,

RS530, RS530-A, X.21 Modes, No Load

All Digital Pins = GND or V

)

RS530, RS530-A, X.21 Modes, Full Load

100

130

V.35 Mode

126

170

V.28 Mode, No Load

V.28 Mode, Full Load

No-Cable Mode

500

Internal Power Dissipation (DCE Mode)

RS530, RS530-A, X.21 Modes, Full Load

410

V.35 Mode, Full Load

625

V.28 Mode, Full Load

150

Positive Charge Pump Output Voltage

V.11 or V.28 Mode, No Load

8.0

9.3

V.35 Mode

7.0

8.0

V.28 Mode, with Load

8.0

8.7

V.28 Mode, with Load, I

= 10mA

6.5

Negative Charge Pump Output Voltage

V.28 Mode, No Load

9.6

V.28 Mode, Full Load

7.5

8.5

V.35 Mode

5.5

6.5

RS530, RS530-A, X.21 Modes, Full Load

4.5

6.0

SOLDERED TO A TYPICAL CIRCUIT BOARD

IS TYPICALLY 60

C/W

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

ELECTRICAL CHARACTERISTICS

LTC1546

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 5V (Notes 2, 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

OSC

Charge Pump Oscillator Frequency

500

kHz

Charge Pump Rise Time

No-Cable Mode/Power-Off to Normal Operation

Logic Inputs and Outputs

Logic Input High Voltage

Logic Input Low Voltage

0.8

Logic Input Current

D1, D2, D3

M0, M1, M2, DCE = GND

120

M0, M1, M2, DCE = V

Output High Voltage

= 3mA

4.5

Output Low Voltage

= 3mA

0.3

0.45

OSR

Output Short-Circuit Current

OZR

Three-State Output Current

M0 = M1 = M2 = V

, 0V

V.11 Driver

ODO

Open Circuit Differential Output Voltage

= 1.95k (Figure 1)

ODL

Loaded Differential Output Voltage

= 50

(Figure 1)

0.5V

ODO

0.67V

ODO

= 50

(Figure 1)

Change in Magnitude of Differential

= 50

(Figure 1)

0.2

Output Voltage

Common Mode Output Voltage

= 50

(Figure 1)

Change in Magnitude of Common Mode

= 50

(Figure 1)

0.2

Output Voltage

Short-Circuit Current

OUT

= GND

150

Output Leakage Current

and

0.25V, Power Off or

100

No-Cable Mode or Driver Disabled

, t

Rise or Fall Time

(Figures 2, 13)

PLH

Input to Output Rising

(Figures 2, 13)

PHL

Input to Output Falling

(Figures 2, 13)

Input to Output Difference,

PLH

PHL

(Figures 2, 13)

SKEW

Output to Output Skew

(Figures 2, 13)

V.11 Receiver

Input Threshold Voltage

0.2

Input Hysteresis

Input Impedance

7V (Figure 3)

100

103

, t

Rise or Fall Time

= 50pF (Figures 4, 14)

PLH

Input to Output Rising

= 50pF (Figures 4, 14)

PHL

Input to Output Falling

= 50pF (Figures 4, 14)

Input to Output Difference,

PLH

PHL

= 50pF (Figures 4, 14)

V.35 Driver

Differential Output Voltage

Open Circuit, R

= 1.95k (Figure 5)

1.2

With Load, 4V

4V (Figure 6)

0.44

0.55

0.66

, V

Single-Ended Output Voltage

Open Circuit, R

= 1.95k (Figure 5)

1.2

Transmitter Output Offset

= 50

(Figure 5)

0.6

ELECTRICAL CHARACTERISTICS

LTC1546

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 5V (Notes 2, 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Transmitter Output High Current

= 0V

9.0

Transmitter Output Low Current

= 0V

9.0

Transmitter Output Leakage Current

and

0.25V

100

Transmitter Differential Mode Impedance

100

150

Transmitter Common Mode Impedance

2V (Figure 7)

135

150

165

, t

Rise or Fall Time

(Figures 8, 13)

PLH

Input to Output

(Figures 8, 13)

PHL

Input to Output

(Figures 8, 13)

Input to Output Difference,

PLH

PHL

(Figures 8, 13)

SKEW

Output to Output Skew

(Figures 8, 13)

V.35 Receiver

Differential Receiver Input Threshold Voltage

2V (Figure 9)

0.2

Receiver Input Hysteresis

2V (Figure 9)

Receiver Differential Mode Impedance

103

110

Receiver Common Mode Impedance

2V (Figure 10)

135

150

165

, t

Rise or Fall Time

= 50pF (Figures 4, 14)

PLH

Input to Output

= 50pF (Figures 4, 14)

PHL

Input to Output

= 50pF (Figures 4, 14)

Input to Output Difference,

PLH

PHL

= 50pF (Figures 4, 14)

V.28 Driver

Output Voltage

Open Circuit

= 3k (Figure 11)

8.5

Short-Circuit Current

OUT

= GND

150

Power-Off Resistance

2V < V

< 2V, Power Off

300

or No-Cable Mode

Slew Rate

= 7k, C

= 0 (Figures 11, 15)

PLH

Input to Output

= 3k, C

= 2500pF (Figures 11, 15)

1.5

2.5

PHL

Input to Output

= 3k, C

= 2500pF (Figures 11, 15)

1.5

2.5

V.28 Receiver

THL

Input Low Threshold Voltage

(Figure 12)

1.2

0.8

TLH

Input High Threshold Voltage

(Figure 12)

1.2

Receiver Input Hysteresis

(Figure 12)

0.05

0.3

Receiver Input Impedance

15V

, t

Rise or Fall Time

= 50pF (Figures 12, 16)

PLH

Input to Output

= 50pF (Figures 12, 16)

300

PHL

Input to Output

= 50pF (Figures 12, 16)

160

300

Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device
are negative. All voltages are referenced to device ground unless otherwise
specified.

Note 3: All typicals are given for V

= 5V, C1 = C2 = C

VCC

= C

VDD

= 1

VEE

= 3.3

F and T

= 25

ELECTRICAL CHARACTERISTICS

LTC1546

(Pin 1): Capacitor C1 Negative Terminal. Connect a

F capacitor between C1

and C1

(Pin 2): Capacitor C1 Positive Terminal. Connect a

F capacitor between C1

and C1

(Pin 3): Generated Positive Supply Voltage for

V.28. Connect a 1

F capacitor to ground.

(Pin 4): Positive Supply Voltage Input. 4.75V

5.25V. Bypass with a 1

F capacitor to ground.

D1 (Pin 5): TTL Level Driver 1 Input.

D2 (Pin 6): TTL Level Driver 2 Input.

D3 (Pin 7): TTL Level Driver 3 Input.

R1 (Pin 8): CMOS Level Receiver 1 Output.

R2 (Pin 9): CMOS Level Receiver 2 Output.

R3 (Pin 10): CMOS Level Receiver 3 Output.

M0 (Pin 11): TTL Level Mode Select Input 0 with Pull-Up
to V

. See Table 1.

M1 (Pin 12): TTL Level Mode Select Input 1 with Pull-Up
to V

. See Table 1.

M2 (Pin 13): TTL Level Mode Select Input 2 with Pull-Up
to V

. See Table 1.

DCE/DTE (Pin 14): TTL Level Mode Select Input with Pull-
Up to V

. See Table 1.

R3 B (Pin 15): Receiver 3 Noninverting Input.

R3 A (Pin 16): Receiver 3 Inverting Input.

R2 B (Pin 17): Receiver 2 Noninverting Input.

R2 A (Pin 18): Receiver 2 Inverting Input.

D3/R1 B (Pin 19): Receiver 1 Noninverting Input and
Driver 3 Noninverting Output.

D3/R1 A (Pin 20): Receiver 1 Inverting Input and Driver 3
Inverting Output.

D2 B (Pin 21): Driver 2 Noninverting Output.

D2 A (Pin 22): Driver 2 Inverting Output.

D1 B (Pin 23): Driver 1 Noninverting Output.

D1 A (Pin 24): Driver 1 Inverting Output.

GND (Pin 25): Ground.

(Pin 26): Negative Supply Voltage. Connect a 3.3

capacitor to GND.

(Pin 27): Capacitor C2 Negative Terminal. Connect a

F capacitor between C2

and C2

(Pin 28): Capacitor C2 Positive Terminal. Connect a

F capacitor between C2

and C2

PI FU CTIO S

LTC1546

Figure 1. V.11 Driver DC Test Circuit

Figure 2. V.11 Driver AC Test Circuit

Figure 4. V.11, V.35 Receiver AC Test Circuit

Figure 3. Input Impedance Test Circuit

1546 F01

1546 F02

100

100pF

1546 F03

2(V

)

1546 F04

Figure 5. V.35 Driver Open-Circuit Test

1546 F05

125

1546 F06

125

Figure 6. V.35 Driver Test Circuit

1546 F07

125

1546 F08

125

1546 F09

Figure 7. V.35 Driver Common Mode
Impedance Test Circuit

Figure 8. V.35 Driver AC Test Circuit

Figure 9. V.35 Receiver DC Test Circuit

1546 F10

51.5

125

51.5

Figure 10. Receiver Common Mode
Impedance Test Circuit

1546 F11

1546 F12

Figure 11. V.28 Driver Test Circuit

Figure 12. V.28 Receiver Test Circuit

TEST CIRCUITS

LTC1546

SWITCHI G TI E WAVEFOR S

Figure 14. V.11, V.35 Receiver Propagation Delays

Figure 13. V.11, V.35 Driver Propagation Delays

OD2

1.5V

PLH

B A

PHL

1546 F14

f = 1MHz : t

10ns : t

10ns

INPUT

OUTPUT

1.5V

50%

10%

90%

PLH

B A

PHL

SKEW

1546 F13

1/2 V

f = 1MHz : t

10ns : t

10ns

50%

10%

90%

ODE SELECTIO

LTC1546 MODE NAME

DCE/DTE

Not Used (Default V.11)

V.11

RS530A

V.11

RS530

V.11

X.21

V.11

V.35

RS449/V.36

V.11

V.28/RS232

V.28

No Cable

Not Used (Default V.11)

V.11

RS530A

V.11

RS530

V.11

X.21

V.11

V.35

RS449/V.36

V.11

V.28/RS232

V.28

No Cable

Table 1

LTC1546

Figure 15. V.28 Driver Propagation Delays

Figure 16. V.28 Receiver Propagation Delays

1.3V

0.8V

1.7V

2.4V

PHL

PLH

1546 F16

1.5V

PHL

PLH

1546 F15

SR = 6V

SWITCHI G TI E WAVEFOR S

Overview

The LTC1546 and LTC1544 form a complete software-
selectable DTE or DCE interface port that supports the
RS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21
protocols. Cable termination is provided on-chip, elimi-
nating the need for discrete termination designs.

A complete DCE-to-DTE interface operating in EIA530
mode is shown in Figure 17. The LTC1546 half of each port
is used to generate and appropriately terminate the clock
and data signals. The LTC1544 is used to generate the
control signals along with LL (Local Loopback).

Mode Selection

The interface protocol is selected using the mode select
pins M0, M1 and M2 (see Table 1).

For example, if the port is configured as a V.35 interface,
the mode selection pins should be M2 = 1, M1 = 0, M0 = 0.
For the control signals, the drivers and receivers will
operate in V.28 (RS232) electrical mode. For the clock and
data signals, the drivers and receivers will operate in V.35

electrical mode. The DCE/DTE pin will configure the port
for DCE mode when high, and DTE when low.

The interface protocol may be selected simply by plugging
the appropriate interface cable into the connector. The
mode pins are routed to the connector and are left uncon-
nected (1) or wired to ground (0) in the cable as shown in
Figure 18. The internal pull-up current sources will ensure
a binary 1 when a pin is left unconnected.

The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or V

When the cable is removed, leaving all mode pins uncon-
nected, the LTC1546/LTC1544 will enter no-cable mode.
In this mode the LTC1546/LTC1544 supply current drops
to less than 500

A and the LTC1546/LTC1544 driver

outputs are forced into a high impedance state. At the
same time, the R2 and R3 receivers of the LTC1546 are
differentially terminated with 103

and the other receiv-

ers on the LTC1546 and LTC1544 are terminated with
30k

to ground.

APPLICATIO S I FOR ATIO

LTC1546

Figure 17. Complete Multiprotocol Interface in EIA530 Mode

LTC1546

DCE

DTE

LTC1546

1546 F17

103

LTC1544

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

SERIAL

CONTROLLER

103

SCTE

103

TXD

LTC1544

TXD

SCTE

TXC

RXC

RXD

RTS

DTR

DCD

DSR

CTS

RTS

DTR

DCD

DSR

CTS

RTS

DTR

DCD

DSR

CTS

SERIAL

CONTROLLER

Cable Termination

Traditional implementations used expensive relays to
switch resistors or required the user to change termina-
tion modules every time a new interface standard was
selected. Switching the terminations with FETs is difficult
because the FETs must remain off when the signal voltage
is beyond the supply voltage. Alternatively, custom cables

may contain termination in the cable head or route signals
to various terminations on the board.

The LTC1546/LTC1544 chipset solves the cable termina-
tion switching problem by automatically providing the
appropriate termination and switching on-chip for the
V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35
electrical protocols.

APPLICATIO S I FOR ATIO

LTC1546

V.10 (RS423) Interface

All V.10 drivers and receivers necessary for the RS449,
EIA530, EIA530-A, V.36 and X.21 protocols are imple-
mented on the LTC1544.

A typical V.10 unbalanced interface is shown in Figure 19.
A V.10 single-ended generator with output A and ground
C is connected to a differential receiver with input A

con-

nected to A, and ground C

connected via the signal return

to ground C. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 20.

The V.10 receiver configuration in the LTC1544 is shown
in Figure 21. In V.10 mode, switch S3 inside the LTC1544
is turned off. The noninverting input is disconnected
inside the LTC1544 receiver and connected to ground. The
cable termination is then the 30k input impedance to
ground of the LTC1544 V.10 receiver.

V.11 (RS422) Interface

A typical V.11 balanced interface is shown in Figure 22. A
V.11 differential generator with outputs A and B and
ground C is connected to a differential receiver with input
A

connected to A, input B

connected to B, and ground C

connected via the signal return to ground C. The V.11

Figure 18: Single Port DCE V.35 Mode Selection in the Cable

CABLE

1546 F18

LTC1546

LTC1544

CONNECTOR

(DATA)

DCE/DTE

(DATA)

Figure 20. V.10 Receiver Input Impedance

Figure 19. Typical V.10 Interface

GENERATOR

BALANCED

INTERCONNECTING

CABLE

LOAD

CABLE

TERMINATION

RECEIVER

1546 F19

10V

3.25mA

10V

1546 F20

APPLICATIO S I FOR ATIO

LTC1546

interface has a differential termination at the receiver end
that has a minimum value of 100

. The termination

resistor is optional in the V.11 specification, but for the
high speed clock and data lines, the termination is essen-
tial to prevent reflections from corrupting the data. The
receiver inputs must also be compliant with the imped-
ance curve shown in Figure 20.

In V.11 mode, all switches are off except S1 of the
LTC1546's receivers which connects a 103

differential

termination impedance to the cable as shown in Figure
23

. The LTC1544 only handles control signals, so no

termination other than its V.11 receivers' 30k input imped-
ance is necessary.

V.28 (RS232) Interface

A typical V.28 unbalanced interface is shown in Figure 24.
A V.28 single-ended generator with output A and ground
C is connected to a single-ended receiver with input A

Figure 22. Typical V.11 Interface

Figure 21. V.10 Receiver Configuration

20k

LTC1544

RECEIVER

1546 F21

R8
6k

R6
10k

R7
10k

GND

20k

GENERATOR

BALANCED

INTERCONNECTING

CABLE

LOAD

CABLE

TERMINATION

RECEIVER

100

MIN

1546 F22

Figure 24. Typical V.28 Interface

Figure 25. V.28 Receiver Configuration

Figure 23. V.11 Receiver Configuration

124

20k

LTC1546

RECEIVER

1546 F23

R1
51.5

R8
6k

R2
51.5

R6
10k

R7
10k

GND

20k

connected to A and ground C

connected via the signal

return to ground C.

In V.28 mode, S3 is closed inside the LTC1546/LTC1544
which connects a 6k (R8) impedance to ground in parallel
with 20k (R5) plus 10k (R6) for a combined impedance of
5k as shown in Figure 25. Proper termination is only pro-
vided when the B input of the receivers is floating, since S1
of the LTC1546's R2 and R3 receivers remains on in V.28
mode

. The noninverting input is disconnected inside the

LTC1546/LTC1544 receiver and connected to a TTL level
reference voltage to give a 1.4V receiver trip point.

GENERATOR

BALANCED

INTERCONNECTING

CABLE

LOAD

CABLE

TERMINATION

RECEIVER

1546 F24

124

20k

LTC1546

RECEIVER

1546 F25

R1
51.5

R8
6k

R2
51.5

R6
10k

R7
10k

GND

20k

Actually, there is no switch S1 in receivers R2 and R3. However, for simplicity, all termination

networks on the LTC1546 can be treated identically if it is assumed that an S1 switch exists and is
always closed on the R2 and R3 receivers.

APPLICATIO S I FOR ATIO

LTC1546

V.35 Interface

A typical V.35 balanced interface is shown in Figure 26. A
V.35 differential generator with outputs A and B and
ground C is connected to a differential receiver with input
A

connected to A, input B

connected to B, and ground C

connected via the signal return to ground C. The V.35
interface requires a T or delta network termination at the
receiver end and the generator end. The receiver differen-
tial impedance measured at the connector must be
100

, and the impedance between shorted termi-

nals (A

and B

)

and ground (C

must be 150

In V.35 mode, both switches S1 and S2 inside the LTC1546
are on, connecting a T network impedance as shown in
Figure 27. The 30k input impedance of the receiver is
placed in parallel with the T network termination, but does
not affect the overall input impedance significantly.

The generator differential impedance must be 50

150

and the impedance between shorted terminals (A

and B) and ground (C) must be 150

No-Cable Mode

The no-cable mode (M0 = M1 = M2 = 1) is intended for
the case when the cable is disconnected from the con-
nector. The charge pump, bias circuitry, drivers and
receivers are turned off, the driver outputs are forced into
a high impedance state, and the supply current drops to
less than 200

A. Note that the LTC1546's R2 and R3

receivers continue to be terminated by a 103

differen-

tial impedance.

Charge Pump

The LTC1546 uses an internal capacitive charge pump to
generate V

and V

as shown in Figure 28. A voltage

doubler generates about 8V on V

and a voltage inverter

generates about 7.5V on V

. Four 1

F surface mounted

tantalum or ceramic capacitors are required for C1, C2, C3
and C4. The V

capacitor C5 should be a minimum of

3.3

F. All capacitors are 16V and should be placed as close

as possible to the LTC1546 to reduce EMI.

Figure 28. Charge Pump

Figure 27. V.35 Receiver Configuration

Figure 26. Typical V.35 Interface

GENERATOR

BALANCED

INTERCONNECTING

CABLE

LOAD

CABLE

TERMINATION

RECEIVER

1546 F26

125

124

20k

LTC1546

RECEIVER

1546 F27

R1
51.5

R8
6k

R2
51.5

R6
10k

R7
10k

GND

20k

1546 F28

C3
1

C4
1

C1
1

C2
1

C5
3.3

LTC1546

GND

Receiver Fail-Safe

All LTC1546/LTC1544 receivers feature fail-safe opera-
tion in all modes. If the receiver inputs are left floating or
are shorted together by a termination resistor, the receiver
output will always be forced to a logic high.

DTE vs DCE Operation

The DCE/DTE pin acts as an enable for Driver 3/Receiver
1 in the LTC1546, and Driver 3/Receiver 1 and Driver 4/
Receiver 4 in the LTC1544. The INVERT pin in the LTC1544
allows the Driver 4/Receiver 4 enable to be high or low true
polarity.

APPLICATIO S I FOR ATIO

LTC1546

The LTC1546/LTC1544 can be configured for either DTE
or DCE operation in one of two ways: a dedicated DTE or
DCE port with a connector of appropriate gender or a port
with one connector that can be configured for DTE or DCE
operation by rerouting the signals to the LTC1546/LTC1544
using a dedicated DTE cable or dedicated DCE cable.

A dedicated DTE port using a DB-25 male connector is
shown in Figure 29. The interface mode is selected by logic
outputs from the controller or from jumpers to either V

or GND on the mode select pins. A dedicated DCE port
using a DB-25 female connector is shown in Figure 30.

A port with one DB-25 connector, that can be configured
for either DTE or DCE operation is shown in Figure 31. The
configuration requires separate cables for proper signal
routing in DTE or DCE operation. For example, in DTE
mode, the TXD signal is routed to Pins 2 and 14 via the
LTC1546's Driver 1. In DCE mode, Driver 1 now routes the
RXD signal to Pins 2 and 14.

Multiprotocol Interface with RL, LL, TM
and a DB-25 Connector

If the RL, LL and TM signals are implemented, there are not
enough drivers and receivers available in the LTC1546/
LTC1544. In Figure 32, the required control signals are
handled by the LTC1545. The LTC1545 has an additional
single-ended driver/receiver pair that can handle two more
optional control signals such as TM and RL.

Cable-Selectable Multiprotocol Interface

A cable-selectable multiprotocol DTE/DCE interface is
shown in Figure 33. The select lines M0, M1 and DCE/DTE
are brought out to the connector. The mode is selected by
the cable by wiring M0 (connector Pin 18) and M1 (con-
nector Pin 21) and DCE/DTE (connector Pin 25) to ground
(connector Pin 7) or letting them float. If M0, M1 or DCE/
DTE is floating, internal pull-up current sources will pull
the signals to V

. The select bit M2 is hard wired to V

When the cable is pulled out, the interface will go into the
no-cable mode.

Compliance Testing

The LTC1546/LTC1544 chipset has been tested by TUV
Telecom Services Inc. and passed the NET1, NET2 and
TBR2 requirements. Copies of the test reports are avail-
able from LTC or TUV Telecom Services.

The titles of the reports are:

NET1 and NET2: Test Report No. NET2/091301/99.

TBR2: Test Report No. CRT2/091301/99.

The address of TUV Telecom Services Inc. is:

TUV Telecom Services Inc.
Type Approval Division
1775 Old Highway 8, Ste 107
St. Paul, MN 55112 USA
TEL: +1 (612) 639-0775
FAX: +1 (612) 639-0873

APPLICATIO S I FOR ATIO

LTC1546

Figure 29. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector

LTC1544

RTS

DTR

DSR

DCD

CTS

LTC1546

TXD

SCTE

TXC

RXC

RXD

DCE/DTE

GND

1546 F29

C2
1

C5
1

C3
1

C4
3.3

SCTE B

RTS A (105)

RTS B

DTR A (108)

DTR B

CTS A (106)

CTS B

LL A (141)

SHIELD

DB-25 MALE

CONNECTOR

DCD A (109)

DCD B

DSR A (107)

DSR B

CHARGE

PUMP

INVERT

C11
1

C10
1

C9
1

DCE/DTE

TXD A (103)

TXD B

TXC A (114)

RXC A (115)

RXD A (104)

TXC B

RXC B

RXD B

SCTE A (113)

TYPICAL APPLICATIO S

LTC1546

Figure 30. Controller-Selectable DCE Port with DB-25 Connector

LTC1544

CTS

DSR

DTR

DCD

RTS

LTC1546

RXD

RXC

TXC

SCTE

TXD

DCE/DTE

GND

1546 F30

C2
1

C5
1

C3
1

C4
3.3

RXC B

CTS A (106)

CTS B

DSR A (107)

DSR B

RTS A (105)

RTS B

LL A (141)

SGND (102)

SHIELD (101)

DB-25 FEMALE

CONNECTOR

DCD A (109)

DCD B

DTR A (108)

DTR B

CHARGE

PUMP

INVERT

C11
1

C10
1

C9
1

DCE/DTE

RXD A (104)

RXD B

TXC A (114)

SCTE A (113)

TXD A (103)

TXC B

SCTE B

TXD B

RXC A (115)

TYPICAL APPLICATIO S

LTC1546

Figure 31. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector

LTC1544

LTC1546

DTE_TXD/DCE_RXD

DTE_SCTE/DCE_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

DTE_LL/DCE_LL

DCE/DTE

GND

1546 F31

C2
1

C5
1

C3
1

C4
3.3

SCTE B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

LL A

SHIELD

DB-25

CONNECTOR

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

LL A

DCD A

DCD B

DTR A

DTR B

CHARGE

PUMP

INVERT

C11
1

C10
1

C9
1

DCE/DTE

TXD A

TXD B

TXC A

RXC A

RXD A

TXC B

RXC B

RXD B

TXC A

SCTE A

TXD A

TXC B

SCTE B

TXD B

SCTE A

RXC B

RXD A

DTE

DCE

RXD B

RXC A

TYPICAL APPLICATIO S

LTC1546

Figure 32. Controller-Selectable Multiprotocol DTE/DCE Port with RL, LL, TM and DB-25 Connector

LTC1545

GND

1,19

2,20

R4EN

D4ENB

DCE/DTE

*OPTIONAL

LTC1546

DTE_TXD/DCE_RXD

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

DTE_LL/DCE_RI

DTE_RI/DCE_LL

DTE_TM/DCE_RL

DTE_RL/DCE_TM

DTE_SCTE/DCE_RXC

DCE/DTE

1546 F32

C2
1

C5
1

C3
1

C4
3.3

TXD A

TXD B

SCTE A

SCTE B

RXD A

RXD B

RXC A

RXC B

RXC A

RXC B

RXD A

RXD B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

SHIELD

DB-25

CONNECTOR

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

TXC A

TXC B

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

DCD A

DCD B

DTR A

DTR B

CHARGE

PUMP

DTE

DCE

C11
1

C10
1

C9
1

TYPICAL APPLICATIO S

LTC1546

Figure 33. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector

LTC1544

LTC1546

DTE_TXD/DCE_RXD

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

DTE_SCTE/DCE_RXC

DCE/DTE

GND

1546 F33

C2
1

C5
1

C3
1

C4
3.3

RXD A

RXD B

RXC A

RXC B

RXC A

RXC B

RXD A

RXD B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

SHIELD

DCE/DTE

DB-25

CONNECTOR

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

TXC A

TXC B

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

DCD A

DCD B

DTR A

DTR B

INVERT

DCE/DTE

DTE

DCE

MODE

V.35

RS449, V.36

RS232

PIN 18

PIN 7

PIN 21

PIN 7

CABLE WIRING FOR MODE SELECTION

MODE

PIN 25

DTE

PIN 7

DCE

CABLE WIRING FOR
DTE/DCE SELECTION

C11
1

C10
1

C9
1

CHARGE

PUMP

TXD A

TXD B

SCTE A

SCTE B

TYPICAL APPLICATIO S

LTC1546

1546i LT/TP 1299 4K · PRINTED IN USA

Dimensions in inches (millimeters) unless otherwise noted.

LINEAR TECHNOLOGY CORPORATION 1999

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1321

Dual RS232/RS485 Transceiver

Two RS232 Driver/Receiver Pairs or Two RS485 Driver/Receiver Pairs

LTC1334

Single 5V RS232/RS485 Multiprotocol Transceiver

Two RS232 Driver/Receiver or Four RS232 Driver/Receiver Pairs

LTC1343

Software-Selectable Multiprotocol Transceiver

4-Driver/4-Receiver for Data and Clock Signals

LTC1344A

Software-Selectable Cable Terminator

Perfect for Terminating the LTC1543 (Not Needed with LTC1546)

LTC1345

Single Supply V.35 Transceiver

3-Driver/3-Receiver for Data and Clock Signals

LTC1346A

Dual Supply V.35 Transceiver

3-Driver/3-Receiver for Data and Clock Signals

LTC1543

Software-Selectable Multiprotocol Transceiver

Terminated with LTC1344A for Data and Clock Signals, Companion to
LTC1544 or LTC1545 for Control Signals

LTC1544

Software-Selectable Multiprotocol Transceiver

Companion to LTC1546 or LTC1543 for Control Signals Including LL

LTC1545

Software-Selectable Multiprotocol Transceiver

5-Driver/5-Receiver Companion to LTC1546 or LTC1543
for Control Signals Including LL, TM and RL

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

G28 SSOP 1098

0.13 0.22

(0.005 0.009)

0.55 0.95

(0.022 0.037)

5.20 5.38**

(0.205 0.212)

7.65 7.90

(0.301 0.311)

2 3

6 7 8

9 10 11 12

10.07 10.33*

(0.397 0.407)

22 21 20 19 18 17 16 15

1.73 1.99

(0.068 0.078)

0.05 0.21

(0.002 0.008)

0.65

(0.0256)

BSC

0.25 0.38

(0.010 0.015)

NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

PACKAGE DESCRIPTIO

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1546IG