1
LTC1588/LTC1589/LTC1592
1588992fa
s
Six Programmable Output Ranges
Unipolar Mode: 0V to 5V, 0V to 10V
Bipolar Mode:
5V,
10V,
2.5V, 2.5V to 7.5V
s
1LSB Max DNL and INL Over the Industrial
Temperature Range
s
Glitch Impulse < 2nV-s
s
16-Lead SSOP Package
s
Power-On Reset to 0V
s
Asynchronous Clear to 0V for All Ranges
The LTC
1588/LTC1589/LTC1592 are serial input 12-/14-
/16-bit multiplying current output DACs that operates
from a single 5V supply. These SoftSpan
TM
DACs can be
software-programmed for either unipolar or bipolar mode
through a 3-wire SPI interface. In either mode, the voltage
output range can also be software-programmed. Two
output ranges in unipolar mode and four output ranges in
bipolar mode are available.
INL and DNL are accurate to 1LSB over the industrial
temperature range in both unipolar and bipolar modes.
True 16-bit 4-quadrant multiplication is achieved with
on-chip four quadrant multiplication resistors. The
LTC1588/LTC1589/LTC1592 are available in a 16-lead
SSOP package.
These devices include an internal deglitcher circuit that
reduces the glitch impulse to less than 2nV-s (typ).
The asynchronous clear pin resets the LTC1588/LTC1589/
LTC1592 to 0V in unipolar or bipolar mode.
s
Process Control and Industrial Automation
s
Precision Instrumentation
s
Direct Digital Waveform Generation
s
Software-Controlled Gain Adjustment
s
Automatic Test Equipment
12-/14-/16-Bit SoftSpan DACs
with Programmable Output Range
+
1/2 LT
1469
+
1/2 LT1469
16-BIT DAC WITH SPAN ADJUST
LTC1592
R
COM
1
R1
2
V
CC
0.1
F
9
R2
R2
R1
16
R
OFS
3
7
5
V
REF
5V
6
REF
15
R
FB
I
OUT1
V
OUT
4
5V
5
1
2
3
I
OUT2
AGND
GND
CLR
CS/LD
SCK
SDI
SDO
6
7
8
14
13
12
11
10
C2
150pF
C1
15pF
1588992 TA01
15V
15V
8
4
0.1
F
0.1
F
, LTC and LT are registered trademarks of Linear Technology Corporation.
Programmable Output Range 16-Bit SoftSpan DAC
DIGITAL INPUT CODE
0
INTEGRAL NONLINEARITY (LSB)
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
16384
32768
1588992 TA02
49152
65535
V
REF
= 5V
ALL OUTPUT RANGES
LTC1592 Integral Nonlinearity
SoftSpan is a trademark of Linear Technology Corporation.
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1588/LTC1589/LTC1592
1588992fa
T
JMAX
= 150
C,
JA
= 125
C/ W
ORDER PART
NUMBER
(Note 1)
V
CC
to AGND, GND ...................................... 0.3V to 7V
AGND to GND .............................. 0.3V to (V
CC
+ 0.3V)
GND to AGND .............................. 0.3V to (V
CC
+ 0.3V)
R
COM
to AGND, GND ................................ 0.3V to 12V
REF to AGND, GND ................................................
15V
R
OFS
, R
FB
, R1, R2 to AGND, GND ..........................
15V
Digital Inputs to AGND, GND ....... 0.3V to (V
CC
+ 0.3V)
I
OUT1
, I
OUT2
to AGND, GND .......... 0.3V to (V
CC
+ 0.3V)
Maximum Junction Temperature .......................... 150
C
Operating Temperature Range
LTC1588C/LTC1589C/LTC1592C ........... 0
C to 70
C
LTC1588I/LTC1589I/LTC1592I ........... 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
LTC1588CG
LTC1588IG
LTC1589CG
LTC1589IG
LTC1592ACG
LTC1592AIG
LTC1592BCG
LTC1592BIG
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= T
MIN
to T
MAX
,
V
CC
= 5V, V
REF
= 5V, I
OUT2
= AGND = GND = 0V.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
1
2
3
4
5
6
7
8
TOP VIEW
G PACKAGE
16-LEAD PLASTIC SSOP
16
15
14
13
12
11
10
9
R2
REF
CLR
CS/LD
SCK
SDI
SDO
V
CC
R
COM
R1
R
OFS
R
FB
I
OUT1
I
OUT2
AGND
GND
PACKAGE/ORDER I FOR ATIO
U
U
W
ABSOLUTE AXI U RATI GS
W
W
W
U
LTC1588
LTC1589
LTC1592B
LTC1592A
SYMBOL PARAMETER
CONDITIONS
TEMPERATURE
MIN TYP MAX
MIN TYP MAX
MIN TYP MAX
MIN TYP MAX
UNITS
Accuracy
Resolution
q
12
14
16
16
Bits
INL
Integral
(Notes 2, 3)
T
A
= 25
C
1
1
2
0.3
1
LSB
Nonlinearity
T
MIN
to T
MAX
q
1
1
2
0.4
1
LSB
DNL
Differential
Guaranteed
T
MIN
to T
MAX
q
1
1
1
0.2
1
LSB
Nonlinearity
Monotonic (Note 3)
GE
Gain Error
All Output Ranges
T
A
= 25
C
0.20
3
1.0
4
3
16
2
16
LSB
(Note 3)
T
MIN
to T
MAX
q
0.22
3
1.3
6
4
24
3
16
LSB
BZE
Bipolar Zero Error All Bipolar Ranges
T
A
= 25
C
1
2.5
10
5
LSB
(Note 3)
T
MIN
to T
MAX
q
1
4.0
16
8
LSB
Gain Temperature
Gain/
Temperature
q
3
3
3
1
3
ppm/
C
Coefficient
(Note 4)
I
LKG
I
OUT1
Leakage
(Note 5)
T
A
= 25
C
5
5
5
5
nA
Current
T
MIN
to T
MAX
q
15
15
15
15
nA
PSRR
Power Supply
V
CC
= 5V
10%
q
0.01
0.15
0.05
0.5
2
0.2
2
LSB/V
Rejection
3
LTC1588/LTC1589/LTC1592
1588992fa
ELECTRICAL CHARACTERISTICS
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= T
MIN
to T
MAX
, V
CC
= 5V, V
REF
= 5V, I
OUT2
= AGND = GND = 0V.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input
R
REF
DAC Input Resistance (Unipolar)
(Note 6)
q
5
7
10
k
R1, R2
R1, R2 Resistance
(Notes 6, 11)
q
10
14
20
k
R
OFS
Offset Resistance (Bipolar)
5V,
10V,
2.5V Ranges
q
10
14
20
k
2.5V to 7.5V Range
q
20
28
40
k
R
FB
Feedback Resistance (Unipolar)
5V Range
q
5
7
10
k
10V Range
q
10
14
20
k
Feedback Resistance (Bipolar)
5V and 2.5V to 7.5V Ranges
q
10
14
20
k
10V Range
q
20
28
40
k
2.5V Range
q
5
7
10
k
Analog Outputs (Note 4)
C
OUT
Output Capacitance (I
OUT1
)
DAC Load All 1s
160
pF
DAC Load All 0s
100
pF
AC Performance (Note 4)
Settling Time
5V Range, 0V to 5V Step with LT1468 (Note 7)
2
s
Midscale Glitch Impulse
(Note 10)
2
nV-s
Multiplying Feedthrough Error
V
REF
=
10V, 10kHz Sine Wave
1
mV
P-P
THD
Total Harmonic Distortion
(Note 8) Multiplying
108
dB
Output Noise Voltage Density
(Note 9) At I
OUT1
11
nV/
Hz
Digital Inputs
V
IH
Digital Input High Voltage
q
2.4
V
V
IL
Digital Input Low Voltage
q
0.8
V
I
IN
Digital Input Current
q
1
A
C
IN
Digital Input Capacitance
V
IN
= 0V (Note 4)
q
8
pF
Digital Outputs
V
OH
Digital Output High Voltage
I
OH
= 200
A
q
4
V
V
OL
Digital Output Low Voltage
I
OL
= 1.6mA
q
0.4
V
Timing Characteristics
t
1
Serial Input Valid to SCK Setup Time
q
60
ns
t
2
Serial Input Valid to SCK Hold Time
q
0
ns
t
3
SCK Pulse Width High
q
35
ns
t
4
SCK Pulse Width Low
q
35
ns
t
5
CS/LD Pulse High Width
q
360
ns
t
6
LSB SCK High to CS/LD High
q
35
ns
t
7
CS/LD Low to SCK High
q
0
ns
t
8
SCK to SDO Propagation Delay
C
LOAD
= 50pF
q
20
180
ns
t
9
SCK Low to CS/LD Low
q
35
ns
t
10
Clear Pulse Low Width
q
100
ns
t
11
CS/LD High to SCK Positive Edge
q
35
ns
SCK Frequency
Non-Daisy Chain (Note 12)
q
14.2
MHz
Daisy Chain (Note 13)
4.1
MHz
4
LTC1588/LTC1589/LTC1592
1588992fa
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
1LSB =
0.0015% of full scale =
15.3ppm of full scale
(LTC1592).
1LSB =
0.006% of full scale =
61.2ppm of full scale
(LTC1589).
1LSB = 0.024% of full scale =
244.8ppm of full scale
(LTC1588).
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: I
OUT1
with DAC register loaded to all 0s.
Note 6: Typical temperature coefficient is 100ppm/
C.
Note 7: To 0.0015% for a full-scale change, measured from the falling
edge of LD for the LTC1592 only.
Note 8: REF = 6V
RMS
at 1kHz. DAC register loaded with all 1s. Output
amplifier = LT1468.
ELECTRICAL CHARACTERISTICS
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= T
MIN
to T
MAX
, V
CC
= 5V, V
REF
= 5V, I
OUT2
= AGND = GND = 0V.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
V
CC
Supply Voltage
q
4.5
5
5.5
V
I
CC
Supply Current, V
CC
Digital Inputs = 0V or V
CC
q
10
A
Note 9: Calculation from e
n
=
4kTRB where: k = Boltzmann constant
(1.38E-23 J/
K); R = resistance (
); T = temperature (
K); B = bandwidth
(Hz).
Note 10: Midscale transition code: 32767 to 32768 for the LTC1592, 8191
to 8192 for the LTC1589, 2047 to 2048 for the LTC1588.
Note 11: R1 and R2 are measured between R1 and R
COM
, R2 and R
COM
.
Note 12: If a continuous clock is used with data changing on the rising
edge of SCK, setup and hold time (t
1
, t
2
) will limit the maximum clock
frequency. If data changes on the falling edge of SCK then the setup time
will limit the maximum clock frequency to 8MHz (continuous 50% duty
cycle clock).
Note 13: SDO propagation delay and SDI setup time (t
8
, t
1
) limit the
maximum clock frequency for daisy chaining.
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
TIME (
s)
0
OUTPUT VOLTAGE (mV)
10
0
10
0.6
1.0
1588992 G03
20
30
40
0.2
0.4
0.8
20
30
40
USING AN LT1468
C
FEEDBACK
= 30pF
V
REF
= 10V
1nV-s TYPICAL
Midscale Glitch Impulse
(LTC1588/LTC1589/LTC1592)
Supply Current vs Input Voltage
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
3
4
5
4
1588992 G09
2
1
0
1
2
3
5
V
CC
= 5V
ALL DIGITAL INPUTS
TIED TOGETHER
Logic Threshold vs Supply Voltage
SUPPLY VOLTAGE (V)
0
0
LOGIC THRESHOLD (V)
0.5
1.0
1.5
2.0
3.0
1
2
3
4
1588992 G10
5
7
6
2.5
5
LTC1588/LTC1589/LTC1592
1588992fa
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
(LTC1588)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUT CODE
0
INTEGRAL NONLINEARITY (LSB)
0.2
0.6
1.0
1588992 G11
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
800
1600
2400
3200
4095
DIGITAL INPUT CODE
0
DIFFERENTIAL NONLINEARITY (LSB)
0.2
0.6
1.0
1588992 G12
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
800
1600
2400
3200
4095
(LTC1589)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUT CODE
0
INTEGRAL NONLINEARITY (LSB)
0.2
0.6
1.0
1588992 G13
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
4112
8224
12336
16383
DIGITAL INPUT CODE
0
DIFFERENTIAL NONLINEARITY (LSB)
0.2
0.6
1.0
1588992 G14
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
4112
8224
12336
16383
Integral Nonlinearity
vs Reference Voltage
in Unipolar Mode
REFERENCE VOLTAGE (V)
10
INTEGRAL NONLINEARITY (LSB)
0.2
0.6
1.0
6
1588992 G05
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
6
2
2
8
8
4
0
4
10
Integral Nonlinearity (INL)
DIGITAL INPUT CODE
0
1.0
INTEGRAL NONLINEARITY (LSB)
0.8
0.4
0.2
0
1.0
0.4
16384
32768
1588992 G01
0.6
0.6
0.8
0.2
49152
65535
DIGITAL INPUT CODE
0
1.0
DIFFERENTIAL NONLINEARITY (LSB) 0.8
0.4
0.2
0
1.0
0.4
16384
32768
1588992 G02
0.6
0.6
0.8
0.2
49152
65535
Differential Nonlinearity (DNL)
(LTC1592)
6
LTC1588/LTC1589/LTC1592
1588992fa
REFERENCE VOLTAGE (V)
10
INTEGRAL NONLINEARITY (LSB)
0.2
0.6
1.0
6
1588992 G06
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
6
2
2
8
8
4
0
4
10
Integral Nonlinearity
vs Reference Voltage
in Bipolar Mode
Differential Nonlinearity
vs Reference Voltage
in Unipolar Mode
REFERENCE VOLTAGE (V)
10
DIFFERENTIAL NONLINEARITY (LSB)
0.2
0.6
1.0
6
1588992 G07
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
6
2
2
8
8
4
0
4
10
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Differential Nonlinearity
vs Reference Voltage
in Bipolar Mode
REFERENCE VOLTAGE (V)
10
DIFFERENTIAL NONLINEARITY (LSB)
0.2
0.6
1.0
6
1588992 G08
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
6
2
2
8
8
4
0
4
10
(LTC1592)
U
U
U
PI FU CTIO S
R
COM
(Pin 1): Center Tap Point of the Two Bipolar Resis-
tors R1 and R2. Normally tied to the inverting input of an
external amplifier. When these resistors are not used,
connect this pin to ground. The absolute maximum volt-
age range on this pin is 0.3V to 12V.
R1 (Pin 2): Bipolar Resistor R1. The main reference input
V
REF
, typically 5V. Accepts up to
15V. Normally tied to
R
OFS
(Pin 3) and the reference input voltage V
REF
(5V).
When not used connect this pin to ground.
R
OFS
(Pin 3): Bipolar Offset Network. This pin provides the
offset of the output voltage range for bipolar modes.
Accepts up to
15V. Normally tied to R1 and the reference
input voltage V
REF
(5V). Alternatively, this pin may be
driven from a different voltage than V
REF
.
R
FB
(Pin 4): Feedback Network. Normally tied to the output
of the current to voltage converter op amp. Range limited
to
15V.
Full-Scale Settling Waveform
GATED
SETTLING
WAVEFORM
500
V/DIV
LD PULSE
5V/DIV
500ns/DIV
1592 G04
USING LT1468 OP AMP
C
FEEDBACK
= 20pF
0V TO 10V STEP
7
LTC1588/LTC1589/LTC1592
1588992fa
I
OUT1
(Pin 5): True DAC Current Output. Tied to the
inverting input of the current-to-voltage op amp.
I
OUT2
(Pin 6): Complement of DAC Current Output. Nor-
mally tied to AGND pin.
AGND (Pin 7): Analog Ground. Tie to the system's analog
ground plane.
GND (Pin 8): Ground. Tie to the system's analog ground
plane.
V
CC
(Pin 9): Positive Supply Input. 4.5V
V
CC
5.5V.
Requires a 0.1
F bypass capacitor to ground.
SDO (Pin 10): Serial Data Output. Data at this pin is shifted
out on the rising edge of SCK.
SDI (Pin 11): Serial Data Input.
U
U
U
PI FU CTIO S
FU CTIO TABLE
U
U
Table 1
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SREG
DATA WORD
Dn IN INPUT
SHIFT REGISTER
Dn
X
Dn
Dn
Dn
Dn
Dn
Dn
Dn
X
BUF1
INPUT
BUFFER
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
No Change
DAC
OUTPUT
RANGE
No Change
No Change
No Change
5V
10V
5V
10V
2.5V
2.5V to 7.5V
No Change
BUF2
DAC
BUFFER
(DAC OUTPUT)
No Change
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
No Change
Copy Data Word Dn in SReg to Buf1
Copy the Data in Buf1 to Buf2
Copy Data Word Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to
5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to
10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to
2.5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to 2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
No Operation
Internal Register Status
OPERATION
EACH COMMAND IS EXECUTED
ON THE RISING EDGE OF CS/LD
COMMAND
Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code.
SCK (Pin 12): Serial Interface Clock. Data on the SDI pin
is shifted into the input shift register on rising edge of SCK.
CS/LD (Pin 13): Chip Select Input. When CS/LD is low,
SCK is enabled for shifting data into the input shift register.
When CS/LD is pulled high, SCK is disabled and the control
logic executes the control word (the first 4 bits of the input
data stream as shown in Table 1).
CLR (Pin 14): When CLR is taken to a logic low, it sets the
DAC output to 0V and all internal registers to zero code.
REF (Pin 15): DAC Reference Input. Typically 5V, accepts
up to
15V.
R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC
reference input REF (Pin 15) and the output of the inverting
amplifier tied to R
COM
(Pin 1).
8
LTC1588/LTC1589/LTC1592
1588992fa
BLOCK DIAGRA
W
12-/14-/16-BIT DAC
12/14/16
BITS
1588992 BD
BUFFER
12/14/16
BITS
12-/14-/16-BIT
DATA WORD
Dn
4 BIT
COMMAND
WORD
BUFFER
DECODER
24-BIT
SHIFT
REGISTER
SREG
8-BIT
SHIFT
REGISTER
SDO
SCK
SDI
CS/LD
BUF2
BUF1
SPAN ADJUST
SDI
SDO
CS/LD
SCK
1588992 TD
t
2
t
8
t
9
t
11
t
5
t
7
1
2
23
24
t
6
t
1
t
3
t
4
TI I G DIAGRA
U
W
W
9
LTC1588/LTC1589/LTC1592
1588992fa
OPERATIO
U
Serial Interface
When the CS/LD is brought to a logic low, the data on the
SDI input is loaded into the shift register on the rising edge
of the clock. A 4-bit command word (C3 C2 C1 C0),
followed by four "don't care" bits and 16 data bits
(MSB-first) is the minimum loading sequence required for
the LTC1588/LTC1589/LTC1592. When the CS/LD is
brought to a logic high, the clock is disabled internally and
the command word is executed.
If no daisy-chaining is required, the input stream can be
24-bit wide as shown in Figure 1a. The first four bits are the
command word, followed by four "don't care" bits, then a
16-bit data word. The last four bits (LSBs) of this 16-bit
data word are don't cares for the LTC1588. For the
LTC1589, the last 2 bits of the 16-bit data word are don't
cares.
If daisy-chaining is required or the input needs to be
written in two 16-bit wide segments, then the input stream
must be 32-bit wide and the first 8 bits loaded are "don't
care" bits. The remaining bits work the same as a 24-bit
stream which is described in the previous paragraph. The
output of the internal 32-bit shift register is available on the
SDO pin 32 clock cycles later.
Multiple LTC1588/LTC1589/LTC1592s may be daisy-
chained together by connecting the SDO pin to the SDI pin
of the next IC. The clock and CS/LD signals should remain
common to all ICs in the daisy-chain. The serial data is
clocked to all ICs, then the CS/LD signal is pulled high to
update all of them simultaneously.
Power-On Reset and Clear
When the power supply is first turned on, the LTC1588/
LTC1589/LTC1592 will power up in 5V unipolar mode (C3
C2 C1 C0 = 1000). All the internal registers are set to zeros
and the DAC is set to zero code.
The LTC1588/LTC1589/LTC1592 must first be pro-
grammed in either unipolar or bipolar mode. There are six
operating modes available and can be software-pro-
grammed by the command word. When a CLR signal is
brought to low, it clears all internal registers to zero. The
DAC output voltage goes to zero volts. If an update DAC
command (C3 C2 C1 C0 = 0001) is issued immediately
after the CLR signal, the DAC output remains at zero volts.
If a CLR signal is given within a 100ns interval immediately
after CS/LD goes high, the user should reload the output
range.
Output Range Programming
There are two output ranges available in unipolar mode
and four output ranges available in bipolar mode. See
Function Table for details. All output ranges are with re-
spect to a 5V reference input. When changing the LTC1588/
LTC1589/LTC1592 to a new mode, the command word
and data are given at the same time (24 or 32 bit). When
C3
COMMAND
DON'T CARE
DATA (16 BITS)
C2
C1
C0
X
X
X
X
D13
D14
D15
D12 D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
1588992 TD2
MSB
LSB
C3
COMMAND
DON'T CARE
DATA (14 BITS + 2 DON'T-CARE BITS)
C2
C1
C0
X
X
X
X
D13 D12 D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
X
X
1588992 TD3
MSB
LSB
C3
COMMAND
DON'T CARE
DATA (12 BITS + 4 DON'T-CARE BITS)
C2
C1
C0
X
X
X
X
D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
X
X
X
X
1588992 TD4
MSB
LSB
INPUT WORD (LTC1592)
INPUT WORD (LTC1589)
INPUT WORD (LTC1588)
10
LTC1588/LTC1589/LTC1592
1588992fa
Figure 1a. LTC1592 24-Bit Load Sequence (Minimum Input Word)
LTC1589 SDI Data Word = 14-Bit Input Code + 2 Don't Care Bits at LSB Positions
LTC1588 SDI Data Word = 12-Bit Input Code + 4 Don't Care Bits at LSB Positions
OPERATIO
U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C2
C1
C0
X
X
X
X
D15
D
14
D13
D
12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C3
CS/LD
SCK
SDI
CONTROL WORD
DON'T CARE
(RESERVED)
DATA WORD Dn
24-BIT DATA STREAM (CANNOT BE DAISY-CHAINED)
1588992 F01a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C2
C1
C0
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C3
X
X
X
X
X
X
X
X
CS/LD
SCK
SDI
CONTROL WORD
DON'T CARE
DATA WORD Dn
32-BIT DATA STREAM (CAN BE DAISY-CHAINED)
DON'T CARE
C2
C1
C0
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C3
X
X
X
X
X
X
X
X
SDO
CURRENT
32-BIT INPUT
WORD
1588992 F01b
PREVIOUS 32-BIT INPUT WORD
t
2
t
3
t
4
t
1
t
8
D15
17
SCK
SDI
SDO
PREVIOUS D14
PREVIOUS D15
18
D14
Figure 1b. LTC1592 32-Bit Load Sequence (Required for Daisy-Chain Operation)
LTC1589 SDI/SDO Data Word = 14-Bit Input Code + 2 Don't Care Bits at LSB Positions
LTC1588 SDI/SDO Data Word = 12-Bit Input Code + 4 Don't Care Bits at LSB Positions
11
LTC1588/LTC1589/LTC1592
1588992fa
APPLICATIO S I FOR ATIO
W
U
U
U
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC1592, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 2 and 3 contain equations for evaluating the effects
of op amp parameters on the LTC1592's accuracy when
programmed in a unipolar or bipolar output range. These
are the changes the op amp can cause to the INL, DNL,
unipolar offset, unipolar gain error, bipolar zero and bipo-
lar gain error. Tables 2 and 3 can also be used to determine
the effects of op amp parameters on the LTC1589 and the
LTC1588. However, the results obtained from Tables 2
and 3 are in 16-bit LSBs. Divide these results by 4
(LTC1589) and 16 (LTC1588) to obtain the correct LSB
sizing.
Table 4 contains a partial list of LTC precision op amps
recommended for use with the LTC1592. The easy-to-use
design equations simplify the selection of op amps to meet
the system's specified error budget. Select the amplifier
from Table 4 and insert the specified op amp parameters
in Table 3. Add up all the errors for each category to
determine the effect the op amp has on the accuracy of the
LTC1592. Arithmetic summation gives an (unlikely) worst-
case effect. A root-sum-square (RMS) summation pro-
duces a more realistic estimate.
Op amp offset will contribute mostly to output offset and
gain error and has minimal effect on INL and DNL. For the
LTC1592, a 250
V op amp offset will cause about 0.65LSB
INL degradation and 0.15LSB DNL degradation with a 10V
full-scale range (20V range in bipolar). For the LTC1592
programmed in a unipolar mode, the same 250
V op amp
offset will cause a 3.3LSB zero-scale error and a 3.3LSB
gain error with a 10V full-scale range.
CS/LD goes high, the mode changes and the DAC output
goes to a value corresponding to the data code.
Examples using the LTC1592:
1. Using a 24-bit loading sequence, load the unipolar
range of 0V to 10V with the DAC output at zero volt:
a) CS/LD
b) Clock SDI = 1001 XXXX 0000 0000 0000 0000
c) CS/LD ; then V
OUT
= 0V
2. Using a 24-bit loading sequence, load the bipolar range
of
5V and the DAC output at zero volt:
a) CS/LD
b) Clock SDI = 1010 XXXX 1000 0000 0000 0000
c) CS/LD ; then V
OUT
= 0V on the
5V range
3. Using a 32-bit load sequence, load the bipolar range of
10V with the DAC output voltage at 5V initially. Then
change the DAC output to 5V:
a) CS/LD
b) Clock SDI = XXXX XXXX 1011 XXXX 1100 0000 0000
0000
c) CS/LD ; then V
OUT
= 5V on the
10V range
Next, the bipolar range of
10V is retained and the DAC
output voltage is changed to V
OUT
= 5V:
a) CS/LD
b) Clock SDI = XXXX XXXX 0010 XXXX 0100 0000 0000
0000
c) CS/LD ; then V
OUT
= 5V on the
10V range
OPERATIO
U
12
LTC1588/LTC1589/LTC1592
1588992fa
While not directly addressed by the simple equations in
Tables 2 and 3, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp's data sheet to find the worst-case V
OS
and I
B
over temperature. Then, plug these numbers in the V
OS
and I
B
equations from Table 3 and calculate the tempera-
ture induced effects.
For applications where fast settling time is important, Appli-
cation Note 74, entitled "
Component and Measurement
Advances Ensure 16-Bit DAC Settling Time," offers a thor-
ough discussion of 16-bit DAC settling time and op amp
selection.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC1592 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC1592
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a DAC output voltage
error.
There are three primary error sources to consider when
selecting a precision voltage reference for 16-bit applica-
tions: output voltage initial tolerance, output voltage tem-
perature coefficient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
APPLICATIO S I FOR ATIO
W
U
U
U
Table 4. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC1588/LTC1589/LTC1592,
with Relevant Specifications
AMPLIFIER SPECIFICATIONS
VOLTAGE
CURRENT
SLEW
GAIN BANDWIDTH
t
SETTLING
POWER
V
OS
I
B
A
OL
NOISE
NOISE
RATE
PRODUCT
with LTC1592
DISSIPATION
AMPLIFIER
V
nA
V/mV
nV/
Hz
pA/
Hz
V/
s
MHz
s
mW
LT1001
25
2
800
10
0.12
0.25
0.8
120
46
LT1097
50
0.35
1000
14
0.008
0.2
0.7
120
11
LT1112 (Dual)
60
0.25
1500
14
0.008
0.16
0.75
115
10.5/Op Amp
LT1124 (Dual)
70
20
4000
2.7
0.3
4.5
12.5
19
69/Op Amp
LT1468
75
10
5000
5
0.6
22
90
2.5
117
LT1469 (Dual)
125
10
2000
5
0.6
22
90
2.5
123/Op Amp
( )
5V
V
REF
( )
5V
V
REF
( )
16.5k
A
VOL1
OP AMP
V
OS1
(mV)
I
B1
(nA)
A
VOL1
(V/V)
V
OS2
(mV)
I
B2
(mV)
A
VOL2
(V/V)
V
OS1
2.4
I
B1
0.0003
A1
0
0
0
INL (LSB)
( )
5V
V
REF
( )
5V
V
REF
( )
1.5k
A
VOL1
( )
66k
A
VOL2
( )
131k
A
VOL1
( )
131k
A
VOL1
( )
131k
A
VOL2
( )
131k
A
VOL2
V
OS1
0.6
I
B1
0.00008
A2
0
0
0
DNL (LSB)
( )
5V
V
REF
( )
5V
V
REF
V
OS1
13.2
I
B1
0.13
0
0
0
0
UNIPOLAR
OFFSET (LSB)
( )
5V
V
REF
( )
5V
V
REF
( )
5V
V
REF
V
OS1
13.2
I
B1
0.0018
A5
V
OS2
26.2
I
B2
0.1
BIPOLAR GAIN
ERROR (LSB)
( )
5V
V
REF
( )
5V
V
REF
(
)
(
)
( )
5V
V
REF
( )
5V
V
REF
A3 V
OS1
19.8
I
B1
0.01
0
A4 V
OS2
13.1
A4 I
B2
0.05
A4
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
( )
5V
V
REF
( )
5V
V
REF
( )
5V
V
REF
( )
5V
V
REF
( )
5V
V
REF
V
OS1
13.2
I
B1
0.0018
A5
V
OS2
26.2
I
B2
0.1
Table 3. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges
Table 2. Variables for Each Output Range That Adjust the
Equations in Table 3
OUTPUT RANGE
A1
A2
A3
A4
A5
5V
1.1
2
1
10V
2.2
3
1.5
5V
2
2
1.2
1
1.5
10V
4
4
1.2
1
2.5
2.5V
1
1
1.6
1
1
2.5V to 7.5V
1.9
3
1
0.5
1.5
13
LTC1588/LTC1589/LTC1592
1588992fa
APPLICATIO S I FOR ATIO
W
U
U
U
with low output voltage initial tolerance, like the LT1236
(
0.05%), minimizes the gain error caused by the refer-
ence; however, a calibration sequence that corrects for
system zero- and full-scale error is always recommended.
A reference's output voltage temperature coefficient af-
fects not only the full-scale error, but can also affect the
circuit's INL and DNL performance. If a reference is
chosen with a loose output voltage temperature coeffi-
cient, then the DAC output voltage along its transfer
characteristic will be very dependent on ambient condi-
tions. Minimizing the error due to reference temperature
coefficient can be achieved by choosing a precision
reference with a low output voltage temperature coeffi-
cient and/or tightly controlling the ambient temperature
of the circuit to minimize temperature gradients.
As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contrib-
ute a dominant share of the system's noise floor. This in
turn can degrade system dynamic range and signal-to-
noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practical
for the system resolution desired. Precision voltage refer-
ences, like the LT1236, produce low output noise in the
0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V
or 10V full-scale systems. However, as the circuit band-
widths increase, filtering the output of the reference may
be required to minimize output noise.
Table 5. Partial List of LTC Precision References Recommended
for Use with the LTC1588/LTC1589/LTC1592 with Relevant
Specifications
INITIAL
TEMPERATURE
0.1Hz to 10Hz
REFERENCE
TOLERANCE
DRIFT
NOISE
LT1019A-5,
0.05%
5ppm/
C
12
V
P-P
LT1019A-10
LT1236A-5,
0.05%
5ppm/
C
3
V
P-P
LT1236A-10
LT1460A-5,
0.075%
10ppm/
C
20
V
P-P
LT1460A-10
LT1790A-2.5
0.05%
10ppm/
C
12
V
P-P
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding techniques should be used. I
OUT2
must be tied
to the star ground with as low a resistance as possible.
When it is not possible to locate star ground close to I
OUT2
,
a low resistance trace should be used to route this pin to
star ground. This minimizes the voltage drop from this pin
to ground caused by the code dependent current flowing
to ground. When the resistance of this circuit board trace
becomes greater than 1
, a force/sense amplified con-
figuration should be used to drive this pin (see Figure 2).
This preserves the excellent accuracy (1LSB INL and DNL)
of the LTC1588/LTC1589/LTC1592.
An Isolated 16-Bit Subsystem Using the LTC1592
The circuit in Figure 4 is a complete example of an optically
isolated analog output subsystem that supports most of
the legacy ranges that are still common in industrial
environments. This circuit uses only two optoisolators,
the load pulse (CS/LD) being derived from a series of
transitions on the data line (SDI) after the clock (SCK) is
halted high. If a single chip microcontroller with an auto-
mated SPI interface is to be used, the SPI port can transfer
the 24 bits as three bytes. Subsequently, the data output
port pin can be reassigned to general purpose port opera-
tion and exercised to produce a number of transitions to
generate the load pulse. Alternatively, the entire sequence
can be programmed bit by bit with a general purpose port.
Figure 5 shows the timing.
The DC/DC converter, Figure 3 based on the LT
3439
ultralow noise transformer driver provides a compact
means of powering this circuit, and allows the output to
deliver output current that is only limited by the LT1468
capabilities. The output capability of the DC/DC converter
itself is 80mA at
12V and is available as demo board
DC511A. This circuit as shown requires approximately
130mA of the 5V supply (no load). The total surface area
required is less than 2 square inches.
14
LTC1588/LTC1589/LTC1592
1588992fa
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 3. Isolated Power Supplies for the Circuit of Figure 4
3
13
11
R1
1M
R9
10k
R2
16.9k
R3
15k
T1
CTX02-16030
D1
MMBD914
D2
MMBD914
D3
MMBD914
C3
22
F
25V
CER
2
4
1
4
5
3
2
5
1
3
D4
MMBD914
C22
2.2nF
1kV
E1
V
IN
5V
5%
E5
SHDN
E7
SYNC
E6
GND
C1
4.7
F
6.3V
C2
820pF
5
6
7
14
4
RSL
PGND
PGND
GND
COLB
RT
10
1
16
CT
SYNC
COLA
SHDN
V
IN
LT3439
C7
0.01
F
2.2
F
5V
C8
0.01
F
C4
22
F
25V
CER
R10
10k
R4
442k
R7
442k
R5
49.9k
12V
AGND
12V
1588992 F03
C5
33
F
25V
TANT
R6
49.9k
IN
OUT
BYP
LT1761
GND ADJ
IN
OUT
BYP
LT1964
GND ADJ
+
C6
33
F
25V
TANT
+
LT1121-5
V
IN
+
1/2 LT1469
+
+
1/2 LT1469
12-/14-/16-BIT DAC WITH SPAN ADJUST
LTC1588/LTC1589/LTC1592
R
COM
1
R1
2
V
CC
0.1
F
9
R2
R2
R1
16
R
OFS
3
7
5
V
REF
5V
6
REF
15
R
FB
I
OUT1
V
OUT
4
6
1
2
3
I
OUT2
2
3
*SCHOTTKY BARRIER DIODE
**FOR MULTIPLYING APPLICATIONS C3 = 15pF
ZETEX*
BAT54S
LT1001
5V
5
1
2
3
I
OUT2
AGND
GND
CLR
CS/LD
SCK
SDI
SDO
6
7
8
14
13
12
11
10
C3**
150pF
C2
15pF
1588992 F02
15V
15V
8
4
0.1
F
0.1
F
1000pF
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
6
1
2
3
6
+
LT1468
3
ZETEX
BAT54S
2
200
200
I
OUT2
Figure 2. Basic Connections for SoftSpan V
OUT
DAC with Two Optional Circuits
for Driving I
OUT2
from AGND with a Force/Sense Amplifier
15
LTC1588/LTC1589/LTC1592
1588992fa
U
PACKAGE DESCRIPTIO
G Package
16-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
G16 SSOP 0802
0.09 0.25
(.0035 .010)
0
8
0.55 0.95
(.022 .037)
5.00 5.60**
(.197 .221)
7.40 8.20
(.291 .323)
1
2 3
4
5
6 7 8
5.90 6.50*
(.232 .256)
14 13 12 11 10 9
15
16
2.0
(.079)
0.05
(.002)
0.65
(.0256)
BSC
0.22 0.38
(.009 .015)
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42
0.03
0.65 BSC
5.3 5.7
7.8 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25
0.12
16
LTC1588/LTC1589/LTC1592
1588992fa
LT/TP 0503 1K REV A PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2001
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear.com
PART NUMBER
DESCRIPTION
COMMENTS
LTC1591/LTC1597
Parallel 14-/16-Bit Current Output DACs
On-Chip 4-Quadrant Resistors
LTC1595/LTC1596
Serial 16-Bit Current Output DACs
Low Glitch,
1LSB Maximum INL, DNL
LTC1599
2-Byte, 16-Bit Current Output DAC
On-Chip 4-Quadrant Resistors
LTC1821
Parallel 16-Bit Voltage Outupt DAC
Precision 16-Bit Settling in 2
s for 10V Step
LTC2600/LTC2610
Octal 16-/14-/12-Bit DACs
Single Supply,
Power in Narrow SSOP16
LTC2620
RELATED PARTS
APPLICATIO S I FOR ATIO
W
U
U
U
+
LT1468
12V
12V
+
LT1468
12-/14-/16-BIT DAC WITH SPAN ADJUST
LTC1588/LTC1589/LTC1592
R
COM
1
R1
2
V
CC
0.1
F
9
R2
R2
R1
16
R
OFS
3
6
10
F
0.1
F
0.1
F
10
F
7
4
2
5V REF
4
2
8
12V
3
REF
15
R
FB
I
OUT1
V
OUT
4
5V
5
6
6
2
3
I
OUT2
AGND
GND
CLR
CS/LD
SCK
SDI
SDO
7
8
14
13
12
11
10
150pF
15pF
1588992 F04
12V
12V
7
4
0.1
F AGND
AGND
0.1
F
10
F
10
F
10
F
+
LT1027-5
A
B
C
D
CLK
ENP
ENT
LD
CLR
14
13
12
11
3
4
5
6
2
7
10
9
1
QA
QB
QC
QD
RCO
GND
5V
15
ISOLATED SDI
ISOLATED SCK
OPTIONAL CIRCUIT FOR 2-WIRE INTERFACE.
FOR A 3-WIRE INTERFACE (SPI), ADD A 3RD
OPTOISOLATOR TO DRIVE CS/LD WITH THE
WAVEFORMS OF FIGURE 1
ISOLATED
CS/LD
74HC161
5
6
2
V
CC
SCK
3
R1
7.5k
7
8
5V
HCPL2300
5
6
2
V
CC
SDI
TO
CONTROLLER
3
R2
7.5k
7
8
5V
HCPL2300
Figure 4. Optically Isolated 16-Bit SoftSpan System
C3
C2
C1
C0
X
D2
D1
D0
SCK
SDI
CS/LD
1588992 F05
Figure 5. Timing Diagram for the Circuit of Figure 4
PDF 
ZIP