1
LTC1594/LTC1598
The LTC
1594/LTC1598 are micropower, 12-bit sampling
A/D converters that feature 4- and 8-channel multiplexers,
respectively. They typically draw only 320
A of supply
current when converting and automatically power down to
a typical supply current of 1nA between conversions. The
LTC1594 is available in a 16-pin SO package and the
LTC1598 is packaged in a 24-pin SSOP. Both operate on
a 5V supply. The 12-bit, switched-capacitor, successive
approximation ADCs include a sample-and-hold.
On-chip serial ports allow efficient data transfer to a wide
range of microprocessors and microcontrollers over three
or four wires. This, coupled with micropower consump-
tion, makes remote location possible and facilitates trans-
mitting data through isolation barriers.
The circuit can be used in ratiometric applications or with
an external reference. The high impedance analog inputs
and the ability to operate with reduced spans (to 1.5V full
scale) allow direct connection to sensors and transducers
in many applications, eliminating the need for gain stages.
4- and 8-Channel,
Micropower Sampling
12-Bit Serial I/O A/D Converters
FEATURES
DESCRIPTIO
N
U
MICROWIRE is a trademark of National Semiconductor Corporation.
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
12-Bit Resolution
s
Auto Shutdown to 1nA
s
Low Supply Current: 320
A Typ
s
Guaranteed
3/4LSB Max DNL
s
Single Supply 5V Operation
(3V Versions Available: LTC1594L/LTC1598L)
s
Multiplexer: 4-Channel MUX (LTC1594)
8-Channel MUX (LTC1598)
s
Separate MUX Output and ADC Input Pins
s
MUX and ADC May Be Controlled Separately
s
Sampling Rate: 16.8ksps
s
I/O Compatible with QSPI, SPI and MICROWIRE
TM
, etc.
s
Small Package: 16-Pin Narrow SO (LTC1594)
24-Pin SSOP (LTC1598)
APPLICATIO
N
S
U
s
Pen Screen Digitizing
s
Battery-Operated Systems
s
Remote Data Acquisition
s
Isolated Data Acquisition
s
Battery Monitoring
s
Temperature Measurement
TYPICAL APPLICATIO
N
U
24
W, 4-Channel, 12-Bit ADC Samples at 200Hz and Runs Off a 5V Supply
ANALOG
INPUTS
0V TO 5V
RANGE
1k
1
F
1594/98 TA01
OPTIONAL
ADC FILTER
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
20
21
22
23
24
1
2
3
+
8-CHANNEL
MUX
8
COM
GND
4, 9
MPU
SERIAL DATA LINK
MICROWIRE AND
SPI COMPATABLE
10
6
5, 14
7
11
CSADC
CSMUX
CLK
D
IN
D
OUT
12
13
NC
NC
12-BIT
SAMPLING
ADC
ADCIN
MUXOUT
18
17
16
15, 19
1
F
5V
V
REF
V
CC
SAMPLE FREQUENCY (kHz)
0.1
1
SUPPLY CURRENT (
A)
10
100
1000
1
10
100
1594/98 TA02
T
A
= 25
C
V
CC
= 5V
V
REF
= 5V
f
CLK
= 320kHz
Supply Current vs Sample Rate
2
LTC1594/LTC1598
(Notes 1, 2)
Supply Voltage (V
CC
) to GND ................................... 12V
Voltage
Analog Reference .................... 0.3V to (V
CC
+ 0.3V)
Analog Inputs .......................... 0.3V to (V
CC
+ 0.3V)
Digital Inputs ......................................... 0.3V to 12V
Digital Output .......................... 0.3V to (V
CC
+ 0.3V)
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1594CS/LTC1598CG ......................... 0
C to 70
C
LTC1594IS/LTC1598IG ..................... 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec) .................. 300
C
PACKAGE/ORDER I
N
FOR
M
ATIO
N
W
U
U
Consult factory for Military grade parts.
LTC1594CS
LTC1594IS
ORDER PART
NUMBER
LTC1598CG
LTC1598IG
ORDER PART
NUMBER
T
JMAX
= 150
C,
JA
= 110
C/ W
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
G PACKAGE
24-LEAD PLASTIC SSOP
24
23
22
21
20
19
18
17
16
15
14
13
CH5
CH6
CH7
GND
CLK
CSMUX
D
IN
COM
GND
CSADC
D
OUT
NC
CH4
CH3
CH2
CH1
CH0
V
CC
MUXOUT
ADCIN
V
REF
V
CC
CLK
NC
T
JMAX
= 125
C,
JA
= 120
C/ W
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CH0
CH1
CH2
CH3
ADCIN
V
REF
COM
GND
V
CC
MUXOUT
D
IN
CSMUX
CLK
V
CC
D
OUT
CSADC
RECO
M
E
N
DED OPERATI
N
G CO
N
DITIO
N
S
U
U
U
U
W
W
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Voltage (Note 3)
4.5
5.5
V
f
CLK
Clock Frequency
V
CC
= 5V
(Note 4)
320
kHz
t
CYC
Total Cycle Time
f
CLK
= 320kHz
60
s
t
hDI
Hold Time, D
IN
After CLK
V
CC
= 5V
150
ns
t
suCS
Setup Time CS
Before First CLK
(See Operating Sequence)
V
CC
= 5V
1
s
t
suDI
Setup Time, D
IN
Stable Before CLK
V
CC
= 5V
400
ns
t
WHCLK
CLK High Time
V
CC
= 5V
1
s
t
WLCLK
CLK Low Time
V
CC
= 5V
1
s
t
WHCS
CS High Time Between Data Transfer Cycles
f
CLK
= 320kHz
16
s
t
WLCS
CS Low Time During Data Transfer
f
CLK
= 320kHz
44
s
(Note 5)
3
LTC1594/LTC1598
(Note 5)
CO
N
VERTER A
N
D
M
ULTIPLEXER CHARACTERISTICS
U
W
U
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
q
12
12
Bits
Integral Linearity Error
(Note 6)
q
3
3
LSB
Differential Linearity Error
q
3/4
1
LSB
Offset Error
q
3
3
LSB
Gain Error
q
8
8
LSB
REF Input Range
(Notes 7, 8)
1.5V to V
CC
+ 0.05V
V
Analog Input Range
(Notes 7, 8)
0.05V to V
CC
+ 0.05V
V
MUX Channel Input Leakage Current
Off Channel
q
200
200
nA
MUXOUT Leakage Current
Off Channel
q
200
200
nA
ADCIN Input Leakage Current
(Note 9)
q
1
1
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D)
Signal-to-Noise Plus Distortion Ratio
1kHz Input Signal
71
dB
THD
Total Harmonic Distortion (Up to 5th Harmonic)
1kHz Input Signal
78
dB
SFDR
Spurious-Free Dynamic Range
1kHz Input Signal
80
dB
Peak Harmonic or Spurious Noise
1kHz Input Signal
80
dB
DY
N
A
M
IC ACCURACY
U
W
DIGITAL A
N
D DC ELECTRICAL CHARACTERISTICS
U
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
CC
= 5.25V
q
2.6
V
V
IL
Low Level Input Voltage
V
CC
= 4.75V
q
0.8
V
I
IH
High Level Input Current
V
IN
= V
CC
q
2.5
A
I
IL
Low Level Input Current
V
IN
= 0V
q
2.5
A
V
OH
High Level Output Voltage
V
CC
= 4.75V, I
O
= 10
A
q
4.0
4.64
V
V
CC
= 4.75V, I
O
= 360
A
q
2.4
4.62
V
V
OL
Low Level Output Voltage
V
CC
= 4.75V, I
O
= 1.6mA
q
0.4
V
I
OZ
Hi-Z Output Leakage
CS = High
q
3
A
I
SOURCE
Output Source Current
V
OUT
= 0V
25
mA
I
SINK
Output Sink Current
V
OUT
= V
CC
45
mA
R
REF
Reference Input Resistance
CS = V
IH
5000
M
CS = V
IL
55
k
I
REF
Reference Current
CS = V
CC
q
0.001
2.5
A
t
CYC
760
s, f
CLK
25kHz
90
A
t
CYC
60
s, f
CLK
320kHz
q
90
140
A
I
CC
Supply Current
CS = V
CC
, CLK = V
CC
, D
IN
= V
CC
q
0.001
5
A
t
CYC
760
s, f
CLK
25kHz
320
A
t
CYC
60
s, f
CLK
320kHz
q
320
640
A
(Note 5) f
SMPL
= 16.8kHz
LTC1594CS/LTC1598CG
LTC1594IS/LTC1598IG
4
LTC1594/LTC1598
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
SMPL
Analog Input Sample Time
See Figure 1 in Applications Information
1.5
CLK Cycles
f
SMPL(MAX)
Maximum Sampling Frequency
See Figure 1 in Applications Information
q
16.8
kHz
t
CONV
Conversion Time
See Figure 1 in Applications Information
12
CLK Cycles
t
dDO
Delay Time, CLK
to D
OUT
Data Valid
See Test Circuits
q
250
600
ns
t
dis
Delay Time, CS
to D
OUT
Hi-Z
See Test Circuits
q
135
300
ns
t
en
Delay Time, CLK
to D
OUT
Enabled
See Test Circuits
q
75
200
ns
t
hDO
Time Output Data Remains Valid After CLK
C
LOAD
= 100pF
230
ns
t
f
D
OUT
Fall Time
See Test Circuits
q
50
150
ns
t
r
D
OUT
Rise Time
See Test Circuits
q
50
150
ns
t
ON
Enable Turn-On Time
See Figure 1 in Applications Information
q
260
700
ns
t
OFF
Enable Turn-Off Time
See Figure 2 in Applications Information
q
100
300
ns
t
OPEN
Break-Before-Make Interval
q
35
160
ns
C
IN
Input Capacitance
Analog Inputs On-Channel
20
pF
Off-Channel
5
pF
Digital Input
5
pF
(Note 5)
AC CHARACTERISTICS
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: These devices are specified at 5V. Consult factory for 3V
specified devices (LTC1594L/LTC1598L).
Note 4: Increased leakage currents at elevated temperatures cause the S/H
to droop, therefore it is recommended that f
CLK
160kHz at 85
C,
f
CLK
75kHz at 70
C and f
CLK
1kHz at 25
C.
Note 5: V
CC
= 5V, V
REF
= 5V and CLK = 320kHz unless otherwise specified.
CSADC and CSMUX pins are tied together during the test.
Note 6: Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above V
CC
. This spec allows 50mV forward
bias of either diode for 4.5V
V
CC
5.5V. This means that as long as the
reference or analog input does not exceed the supply voltage by more than
50mV, the output code will be correct. To achieve an absolute 0V to 5V
input voltage range, it will therefore require a minimum supply voltage of
4.950V over initial tolerance, temperature variations and loading.
Note 8: Recommended operating condition.
Note 9: Channel leakage current is measured after the channel selection.
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
SAMPLE FREQUENCY (kHz)
0.1
1
SUPPLY CURRENT (
A)
10
100
1000
1
10
100
1594/98 G01
T
A
= 25
C
V
CC
= 5V
V
REF
= 5V
f
CLK
= 320kHz
Supply Current vs Sample Rate
TEMPERATURE (
C)
55
92.0
REFERENCE CURRENT (
A)
92.5
93.5
94.0
94.5
15
25
45
125
1594/98 G03
93.0
35
5
65
85 105
95.0
V
CC
= V
REF
= 5V
f
SMPL
= 16.8kHz
f
CLK
= 320kHz
TEMPERATURE (
C)
55
200
SUPPLY CURRENT (
A)
250
350
400
450
15
25
45
125
1594/98 G02
300
35
5
65
85 105
T
A
= 25
C
V
CC
= V
REF
= 5V
f
CLK
= 320kHz
f
SMPL
= 16.8kHz
Supply Current vs Temperature
Reference Current vs Temperature
5
LTC1594/LTC1598
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
0
0 .05
0 .15
0 .20
0 .25
0 .30
0 .50
0 .35
0 .10
0 .40
0 .45
REFERENCE VOLTAGE (V)
1.0
CHANGE IN LINEARITY (LSB)
2.0
3.0
4.0
5.0
1594/98 G06
1.5
2.5
3.5
4.5
T
A
= 25
C
V
CC
= 5V
f
CLK
= 320kHz
f
SMPL
= 16.8kHz
Change in Linearity
vs Reference Voltage
TEMPERATURE (
C)
55
3.0
CHANGE IN OFFSET (LSB)
2.5
2.0
1.5
1.0
15
25
65
1594/98 G05
0.5
0
35
5
45
85
V
CC
= V
REF
= 5V
f
CLK
= 320kHz
f
SMPL
= 16.8kHz
Change in Offset vs Temperature
Change in Gain
vs Reference Voltage
REFERENCE VOLTAGE (V)
1.0
0
CHANGE IN OFFSET (LSB = 1/4096 V
REF
)
0.5
1.0
1.5
2.0
2.0
3.0
4.0
5.0
1594/98 G04
2.5
3.0
1.5
2.5
3.5
4.5
T
A
= 25
C
V
CC
= 5V
f
CLK
= 320kHz
f
SMPL
= 16.8kHz
Change in Offset
vs Reference Voltage
0
1
3
4
5
6
10
7
2
8
9
REFERENCE VOLTAGE (V)
1.0
CHANGE IN GAIN (LSB)
2.0
3.0
4.0
5.0
1594/98 G07
1.5
2.5
3.5
4.5
T
A
= 25
C
V
CC
= 5V
f
CLK
= 320kHz
f
SMPL
= 16.8kHz
Peak-to-Peak ADC Noise
vs Reference Voltage
REFERENCE VOLTAGE (V)
1
ADC NOISE IN LBSs
1.0
1.5
5
1594/98 G08
0.5
0
2
3
4
2.0
T
A
= 25
C
V
CC
= 5V
f
CLK
= 320kHz
Differential Nonlinearity vs Code
Effective Bits and S/(N + D)
vs Input Frequency
S/(N + D) vs Input Level
INPUT FREQUENCY (kHz)
1
0
EFFECTIVE NUMBER OF BITS (ENOBs)
8
7
10
9
12
11
10
100
1000
1594/98 G10
6
50
44
62
56
74
68
38
5
4
3
2
1
T
A
= 25
C
V
CC
= 5V
f
CLK
= 320kHz
f
SMPL
= 16.8kHz
INPUT LEVEL (dB)
40
0
SIGNAL-TO-NOISE PLUS DISTORTION (dB)
20
10
40
30
60
50
80
70
30
20
1594/98 G12
10
0
T
A
= 25
C
V
CC
= V
REF
=
5V
f
IN
= 1kHz
f
SMPL
= 16.8kHz
Spurious Free Dynamic Range
vs Frequency
INPUT FREQUENCY (kHz)
1
40
SPURIOUS FREE DYNAMIC RANGE (dB)
50
60
70
80
10
100
1000
1594/98 G11
30
20
10
0
90
100
T
A
= 25
C
V
CC
= V
REF
=
5V
f
SMPL
= 16.8kHz
CODE
0
DIFFERENTIAL NONLINEARITY ERROR (LBS)
1.0
0.8
0.6
0.4
0.2
0.4
0.6
0.8
1.0
0.2
0.0
2048
1594/98 G09
4096
6
LTC1594/LTC1598
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
Intermodulation Distortion
FREQUENCY (kHz)
0
60
40
0
3
5
1594/98 G15
80
100
1
2
4
6
7
120
140
20
MAGNITUDE (dB)
T
A
= 25
C
V
CC
= V
REF
=
5V
f
1
= 5kHz
f
2
= 6kHz
f
SMPL
= 12.5kHz
Attenuation vs Input Frequency
4096 Point FFT Plot
FREQUENCY (kHz)
0
60
40
0
3
5
1594/98 G14
80
100
1
2
4
6
7
120
140
20
MAGNITUDE (dB)
T
A
= 25
C
V
CC
= V
REF
= 5V
f
IN
= 5kHz
f
CLK
= 320kHz
f
SMPL
= 12.5kHz
Power Supply Feedthrough
vs Ripple Frequency
Maximum Clock Frequency
vs Source Resistance
INPUT FREQUENCY (kHz)
1
10
100
ATTENUATION (%)
80
90
60
70
40
50
20
30
100
1000
10000
1594/98 G13
0
10
T
A
= 25
C
V
CC
= V
REF
=
5V
f
SMPL
= 16.8kHz
RIPPLE FREQUENCY (kHz)
FEEDTHROUGH (dB)
50
0
1
100
1000
10000
1594/98 G16
100
10
T
A
= 25
C
V
CC
= 5V (V
RIPPLE
= 20mV)
V
REF
= 5V
f
CLK
= 320kHz
SOURCE RESISTANCE (k
)
0.1
0
CLOCK FREQUENCY (kHz)
60
120
180
240
360
1
10
1594/98 G17
300
+ INPUT
COM
R
SOURCE
V
IN
T
A
= 25
C
V
CC
= V
REF
= 5V
Sample-and-Hold Acquisition Time
vs Source Resistance
SOURCE RESISTANCE (
)
10
100
1000
1594/98 G18
1
0.1
10000
100
S & H ACQUISITION TIME (ns)
1000
10000
T
A
= 25
C
V
CC
= V
REF
= 5V
+ INPUT
COM
R
SOURCE
+
V
IN
Input Channel Leakage Current
vs Temperature
TEMPERATURE (
C)
60
LEAKAGE CURRENT (nA)
1000
100
10
1
0.1
0.01
100
1594/98 G20
20
20
60
140
40
0
40
80
120
V
CC
= 5V
V
REF
= 5V
ON CHANNEL
OFF CHANNEL
Minimum Clock Frequency for
0.1LSB Error vs Temperature
TEMPERATURE (
C)
55
CLOCK FREQUENCY (kHz)
160
240
25
45
65
85
1594/98 G19
80
0
35
15
5
320
V
CC
= V
REF
= 5V
7
LTC1594/LTC1598
PI
N
FU
N
CTIO
N
S
U
U
U
LTC1594
CH0 (Pin 1): Analog Multiplexer Input.
CH1 (Pin 2): Analog Multiplexer Input.
CH2 (Pin 3): Analog Multiplexer Input.
CH3 (Pin 4): Analog Multiplexer Input.
ADCIN (Pin 5): ADC Input. This input is the positive analog
input to the ADC. Connect this pin to MUXOUT for normal
operation.
V
REF
(Pin 6): Reference Input. The reference input defines
the span of the ADC.
COM (Pin 7): Negative Analog Input. This input is the
negative analog input to the ADC and must be free of noise
with respect to GND.
GND (Pin 8): Analog Ground. GND should be tied directly
to an analog ground plane.
CSADC (Pin 9): ADC Chip Select Input. A logic high on this
input powers down the ADC and three-states D
OUT
. A logic
low on this input enables the ADC to sample the selected
channel and start the conversion. For normal operation
drive this pin in parallel with CSMUX.
LTC1598
CH5 (Pin 1): Analog Multiplexer Input.
CH6 (Pin 2): Analog Multiplexer Input.
CH7 (Pin 3): Analog Multiplexer Input.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CLK (Pin 5): Shift Clock. This clock synchronizes the serial
data transfer to both MUX and ADC. It also determines the
conversion speed of the ADC.
CSMUX (Pin 6): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
D
IN
(Pin 7): Digital Data Input. The multiplexer address is
shifted into this input.
D
OUT
(Pin 10): Digital Data Output. The A/D conversion
result is shifted out of this output.
V
CC
(Pin 11): Power Supply Voltage. This pin provides
power to the ADC. It must be bypassed directly to the
analog ground plane.
CLK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer to both MUX and ADC.
CSMUX (Pin 13): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
D
IN
(Pin 14): Digital Data Input. The multiplexer address
is shifted into this input.
MUXOUT (Pin 15): MUX Output. This pin is the output of
the multiplexer. Tie to ADCIN for normal operation.
V
CC
(Pin 16): Power Supply Voltage. This pin should be
tied to Pin 11.
COM (Pin 8): Negative Analog Input. This input is the
negative analog input to the ADC and must be free of noise
with respect to GND.
GND (Pin 9): Analog Ground. GND should be tied directly
to an analog ground plane.
CSADC (Pin 10): ADC Chip Select Input. A logic high on
this input deselects and powers down the ADC and three-
states D
OUT
. A logic low on this input enables the ADC to
sample the selected channel and start the conversion. For
normal operation drive this pin in parallel with CSMUX.
D
OUT
(Pin 11): Digital Data Output. The A/D conversion
result is shifted out of this output.
NC (Pin 12): No Connection.
NC (Pin 13): No Connection.
CLK (Pin 14): Shift Clock. This input should be tied to Pin 5.
8
LTC1594/LTC1598
PI
N
FU
N
CTIO
N
S
U
U
U
V
CC
(Pin 15): Power Supply Voltage. This pin provides
power to the A/D Converter. It must be bypassed directly
to the analog ground plane.
V
REF
(Pin 16): Reference Input. The reference input de-
fines the span of the ADC.
ADCIN (Pin 17): ADC Input. This input is the positive
analog input to the ADC. Connect this pin to MUXOUT for
normal operation.
MUXOUT (Pin 18): MUX Output. This pin is the output of
the multiplexer. Tie to ADCIN for normal operation.
V
CC
(Pin 19): Power Supply Voltage. This pin should be
tied to Pin 15.
CH0 (Pin 20): Analog Multiplexer Input.
CH1 (Pin 21): Analog Multiplexer Input.
CH2 (Pin 22): Analog Multiplexer Input.
CH3 (Pin 23): Analog Multiplexer Input.
CH4 (Pin 24): Analog Multiplexer Input.
TEST CIRCUITS
Voltage Waveforms for D
OUT
Rise and Fall Times, t
r
, t
f
Load Circuit for t
dDO
, t
r
and t
f
D
OUT
1.4V
3k
100pF
TEST POINT
1594/98 TC01
D
OUT
V
OL
V
OH
t
r
t
f
1594/98 TC02
1594/98 BD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
20
21
22
23
24
1
2
3
+
8-CHANNEL
MUX
8
COM
GND
4, 9
10
6
5, 14
7
11
CSADC
CSMUX
CLK
D
IN
D
OUT
12
13
NC
NC
12-BIT
SAMPLING
ADC
ADCIN
MUXOUT
18
17
16
15, 19
V
REF
V
CC
CH0
CH1
CH2
CH3
1
2
3
4
+
4-CHANNEL
MUX
7
COM
GND
8
9
13
12
14
10
CSADC
CSMUX
CLK
D
IN
D
OUT
12-BIT
SAMPLING
ADC
ADCIN
MUXOUT
15
5
6
16
V
REF
V
CC
LTC1594
LTC1598
BLOCK DIAGRA S
W
LTC1594
LTC1598
9
LTC1594/LTC1598
TEST CIRCUITS
Voltage Waveforms for t
en
Voltage Waveforms for D
OUT
Delay Times, t
dDO
CLK
D
OUT
V
IL
t
dDO
V
OL
V
OH
1594/98 TC03
1594/98 TC06
CSADC
LTC1594/LTC1598
1
CLK
D
OUT
t
en
B11
V
OL
2
D
OUT
WAVEFORM 1
(SEE NOTE 1)
V
IH
t
dis
90%
10%
D
OUT
WAVEFORM 2
(SEE NOTE 2)
CSADC = CSMUX = CS
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
1594/98 TC05
Load Circuit for t
dis
and t
en
D
OUT
3k
100pF
TEST POINT
V
CC
t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
1594/98 TC04
Voltage Waveforms for t
dis
10
LTC1594/LTC1598
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
OVERVIEW
The LTC1594/LTC1598 are micropower, 12-bit sampling
A/D converters that feature a 4- and 8-channel multi-
plexer respectively. They typically draw only 320
A of
supply current when sampling at 16.8kHz. Supply cur-
rent drops linearly as the sample rate is reduced (see
Supply Current vs Sample Rate). The ADCs automatically
power down when not performing conversions, drawing
only leakage current. The LTC1594 is available in a 16-pin
narrow SO package and the LTC1598 is packaged in a
24-pin SSOP. Both devices operate on a single supply
from 4.5V to 5.5V.
The LTC1594/LTC1598 contain a 12-bit, switched-
capacitor ADC, sample-and-hold, serial port and an
external reference input pin. In addition, the LTC1594 has
a 4-channel multiplexer and the LTC1598 provides an
8-channel multiplexer (see Block Diagram). They can
measure signals floating on a DC common mode voltage
and can operate with reduced spans to 1.5V. Reducing
the spans allow them to achieve 366
V resolution.
The LTC1594/LTC1598 provide separate MUX output
and ADC input pins to form an ideal MUXOUT/ADCIN
loop which economizes signal conditioning. The MUX
and ADC of the devices can also be controlled individually
through separate chip selects to enhance flexibility.
SERIAL INTERFACE
For this discussion we will assume that CSMUX and
CSADC are tied together and will refer to them as simply
CS, unless otherwise specified.
The LTC1594/LTC1598 communicate with the micropro-
cessor and other external circuitry via a synchronous,
half duplex, 4-wire interface (see Operating Sequences in
Figures 1 and 2).
CLK
EN
D1
D2
CSMUX = CSADC = CS
t
CYC
B5
B6
B7
B8
B9
B10
B11
Hi-Z
D
OUT
CH0 TO
CH7
D
IN
t
CONV
Hi-Z
t
suCS
NULL
BIT
D0
B4
B3
B2
B1 B0*
t
SMPL
t
ON
DON'T CARE
ADCIN =
MUXOUT
COM = GND
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY
1594/98 F01
Figure 1. LTC1594/LTC1598 Operating Sequence Example: CH2, GND
11
LTC1594/LTC1598
APPLICATIO
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ATIO
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Figure 2. LTC1594/LTC1598 Operating Sequence Example: All Channels Off
CLK
EN
D1
D2
t
CYC
Hi-Z
D
OUT
CH0 TO
CH7
D
IN
t
CONV
Hi-Z
t
suCS
NULL
BIT
D0
t
OFF
D0N`T CARE
ADCIN =
MUXOUT
COM = GND
1594/98 F02
DUMMY CONVERSION
CSMUX = CSADC = CS
break-before-make interval, t
OPEN
. After a delay of t
ON
(t
OFF
+ t
OPEN
), the selected channel is switched on,
allowing the ADC in the chip to acquire input signal and
start the conversion (see Figures 1 and 2). After 1 null bit,
the result of the conversion is output on the D
OUT
line.
The selected channel remains on, until the next falling
edge of CS. At the end of the data exchange CS should be
brought high. This resets the LTC1594/LTC1598 and
initiates the next data exchange.
D
IN1
D
IN2
D
OUT1
D
OUT2
CS
SHIFT MUX
ADDRESS IN
t
SMPL
+ 1 NULL BIT
SHIFT A/D CONVERSION
RESULT OUT
1594/98 AI01
Break-Before-Make
The LTC1594/LTC1598 provide a break-before-make
interval from switching off all the channels simulta-
neously to switching on the next selected channel once
CS is pulled low. In other words, once CS is pulled low,
Data Transfer
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
The LTC1594/LTC1598 first receive input data and then
transmit back the A/D conversion results (half duplex).
Because of the half duplex operation, D
IN
and D
OUT
may
be tied together allowing transmission over just 3 wires:
CS, CLK and DATA (D
IN
/D
OUT
).
Data transfer is initiated by a rising chip select (CS)
signal. After CS rises the input data on the D
IN
pin is
latched into a 4-bit register on the rising edge of the clock.
More than four input bits can be sent to the D
IN
pin
without problems, but only the last four bits clocked in
before CS falls will be stored into the 4-bit register. This
4-bit input data word will select the channel in the
muliplexer (see Input Data Word and Tables 1 and 2). To
ensure correct operation the CS must be pulled low
before the next rising edge of the clock.
Once the CS is pulled low, all channels are simulta-
neously switched off after a delay of t
OFF
to ensure a
12
LTC1594/LTC1598
after a delay of t
OFF
, all the channels are switched off to
ensure a break-before-make interval. After this interval,
the selected channel is switched on allowing signal
transmission. The selected channel remains on until the
next falling edge of CS and the process repeats itself with
the "EN" bit being logic high. If the "EN" bit is logic low,
all the channels are switched off simultaneously after a
delay of t
OFF
from CS being pulled low and all the
channels remain off until the next falling edge of CS.
Input Data Word
When CS is high, the LTC1594/LTC1598 clock data into
the D
IN
inputs on the rising edge of the clock and store the
data into a 4-bit register. The input data words are defined
as follows:
D0
EN
D2
D1
CHANNEL SELECTION
1594/98 AI02
"EN" Bit
The first bit in the 4-bit register is an "EN" bit. If the "EN"
bit is a logic high, as illustrated in Figure 1, it enables the
selected channel after a delay of t
ON
when the CS is pulled
low. If the "EN" bit is logic low, as illustrated in Figure 2,
it disables all channels after a delay of t
OFF
when the CS
is pulled low.
Multiplexer (MUX) Address
The 3 bits of input word following the "EN" bit select the
channel in the MUX for the requested conversion. For a
given channel selection, the converter will measure the
voltage of the selected channel with respect to the voltage
on the COM pin. Tables 1 and 2 show the various bit
combinations for the LTC1594/LTC1598 channel selection.
Table 1. Logic Table for the LTC1594 Channel Selection
CHANNEL STATUS
EN
D2
D1
DO
All Off
0
X
X
X
CH0
1
0
0
0
CH1
1
0
0
1
CH2
1
0
1
0
CH3
1
0
1
1
APPLICATIO
N
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FOR
M
ATIO
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Table 2. Logic Table for the LTC1598 Channel Selection
CHANNEL STATUS
EN
D2
D1
DO
All Off
0
X
X
X
CH0
1
0
0
0
CH1
1
0
0
1
CH2
1
0
1
0
CH3
1
0
1
1
CH4
1
1
0
0
CH5
1
1
0
1
CH6
1
1
1
0
CH7
1
1
1
1
Transfer Curve
The LTC1594/LTC1598 are permanently configured for
unipolar only. The input span and code assignment for
this conversion type is illustrated below.
Transfer Curve
0V
1LSB
V
REF
2LSB
V
REF
4096
V
REF
1LSB
V
REF
V
IN
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
1594/98 AI03
1LSB =
Output Code
OUTPUT CODE
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
INPUT VOLTAGE
V
REF
1LSB
V
REF
2LSB
1LSB
0V
INPUT VOLTAGE
(V
REF
= 5.000V)
4.99878V
4.99756V
0.00122V
0V
1594/98 AI04
13
LTC1594/LTC1598
APPLICATIO
N
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FOR
M
ATIO
N
W
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U
U
Operation with D
IN
and D
OUT
Tied Together
The LTC1594/LTC1598 can be operated with D
IN
and
D
OUT
tied together. This eliminates one of the lines
required to communicate to the microprocessor (MPU).
Data is transmitted in both directions on a single wire.
The processor pin connected to this data line should be
configurable as either an input or an output. The LTC1594/
LTC1598 will take control of the data line after CS falling
and before the 6th falling CLK while the processor takes
control of the data line when CS is high (see Figure 3).
Therefore the processor port line must be switched to an
input with CS being low to avoid a conflict.
Separate Chip Selects for MUX and ADC
The LTC1594/LTC1598 provide separate chip selects,
CSMUX and CSADC, to control MUX and ADC separately.
This feature not only provides the flexibility to select a
particular channel once for multiple conversions (see
Figure 4) but also maximizes the sample rate up to
20ksps (see Figure 5).
Figure 4. Select Certain Channel Once for Mulitple Conversions
CLK
EN
D1
D2
CSADC
CSMUX
B5
B6
B7
B8
B9
B10
B11
Hi-Z
D
OUT
CH0 TO
CH7
D
IN
t
CONV
Hi-Z
t
suCS
NULL
BIT
D0
B4
B3
B2
B1
B0
t
SMPL
t
ON
B5
B6
B7
B8
B9
B10
B11
Hi-Z
t
CONV
t
suCS
NULL
BIT
D0
B4
B3
B2
B1
B0
t
SMPL
ADCIN =
MUXOUT
COM = GND
1594 TD01
DON'T CARE
DON'T CARE
1
2
3
4
5
6
CS
CLK
DATA (D
IN
/D
OUT
)
EN
D2
D1
D0
B11
B10
LTC1594/LTC1598 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1594/LTC1598
PROCESSOR MUST RELEASE DATA
LINE AFTER CS FALLING AND
BEFORE THE 6TH FALLING CLK
LTC1594/LTC1598 TAKES CONTROL OF DATA
LINE AFTER CS FALLING AND BEFORE THE
6TH FALLING CLK
1594/98 F03
t
suCS
Figure 3. LTC1594/LTC1598 Operation with D
IN
and D
OUT
Tied Together
14
LTC1594/LTC1598
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
CLK
EN
D1
D2
CSMUX
CSADC
B5
B6
B7
B8
B9
B10
B11
D
OUT
CH0 TO
CH7
D
IN
t
CONV
t
suCS
NULL
BIT
D0
B4
B3
B2
B1
B0
EN
D1
t
SMPL
t
ON
t
ON
B5
B6
B7
B8
B9
B10
B11
t
CONV
t
suCS
NULL
BIT
D0
D2
EN
D1
D0
D2
B4
B3
B2
B1
B0
t
SMPL
ADCIN =
MUXOUT
COM = GND
1594/98 F05
B4
B3
B2
B1
B0
DON'T CARE
DON'T CARE
MUXOUT/ADCIN Loop Economizes
Signal Conditioning
The MUXOUT and ADCIN pins of the LTC1594/LTC1598
form a very flexible external loop that allows Program-
mable Gain Amplifier (PGA) and/or processing analog
input signals prior to conversion. This loop is also a cost
effective way to perform the conditioning, because only
one circuit is needed instead of one for each channel.
In the Typical Applications section, there are a few
examples illustrating how to use the MUXOUT/ADCIN loop
to form a PGA and to antialias filter several analog inputs.
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 320
A and automatic
shutdown between conversions, the LTC1594/LTC1598
achieve extremely low power consumption over a wide
range of sample rates (see Figure 6). The auto shutdown
allows the supply current to drop with reduced sample
rate. Several things must be taken into account to achieve
such a low power consumption.
Shutdown
The LTC1594/LTC1598 are equipped with automatic shut-
down features. They draw power when the CS pin is low.
The bias circuits and comparator of the ADC powers down
and the reference input becomes high impedance at the
end of each conversion leaving the CLK running to clock
out the LSB first data or zeroes (see Figures 1 and 2). When
the CS pin is high, the ADC powers down completely
leaving the CLK running to clock the input data word into
MUX. If the CS, D
IN
and CLK are not running rail-to-rail, the
input logic buffers will draw currents. These currents may
be large compared to the typical supply current. To obtain
the lowest supply current, run the CS, D
IN
and CLK pins
rail-to-rail.
D
OUT
Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the D
OUT
pin
can add more than 80mA to the supply current at a
320kHz clock frequency. An extra 80mA or so of current
goes into charging and discharging the load capacitor.
The same goes for digital lines driven at a high frequency
by any logic. The (C)(V)(f) currents must be evaluated
and the troublesome ones minimized.
Figure 5. Use Separate Chip Selects to Maximize Sample Rate
SAMPLE FREQUENCY (kHz)
0.1
1
SUPPLY CURRENT (
A)
10
100
1000
1
10
100
1594/98 F06
T
A
= 25
C
V
CC
= 5V
V
REF
= 5V
f
CLK
= 320kHz
Figure 6. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
15
LTC1594/LTC1598
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
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BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1594/LTC1598 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The V
CC
pin should be bypassed to the ground plane with
a 10
F tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1594/LTC1598 can
also operate with smaller 1
F or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
SAMPLE-AND-HOLD
Both the LTC1594/LTC1598 provide a built-in sample-
and-hold (S&H) function to acquire signals through the
selected channel, assuming the ADCIN and MUXOUT
pins are tied together. The S & H of these parts acquire
input signals through the selected channel relative to
COM input during the t
SMPL
time (see Figure 7).
Single-Ended Inputs
The sample-and-hold of the LTC1594/LTC1598 allows
conversion of rapidly varying signals. The input voltage
is sampled during the t
SMPL
time as shown in Figure 7.
The sampling interval begins after t
ON
time once the CS
is pulled low and continues until the second falling CLK
edge after the CS is low (see Figure 7). On this falling CLK
Figure 7. LTC1594/LTC1598 ADCIN and COM Input Settling Windows
CLK
D
IN
D
OUT
MUXOUT = ADCIN
CH0 TO CH7
SAMPLE
HOLD
"ANALOG" INPUT MUST
SETTLE DURING
THIS TIME
t
SMPL
t
ON
t
CONV
CSADC = CSMUX = CS
D2
D1
EN
D0
DON`T CARE
1ST BIT TEST "COM" INPUT MUST
SETTLE DURING THIS TIME
B11
COM
1594/98 F07
16
LTC1594/LTC1598
APPLICATIO
N
S I
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FOR
M
ATIO
N
W
U
U
U
edge, the S & H goes into hold mode and the conversion
begins. The voltage on the "COM" input must remain
constant and be free of noise and ripple throughout the
conversion time. Otherwise, the conversion operation
may not be performed accurately. The conversion time is
12 CLK cycles. Therefore, a change in the "COM" input
voltage during this interval can cause conversion errors.
For a sinusoidal voltage on the "COM" input this error
would be:
V
ERROR(MAX)
= V
PEAK
(2
)(f)("COM")12/f
CLK
Where f("COM") is the frequency of the "COM" input
voltage, V
PEAK
is its peak amplitude and f
CLK
is the
frequency of the CLK. In most cases V
ERROR
will not be
significant. For a 60Hz signal on the "COM" input to
generate a 1/4LSB error (305
V) with the converter
running at CLK = 320kHz, its peak value would have to be
8.425mV.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1594/
LTC1598 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used
or if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
"Analog" Input Settling
The input capacitor of the LTC1594/LTC1598 is switched
onto the selected channel input during the t
SMPL
time (see
Figure 7) and samples the input signal within that time. The
sample phase is at least 1 1/2 CLK cycles before conver-
sion starts. The voltage on the "analog" input must settle
completely within t
SMPL
. Minimizing R
SOURCE
+
and C1 will
improve the input settling time. If a large "analog" input
source resistance must be used, the sample time can be
increased by using a slower CLK frequency.
"COM" Input Settling
At the end of the t
SMPL
, the input capacitor switches to the
"COM" input and conversion starts (see Figures 1 and 7).
During the conversion, the "analog" input voltage is
effectively "held" by the sample-and-hold and will not
affect the conversion result. However, it is critical that the
"COM" input voltage settles completely during the first
CLK cycle of the conversion time and be free of noise.
Minimizing R
SOURCE
and C2 will improve settling time.
If a large "COM" input source resistance must be used,
the time allowed for settling can be extended by using a
slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the "analog" and "COM" input
sampling times can be extended as described above to
accommodate slower op amps. Most op amps, including
the LT
1006 and LT1413 single supply op amps, can be
made to settle well even with the minimum settling
windows of 4.8
s ("analog" input) which occur at the
maximum clock rate of 320kHz.
Source Resistance
The analog inputs of the LTC1594/LTC1598 look like a
20pF capacitor (C
IN
) in series with a 500
resistor (R
ON
)
and a 45
channel resistance as shown in Figure 8.
C
IN
gets switched between the selected "analog" and
"COM" inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC
time constants be short enough to allow the analog
inputs to completely settle within the allowed time.
Figure 8. Analog Input Equivalent Circuit
R
ON
500
R
ON
45
C
IN
20pF
LTC1594
LTC1598
"ANALOG"
INPUT
R
SOURCE
+
V
IN
+
C1
"COM"
INPUT
MUXOUT
MUX
ADCIN
R
SOURCE
V
IN
C2
1594/98 F08
17
LTC1594/LTC1598
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
input leakage specification of 200nA (at 85
C) flowing
through a source resistance of 1.2k will cause a voltage
drop of 240
V or 0.2LSB. This error will be much
reduced at lower temperatures because leakage drops
rapidly (see typical curve Input Channel Leakage Current
vs Temperature).
REFERENCE INPUTS
The reference input of the LTC1594/LTC1598 is effec-
tively a 50k resistor from the time CS goes low to the end
of the conversion. The reference input becomes a high
impedance node at any other time (see Figure 9). Since
the voltage on the reference input defines the voltage
span of the A/D converter, the reference input should be
driven by a reference with low R
OUT
(ex. LT1004, LT1019
and LT1021) or a voltage source with low R
OUT
.
Reduced Reference Operation
The effective resolution of the LTC1594/LTC1598 can be
increased by reducing the input span of the converters.
The LTC1594/LTC1598 exhibit good linearity and gain
over a wide range of reference voltages (see typical
curves Change in Linearity vs Reference Voltage and
Change in Gain vs Reference Voltage). However, care
must be taken when operating at low values of V
REF
because of the reduced LSB step size and the resulting
higher accuracy requirement placed on the converters.
The following factors must be considered when operat-
ing at low V
REF
values:
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
Offset with Reduced V
REF
The offset of the LTC1594/LTC1598 has a larger effect on
the output code when the ADCs are operated with
reduced reference voltage. The offset (which is typically
a fixed voltage) becomes a larger fraction of an LSB as the
size of the LSB is reduced. The typical curve of Change in
Offset vs Reference Voltage shows how offset in LSBs is
related to reference voltage for a typical value of V
OS
. For
example, a V
OS
of 122
V which is 0.1LSB with a 5V
reference becomes 0.5LSB with a 1V reference and
2.5LSBs with a 0.2V reference. If this offset is unaccept-
able, it can be corrected digitally by the receiving system
or by offsetting the "COM" input of the LTC1594/LTC1598.
Noise with Reduced V
REF
The total input referred noise of the LTC1594/LTC1598
can be reduced to approximately 400
V peak-to-peak
using a ground plane, good bypassing, good layout
techniques and minimizing noise on the reference inputs.
This noise is insignificant with a 5V reference but will
become a larger fraction of an LSB as the size of the LSB
is reduced.
For operation with a 5V reference, the 400
V noise is only
0.33LSB peak-to-peak. In this case, the LTC1594/LTC1598
noise will contribute virtually no uncertainty to the output
code. However, for reduced references the noise may
become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with a
2.5V reference this same 400
V noise is 0.66LSB peak-
to-peak. This will reduce the range of input voltages over
which a stable output code can be achieved by 1LSB. If
the reference is further reduced to 1V, the 400
V noise
becomes equal to 1.65LSBs and a stable code may be
difficult to achieve. In this case averaging multiple read-
ings may be necessary.
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on V
CC
, V
REF
or V
IN
) will
add to the internal noise. The lower the reference voltage
to be used the more critical it becomes to have a clean,
noise free setup.
LTC1594
LTC1598
REF
+
R
OUT
V
REF
1
4
GND
1594/98 F09
Figure 9. Reference Input Equivalent Circuit
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
18
LTC1594/LTC1598
Conversion Speed with Reduced V
REF
With reduced reference voltages, the LSB step size is
reduced and the LTC1594/LTC1598 internal comparator
overdrive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values of
V
REF
are used.
DYNAMIC PERFORMANCE
The LTC1594/LTC1598 have exceptional sampling capa-
bility. Fast Fourier Transform (FFT) test techniques are
used to characterize the ADC's frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital
output using an FFT algorithm, the ADC's spectral con-
tent can be examined for frequencies outside the funda-
mental. Figure 10 shows a typical LTC1594/LTC1598
plot.
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to S/(N + D)
by the equation:
ENOB = [S/(N + D) 1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 16.8kHz with a 5V supply, the LTC1594/
LTC1598 maintain above 11 ENOBs at 10kHz input
frequency. Above 10kHz the ENOBs gradually decline, as
shown in Figure 11, due to increasing second harmonic
distortion. The noise floor remains low.
FREQUENCY (kHz)
0
60
40
0
3
5
1594/98 G14
80
100
1
2
4
6
7
120
140
20
MAGNITUDE (dB)
T
A
= 25
C
V
CC
= V
REF
= 5V
f
IN
= 5kHz
f
CLK
= 320kHz
f
SMPL
= 12.5kHz
Figure 10. LTC1594/LTC1598 Nonaveraged, 4096 Point FFT Plot
INPUT FREQUENCY (kHz)
1
0
EFFECTIVE NUMBER OF BITS (ENOBs)
8
7
10
9
12
11
10
100
1000
1594/98 G10
6
50
44
62
56
74
68
38
5
4
3
2
1
T
A
= 25
C
V
CC
= 5V
f
CLK
= 320kHz
f
SMPL
= 16.8kHz
Figure 11. Effective Bits and S/(N + D) vs Input Frequency
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamen-
tal itself. The out-of-band harmonics alias into the fre-
quency band between DC and half of the sampling
frequency. THD is defined as:
THD
=
+
+
+ +
20log
V
V
V
V
V
2
2
3
2
4
2
N
2
1
...
where V
1
is the RMS amplitude of the fundamental
frequency and V
2
through V
N
are the amplitudes of the
second through the N
th
harmonics. The typical THD
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio (S/N + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the ADC's output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 11 shows a typical spec-
tral content with a 16.8kHz sampling rate.
19
LTC1594/LTC1598
specification in the Dynamic Accuracy table includes the
2nd through 5th harmonics. With a 7kHz input signal, the
LTC1594/LTC1598 have typical THD of 80dB with V
CC
= 5V.
Intermodulation Distortion
If the ADC input signal consists of more than one
spectral component, the ADC transfer function nonlin-
earity can produce intermodulation distortion (IMD)
in addition to THD. IMD is the change in one sinusoi-
dal input caused by the presence of another sinusoidal
input at a different frequency.
If two pure sine waves of frequencies f
a
and f
b
are applied
to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at sum and
difference frequencies of mf
a
nf
b
, where m and n = 0,
1, 2, 3, etc. For example, the 2nd order IMD terms include
(f
a
+ f
b
) and (f
a
f
b
) while 3rd order IMD terms include
(2f
a
+ f
b
), (2f
a
f
b
), (f
a
+ 2f
b
), and (f
a
2f
b
). If the two input
sine waves are equal in magnitudes, the value (in dB) of
the 2nd order IMD products can be expressed by the
following formula:
IMD f
f
mplitude f
f
a
b
a
b
( )
=
( )
20log
a
amplitude at f
a
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
For input frequencies of 5kHz and 6kHz, the IMD of the
LTC1594/LTC1598 is 73dB with a 5V supply.
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest
spectral component excluding the input signal and DC.
This value is expressed in dBs relative to the RMS value
of a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full-scale input.
The full-linear bandwidth is the input frequency at which
the effective bits rating of the ADC falls to 11 bits. Beyond
this frequency, distortion of the sampled input signal
increases. The LTC1594/LTC1598 have been designed to
optimize input bandwidth, allowing the ADCs to
undersample input signals with frequencies above the
converters' Nyquist Frequency.
TYPICAL APPLICATIO
N
S
N
U
Microprocessor Interfaces
The LTC1594/LTC1598 can interface directly (without
external hardware) to most popular microprocessors'
(MPU) synchronous serial formats including
MICROWIRE, SPI and QSPI. If an MPU without a dedi-
cated serial port is used, then three of the MPU's parallel
port lines can be programmed to form the serial link to the
LTC1594/LTC1598. Included here is one serial interface
example.
Motorola SPI (MC68HC05)
The MC68HC05 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSB-
first and in 8-bit increments. The D
IN
word sent to the data
register starts the SPI process. With three
8-bit transfers the A/D result is read into the MPU. The
second 8-bit transfer clocks B11 through B7 of the A/D
conversion result into the processor. The third 8-bit trans-
fer clocks the remaining bits B6 through B0 into the MPU.
ANDing the second byte with 1F
HEX
clears the three most
significant bits and ANDing the third byte with FE
HEX
clears
the least significant bit. Shifting the data to the right by one
bit results in a right justified word.
20
LTC1594/LTC1598
TYPICAL APPLICATIO
N
S
N
U
LDA #$52
Configuration data for serial peripheral
control register (Interrupts disabled, output
enabled, master, Norm = 0, Ph = 0, Clk/16)
STA $0A
Load configuration data into location $0A (SPCR)
LDA #$FF
Configuration data for I/O ports
(all bits are set as outputs)
STA $04
Load configuration data into Port A DDR ($04)
STA $05
Load configuration data into Port B DDR ($05)
STA $06
Load configuration data into Port C DDR ($06)
LDA #$08
Put D
IN
word for LTC1598 into Accumulator
(CH0 with respect to GND)
STA $50
Load D
IN
word into memory location $50
START BSET 0,$02
Bit 0 Port C ($02) goes high (CS goes high)
LDA $50
Load D
IN
word at $50 into Accumulator
STA $0C
Load D
IN
word into SPI data register ($0C) and
start clocking data
LOOP1 TST $0B
Test status of SPIF bit in SPI status register ($0B)
MC68HC05 CODE
BPL LOOP1 Loop if not done with transfer to previous instruction
BCLR 0,$02
Bit 0 Port C ($02) goes low (CS goes low)
LDA $0C
Load contents of SPI data register into Accumulator
STA $0C
Start next SPI cycle
LOOP2 TST $0B
Test status of SPIF
BPL LOOP2 Loop if not done
LDA $0C
Load contents of SPI data register into Accumulator
STA $0C
Start next SPI cycle
AND #$IF
Clear 3 MSBs of first D
OUT
word
STA $00
Load Port A ($00) with MSBs
LOOP3 TST $0B
Test status of SPIF
BPL LOOP3 Loop if not done
LDA $0C
Load contents of SPI data register into Accumulator
AND #$FE
Clear LSB of second D
OUT
word
STA $01
Load Port B ($01) with LSBs
JMP START Go back to start and repeat program
1594/98 TA04
DOUT FROM LTC1598 STORED IN MC68HC05 RAM
B1
B0
0
B2
B3
B5
B6
B4
0
0
LSB
MSB
#00
#01
0
B11
B10
B9
B8
B7
CLK
D
IN
CSMUX
CSADC
ANALOG
INPUTS
C0
SCK
MC68HC05
D
OUT
MOSI
LTC1598
BYTE 1
BYTE 2
MISO
Hardware and Software Interface to Motorola MC68HC05
Data Exchange Between LTC1598 and MC68HC05
CSMUX
= CSADC
= CS
CLK
D
OUT
MPU
RECEIVED
WORD
1594/98 TA03
B3
B7
B6
B5
B4
B2
B1
B0
B1
B2
B11
B10
B9
B8
D
IN
MPU
TRANSMIT
WORD
BYTE 3
BYTE 2
EN
D2
0
D1
X
D0
BYTE 1
X
X
X
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
BYTE 3
BYTE 2
BYTE 1
B10
?
?
0
B11
B9
B7
B8
B6
B5
B3
B4
B2
B1
B1
B0
DON`T CARE
D1
D2
?
?
?
?
?
?
?
?
DO
EN
21
LTC1594/LTC1598
TYPICAL APPLICATIO
N
S
N
U
MULTICHANNEL A/D USES A SINGLE ANTIALIASING
FILTER
This circuit demonstrates how the LTC1598's indepen-
dent analog multiplexer can simplify design of a 12-bit
data acquisition system. All eight channels are MUXed into
a single 1kHz, 4th order Sallen-Key antialiasing filter,
which is designed for single supply operation. Since the
LTC1598's data converter accepts inputs from ground to
the positive supply, rail-to-rail op amps were chosen for
the filter to maximize dynamic range. The LT1368 dual rail-
to-rail op amp is designed to operate with 0.1
F load
capacitors (C1 and C2). These capacitors provide fre-
quency compensation for the amplifiers and help reduce
the amplifier's output impedance and improve supply
rejection at high frequencies. The filter contributes less
than 1LSB of error due to offsets and bias currents. The
filter's noise and distortion are less than 72dB for a
100Hz, 2V
P-P
offset sine input.
The combined MUX and A/D errors result in an integral
nonlinearity error of
3LSB (maximum) and a differential
nonlinearity error of
3/4LSB (maximum). The typical
signal-to-noise plus distortion ratio is 71dB, with approxi-
mately 78dB of total harmonic distortion. The LTC1598
is programmed through a 4-wire serial interface that is
compatable with MICROWIRE, SPI and QSPI. Maximum
serial clock speed is 320kHz, which corresponds to a
16.8kHz sampling rate.
The complete circuit consumes approximately 800
A
from a single 5V supply.
Simple Data Acquisition System Takes Advantage of the LTC1598's
MUXOUT/ADCIN Pins-to-Filter Analog Signals Prior to A/D Conversion
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CH5
CH6
CH7
GND
CLK
CSMUX
D
IN
COM
GND
CSADC
D
OUT
NC
CH4
CH3
CH2
CH1
CH0
V
CC
MUXOUT
ADCIN
V
REF
V
CC
CLK
NC
LTC1598
ANALOG INPUTS
0V TO 5V
RANGE
7.5k
7.5k
1
F
5V
1594/98 TA05
DATA IN
CHIP SELECT
CLOCK
DATA OUT
+
1
F
0.015
F
0.03
F
C2
0.1
F
7.5k
7.5k
0.03
F
0.015
F
+
C1
0.1
F
5V
1/2
LT1368
1/2
LT1368
22
LTC1594/LTC1598
TYPICAL APPLICATIO
N
S
N
U
Using MUXOUT/ADCIN Loop as PGA
This figure shows the LTC1598's MUXOUT/ADCIN loop
and an LT1368 being used to create a single channel PGA
with eight noninverting gains. Combined with the LTC1391,
the system can expand to eight channels and eight gains
for each channel. Using the LTC1594, the PGA is reduced
to four gains. The output of the LT1368 drives the ADCIN
and the resistor ladder. The resistors above the selected
MUX channel form the feedback for the LT1368. The loop
gain for this amplifier is R
S1
/R
S2
+ 1. R
S1
is the summation
of the resistors above the selected MUX channel and R
S2
Using the MUXOUT/ADCIN Loop of the LTC1598 to Form a PGA with Eight Gains in a Noninverting Configuration
1594/98 TA06
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
20
21
22
23
24
1
2
3
64R
32R
16R
8R
4R
2R
R
R
+
8
COM
18
MUXOUT
GND
4, 9
10
6
5, 14
11
7
CSADC
CSMUX
CLK
D
OUT
D
IN
12
13
NC
NC
12-BIT
SAMPLING
ADC
8-CHANNEL
MUX
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1391
5V
1
F
ADCIN
17
16
15, 19
1
F
0.1
F
5V
1
F
5V
V
REF
V
CC
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V+
D
V
D
OUT
D
IN
CS
CLK
GND
1/2 LT1368
LTC1598
P/
C
is the summation of the resistors below the selected MUX
channel. If CH0 is selected, the loop gain is 1 since R
S1
is
0. Table 1 shows the gain for each MUX channel. The
LT1368 dual rail-to-rail op amp is designed to operate with
0.1
F load capacitors. These capacitors provide frequency
compensation for the amplifiers, help reduce the amplifi-
ers' output impedance and improve supply rejection at
high frequencies. Because the LT1368's I
B
is low, the R
ON
of the selected channel will not affect the loop gain given
by the formula above.
23
LTC1594/LTC1598
G Package
24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N
U
0.016 0.050
0.406 1.270
0.010 0.020
(0.254 0.508)
45
0
8
TYP
0.008 0.010
(0.203 0.254)
1
2
3
4
5
6
7
8
0.150 0.157**
(3.810 3.988)
16
15
14
13
0.386 0.394*
(9.804 10.008)
0.228 0.244
(5.791 6.197)
12
11
10
9
S16 0695
0.053 0.069
(1.346 1.752)
0.014 0.019
(0.355 0.483)
0.004 0.010
(0.101 0.254)
0.050
(1.270)
TYP
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
G24 SSOP 0595
0.005 0.009
(0.13 0.22)
0
8
0.022 0.037
(0.55 0.95)
0.205 0.212**
(5.20 5.38)
0.301 0.311
(7.65 7.90)
1
2 3
4
5
6 7 8
9 10 11 12
0.318 0.328*
(8.07 8.33)
21
22
18 17 16 15 14 13
19
20
23
24
0.068 0.078
(1.73 1.99)
0.002 0.008
(0.05 0.21)
0.0256
(0.65)
BSC
0.010 0.015
(0.25 0.38)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24
LTC1594/LTC1598
LINEAR TECHNOLOGY CORPORATION 1996
15948f LT/GP 1296 7K PRINTED IN USA
TYPICAL APPLICATIO
N
U
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LTC1096L/LTC1098L
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140ksps, Complete with V
REF
, CLK, Sample-and-Hold
LTC1285/LTC1288
8-Pin SO, 3V, Micropower
1- or 2-Channel, Auto Shutdown
LTC1286/LTC1298
8-Pin SO, 5V, Micropower
1- or 2-Channel, Auto Shutdown
LTC1286
Multiplexed 12-Bit ADC
8-Channel 12-Bit Serial I/O
LTC1289
Multiplexed 3V, 1A, 12-Bit ADC
8-Channel 12-Bit Serial I/O
LTC1415
5V High Speed Parallel 12-Bit ADC
1.25Msps, Complete with V
REF
, CLK, Sample-and-Hold
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Low Power, Small Size, Low Cost
LTC1598L
8-Channel, 3V Micropower 12-Bit ADC
Low Power, Small Size, Low Cost
Using the LTC1598 and LTC1391 as an 8-Channel Differential 12-Bit ADC System
1594/98 TA07
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
20
21
22
23
24
1
2
3
+
8-CHANNEL
MUX
8
COM
GND
4, 9
10
6
5, 14
7
11
CSADC
CSMUX
CLK
D
IN
D
OUT
12
13
NC
NC
12-BIT
SAMPLING
ADC
ADCIN
MUXOUT
18
17
16
15, 19
1
F
1
F
5V
V
REF
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC1391
CH0
CH7
D
IN
CLK
CS
D
OUT
5V
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V+
D
V
D
OUT
D
IN
CS
CLK
GND
LTC1598
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
q
(408) 432-1900
FAX: (408) 434-0507
q
TELEX: 499-3977
q
www.linear-tech.com
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