1
LTC1599
V
CC
LTC1599
R
FB
R
FB
R
OFS
R
OFS
5V
LD
LD
4
3
2
6
3
3
6
2
12
11
24
10
20
8
19
R1
R
COM
2
R2
1
REF
5
6
0.1
F
7
I
OUT1
15pF
15pF
V
OUT
=
1599 TA01
I
OUT2F
9
I
OUT2S
DGND
+
LT1468
WR
14 TO 18,
21 TO 23
13
WR
MLBYTE
MLBYTE
CLR
CLVL
CLR
CLVL
V
REF
V
REF
+
LT1468
16-BIT DAC
R1
R2
8
DATA
INPUTS
V
REF
V
REF
s
True 16-Bit Performance over Industrial
Temperature Range
s
DNL and INL: 1LSB Max
s
On-Chip 4-Quadrant Resistors Allow Precise
0V to 10V, 0V to 10V or
10V Outputs
s
2
s Settling Time to 0.0015% (with LT
1468)
s
Asynchronous Clear Pin Resets to Zero Scale
or Midscale
s
Glitch Impulse: 1.5nV-s
s
24-Lead SSOP Package
s
Low Power Consumption: 10
W Typ
s
Power-On Reset to Zero Scale or Midscale
s
2-Byte Parallel Digital Interface
The LTC
1599 is a 2-byte parallel input 16-bit multiplying
current output DAC that operates from a single 5V supply.
INL and DNL are accurate to 1LSB over the industrial
temperature range in both 2- and 4-quadrant multiplying
modes. True 16-bit 4-quadrant multiplication is achieved
with on-chip 4-quadrant multiplication resistors.
The LTC1599 is available in 24-pin PDIP and SSOP packages
and is specified over the commercial and industrial tempera-
ture ranges. The device includes an internal deglitcher circuit
that reduces the glitch impulse to 1.5nV-s (typ). The asyn-
chronous CLR pin resets the LTC1599 to zero scale when the
CLVL pin is at a logic low and to midscale when the CLVL pin
is at a logic high.
For a full 16-bit wide parallel interface current output DAC,
refer to the LTC1597 data sheet. For serial interface 16-bit
current output DACs, refer to the LTC1595/LTC1596 data
sheet.
s
Process Control and Industrial Automation
s
Direct Digital Waveform Generation
s
Software-Controlled Gain Adjustment
s
Automatic Test Equipment
A 16-Bit, 4-Quadrant Multiplying DAC with a Minimum of External Components
Integral Nonlinearity
16-Bit Byte Wide,
Low Glitch Multiplying DAC with
4-Quadrant Resistors
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
DIGITAL INPUT CODE
0
1.0
INTEGRAL NONLINEARITY (LSB)
0.8
0.4
0.2
0
1.0
0.4
16384
32768
1599 G08
0.6
0.6
0.8
0.2
49152
65535
, LTC and LT are registered trademarks of Linear Technology Corporation.
2
LTC1599
ELECTRICAL CHARACTERISTICS
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
PACKAGE/ORDER I
N
FOR
M
ATIO
N
W
U
U
(Note 1)
V
CC
to DGND .............................................. 0.3V to 7V
REF, R
OFS
, R
FB
, R1, R2 to DGND ..........................
25V
R
COM
........................................................ 0.3V to 12V
Digital Inputs to DGND ............... 0.3V to (V
CC
+ 0.3V)
I
OUT1
, I
OUT2F
, I
OUT2S
to DGND .... 0.3V to( V
CC
+ 0.3V)
Maximum Junction Temperature .......................... 125
C
Operating Temperature Range
LTC1599C ............................................... 0
C to 70
C
LTC1599I ............................................ 40
C to 85
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
ORDER PART
NUMBER
T
JMAX
= 125
C,
JA
= 95
C/ W (G)
T
JMAX
= 125
C,
JA
= 58
C/ W (N)
Consult factory for Military grade parts.
LTC1599ACG
LTC1599BCG
LTC1599AIG
LTC1599BIG
LTC1599ACN
LTC1599BCN
LTC1599AIN
LTC1599BIN
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
CC
= 5V
10%, V
REF
= 10V, I
OUT1
= I
OUT2F
= I
OUT2S
= DGND = 0V,
T
A
= T
MIN
to T
MAX
unless otherwise noted.
LTC1599B
LTC1599A
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Accuracy
Resolution
q
16
16
Bits
Monotonicity
q
16
16
Bits
INL
Integral Nonlinearity
T
A
= 25
C (Note 2)
2
0.25
1
LSB
T
MIN
to T
MAX
q
2
0.35
1
LSB
DNL
Differential Nonlinearity
T
A
= 25
C
1
0.2
1
LSB
T
MIN
to T
MAX
q
1
0.2
1
LSB
GE
Gain Error
Unipolar Mode
T
A
= 25
C (Note 3)
16
2
16
LSB
T
MIN
to T
MAX
q
24
3
16
LSB
Bipolar Mode
T
A
= 25
C (Note 3)
16
2
16
LSB
T
MIN
to T
MAX
q
24
3
16
LSB
Gain Temperature Coefficient
Gain/
Temperature (Note 4)
q
1
3
1
3
ppm/
C
Bipolar Zero Error
T
A
= 25
C
10
5
LSB
T
MIN
to T
MAX
q
16
8
LSB
I
LKG
OUT1 Leakage Current
T
A
= 25
C (Note 5)
5
5
nA
T
MIN
to T
MAX
q
15
15
nA
PSRR
Power Supply Rejection
V
CC
= 5V
10%
q
1
2
1
2
LSB/V
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
REF
R2
R
COM
R1
R
OFS
R
FB
I
OUT1
I
OUT2F
I
OUT2S
CLVL
LD
WR
CLR
D0
D1
D2
V
CC
DGND
D3
D4
D5
D6
D7
MLBYTE
N PACKAGE
24-LEAD PDIP
G PACKAGE
24-LEAD PLASTIC SSOP
3
LTC1599
Note 9: V
REF
= 0V. DAC register contents changed from all 0s to all 1s or
all 1s to all 0s. LD high, WR and MLBYTE pulsed.
Note 10: V
REF
= 6V
RMS
at 1kHz. DAC register loaded with all 1s.
R
L
= 600
. Unipolar mode op amp = LT1468.
Note 11: Calculation from e
n
=
4kTRB where: k = Boltzmann constant
(J/
K), R = resistance (
), T = temperature (
K), B = bandwidth (Hz).
Note 12: Midscale transition code 0111 1111 1111 1111 to
1000 0000 0000 0000.
Note 13: R1 and R2 are measured between R1 and R
COM
, R2 and R
COM
.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
1LSB =
0.0015% of full scale =
15.3ppm of full scale.
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: I
(OUT1)
with DAC register loaded to all 0s.
Note 6: Typical temperature coefficient is 100ppm/
C.
Note 7: I
OUT1
load = 100
in parallel with 13pF.
Note 8: To 0.0015% for a full-scale change, measured from the falling
edge of LD.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input
R
REF
DAC Input Resistance (Unipolar)
(Note 6)
q
4.5
6
10
k
R1, R2
R1, R2 Resistance (Bipolar)
(Notes 6, 13)
q
9
14
20
k
R
OFS
, R
FB
Feedback and Offset Resistances
(Note 6)
q
9
13.5
20
k
AC Performance (Note 4)
Output Current Settling Time
(Notes 7, 8)
1
s
Midscale Glitch Impulse
(Note 12)
1.5
nV-s
Digital-to-Analog Glitch Impulse
(Note 9)
1
nV-s
Multiplying Feedthrough Error
V
REF
=
10V, 10kHz Sine Wave
1
mV
P-P
THD
Total Harmonic Distortion
(Note 10)
108
dB
Output Noise Voltage Density
(Note 11)
10
nV/
Hz
Analog Outputs (Note 4)
C
OUT
Output Capacitance (Note 4)
DAC Register Loaded to All 1s: C
OUT1
q
115
130
pF
DAC Register Loaded to All 0s: C
OUT1
q
70
80
pF
Digital Inputs
V
IH
Digital Input High Voltage
q
2.4
V
V
IL
Digital Input Low Voltage
q
0.8
V
I
IN
Digital Input Current
q
0.001
1
A
C
IN
Digital Input Capacitance
(Note 4) V
IN
= 0V
q
8
pF
Timing Characteristics
t
DS
Data to WR Setup Time
q
80
20
ns
t
DH
Data to WR Hold Time
q
0
12
ns
t
WR
WR Pulse Width
q
80
25
ns
t
BWS
MLBYTE to WR Setup Time
q
0
12
ns
t
BWH
MLBYTE to WR Hold Time
q
0
12
ns
t
LD
LD Pulse Width
q
150
55
ns
t
CLR
Clear Pulse Width
q
150
50
ns
t
LWD
WR to LD Delay Time
q
0
ns
Power Supply
V
CC
Supply Voltage
q
4.5
5
5.5
V
I
CC
Supply Current
Digital Inputs = 0V or V
CC
q
10
A
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
CC
= 5V
10%, V
REF
= 10V, I
OUT1
= I
OUT2F
= I
OUT2S
= DGND = 0V,
T
A
= T
MIN
to T
MAX
unless otherwise noted.
4
LTC1599
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Unipolar Multiplying Mode
Signal-to-(Noise + Distortion)
vs Frequency
Full-Scale Settling Waveform
Midscale Glitch Impulse
TIME (
s)
0
OUTPUT VOLTAGE (mV)
10
0
10
0.6
1.0
1599 G01
20
30
40
0.2
0.4
0.8
20
30
40
USING AN LT1468
C
FEEDBACK
= 30pF
V
REF
= 10V
1.5nV-s TYPICAL
FREQUENCY (Hz)
90
SIGNAL/(NOISE + DISTORTION) (dB)
70
50
40
10
1k
10k
100k
1599 G03
110
100
60
80
100
V
CC
= 5V USING AN LT1468
C
FEEDBACK
= 30pF
R
L
= 600
REFERENCE = 6V
RMS
500kHz FILTER
80kHz FILTER
30kHz FILTER
LD PULSE
5V/DIV
GATED
SETTLING
WAVEFORM
500
V/DIV
500ns/DIV
1599 G02
USING LT1468 OP AMP
C
FEEDBACK
= 20pF
0V to 10V STEP
Bipolar Multiplying Mode
Signal-to-(Noise + Distortion)
vs Frequency, Code = All Zeros
FREQUENCY (Hz)
90
SIGNAL/(NOISE + DISTORTION) (dB)
70
50
40
10
1k
10k
100k
1599 G04
110
100
60
80
100
V
CC
= 5V USING TWO LT1468s
C
FEEDBACK
= 15pF
R
L
= 600
REFERENCE = 6V
RMS
500kHz FILTER
80kHz FILTER
30kHz
FILTER
FREQUENCY (Hz)
90
SIGNAL/(NOISE + DISTORTION) (dB)
70
50
40
10
1k
10k
100k
1599 G05
110
100
60
80
100
V
CC
= 5V USING TWO LT1468s
C
FEEDBACK
= 15pF
R
L
= 600
REFERENCE = 6V
RMS
500kHz FILTER
80kHz FILTER
30kHz FILTER
INTPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
3
4
5
4
1599 G06
2
1
0
1
2
3
5
V
CC
= 5V
ALL DIGITAL INPUTS
TIED TOGETHER
Bipolar Multiplying Mode
Signal-to-(Noise + Distortion)
vs Frequency, Code = All Ones
Supply Current vs Input Voltage
Logic Threshold vs Supply Voltage
SUPPLY VOLTAGE (V)
0
0
LOGIC THRESHOLD (V)
0.5
1.0
1.5
2.0
3.0
1
2
3
4
1599 G07
5
7
6
2.5
Integral Nonlinearity (INL)
DIGITAL INPUT CODE
0
1.0
INTEGRAL NONLINEARITY (LSB)
0.8
0.4
0.2
0
1.0
0.4
16384
32768
1599 G08
0.6
0.6
0.8
0.2
49152
65535
Differential Nonlinearity (DNL)
DIGITAL INPUT CODE
0
1.0
DIFFERENTIAL NONLINEARITY (LSB) 0.8
0.4
0.2
0
1.0
0.4
16384
32768
1598 G09
0.6
0.6
0.8
0.2
49152
65535
5
LTC1599
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Integral Nonlinearity
vs Reference Voltage
in Unipolar Mode
REFERENCE VOLTAGE (V)
10
INTEGRAL NONLINEARITY (LSB)
0.2
0.6
1.0
6
1599 G10
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
6
2
2
8
8
4
0
4
10
REFERENCE VOLTAGE (V)
10
INTEGRAL NONLINEARITY (LSB)
0.2
0.6
1.0
6
1599 G11
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
6
2
2
8
8
4
0
4
10
REFERENCE VOLTAGE (V)
10
DIFFERENTIAL NONLINEARITY (LSB)
0.2
0.6
1.0
6
1599 G12
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
6
2
2
8
8
4
0
4
10
Integral Nonlinearity
vs Reference Voltage
in Bipolar Mode
Differential Nonlinearity
vs Reference Voltage
in Unipolar Mode
Differential Nonlinearity
vs Reference Voltage
in Bipolar Mode
REFERENCE VOLTAGE (V)
10
DIFFERENTIAL NONLINEARITY (LSB)
0.2
0.6
1.0
6
1599 G13
0.2
0.6
0
0.4
0.8
0.4
0.8
1.0
6
2
2
8
8
4
0
4
10
SUPPLY VOLTAGE (V)
1.0
INTEGRAL NONLINEARITY (LSB)
0.8
0.4
0.2
0
1.0
0.4
2
4
5
1599 G14
0.6
0.6
0.8
0.2
3
6
7
V
REF
= 10V
V
REF
= 10V
V
REF
= 2.5V
V
REF
= 2.5V
Integral Nonlinearity vs
Suppy Voltage in Unipolar Mode
Integral Nonlinearity vs
Suppy Voltage in Bipolar Mode
SUPPLY VOLTAGE (V)
INTEGRAL NONLINEARITY (LSB)
2.0
1.0
0.5
0
2.0
1.0
2
4
5
1599 G15
1.5
1.5
0.5
3
6
7
V
REF
= 10V
V
REF
= 10V
V
REF
= 2.5V
V
REF
= 2.5V
Differential Nonlinearity vs
Suppy Voltage in Unipolar Mode
SUPPLY VOLTAGE (V)
1.0
DIFFERENTIAL NONLINEARITY (LSB) 0.8
0.4
0.2
0
1.0
0.4
2
4
5
1599 G16
0.6
0.6
0.8
0.2
3
6
7
V
REF
= 10V
V
REF
= 2.5V
V
REF
= 10V
V
REF
= 2.5V
6
LTC1599
Differential Nonlinearity vs
Supply Voltage in Bipolar Mode
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
SUPPLY VOLTAGE (V)
1.0
DIFFERENTIAL NONLINEARITY (LSB) 0.8
0.4
0.2
0
1.0
0.4
2
4
5
1599 G17
0.6
0.6
0.8
0.2
3
6
7
V
REF
= 10V
V
REF
= 10V
V
REF
= 2.5V
V
REF
= 2.5V
FREQUENCY (Hz)
100
120
ATTENUATION (dB) 80
40
0
100
10k
100k
10M
1599 G18
1k
1M
20
60
D15 ON
D14 ON
D13 ON
D12 ON
ALL BITS ON
D9 ON
D1 ON
D0 ON
+
30pF
3 2 1 4
6
7
22
5
LT1468
LTC1599
V
OUT
V
REF
D11 ON
D10 ON
D8 ON
D7 ON
D6 ON
D5 ON
D4 ON
D3 ON
D2 ON
ALL BITS OFF
Unipolar Mulitplying Mode Frequency
Response vs Digital Code
Bipolar Mulitplying Mode Frequency
Response vs Digital Code
Bipolar Mulitplying Mode Frequency
Response vs Digital Code
FREQUENCY (Hz)
100
ATTENUATION (dB) 80
40
0
10
*DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR
ZERO ERROR TO 96dB TYPICAL (78dB MAX, A GRADE)
1k
10k
10M
1M
1599 G19
100
100k
20
60
D15 AND D14 ON
D15 AND D13 ON
D15 AND D12 ON
D15 AND D11 ON
D15 AND D10 ON
D15 AND D9 ON
D15 AND D8 ON
D15 AND D7 ON
D15 AND D6 ON
D15 AND D5 ON
D15 AND D4 ON
D15 AND D3 ON
D15 AND D2 ON
ALL BITS ON
15pF
12pF
+
+
12pF
V
REF
V
OUT
1
2
3
4
6
7
22
5
LT1468
LT1468
LTC1599
D15 ON
*
D15 AND D0 ON
D15 AND D1 ON
CODES FROM
MIDSCALE
TO FULL SCALE
FREQUENCY (Hz)
100
ATTENUATION (dB)
80
40
0
10
1k
10k
10M
1M
1599 G20
100
100k
20
60
D14 ON
D14 AND D13 ON
D14 TO D12 ON
D14 TO D11 ON
D14 TO D10 ON
D14 TO D9 ON
D14 TO D8 ON
D14 TO D7 ON
D14 TO D6 ON
D14 TO D5 ON
D14 TO D4 ON
D14 TO D3 ON
D14 TO D2 ON
D14 TO D1 ON
ALL BITS OFF
*DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR
ZERO ERROR TO 96dB TYPICAL (78dB MAX, A GRADE)
15pF
12pF
+
+
12pF
V
REF
V
OUT
1
2
3
4
6
7
22
5
LT1468
LT1468
LTC1599
D14 TO D0 ON
D15 ON
*
CODES FROM
MIDSCALE
TO ZERO SCALE
7
LTC1599
PI
N
FU
N
CTIO
N
S
U
U
U
CLVL (Pin 10): Clear Level. CLVL = 0, selects reset to zero
code. CLVL = 1, selects reset to midscale code. Normally
hardwired to a logic high or a logic low.
LD (Pin 11): DAC Digital Input Load Control Input. When
LD is taken to a logic low, data is loaded from the input
register into the DAC register, updating the DAC output.
WR (Pin 12): DAC Digital Write Control Input. When WR
is taken to a logic low, data is loaded from the 8 digital input
pins into the 16-bit wide input register. The MLBYTE pin
determines whether the MSB or LSB byte is loaded.
MLBYTE (Pin 13): MSB or LSB Byte Select. When MLBYTE
is taken to a logic low and WR is taken to a logic low, data
is loaded from the 8 digital input pins into the first 8 bits
of the 16-bit wide input register. When MLBYTE is taken to
a logic high and WR is taken to a logic low, data is loaded
from the 8 digital input pins into the 8 MSB bits of the input
register.
D7 to D3 (Pins 14 to 18): Digital Input Data Bits.
DGND (Pin 19): Digital Ground. Tie to ground.
V
CC
(Pin 20): The Positive Supply Input. 4.5V
V
CC
5.5V.
Requires a bypass capacitor to ground.
D2 to D0 (Pins 21 to 23): Digital Input Data Bits.
CLR (Pin 24): Digital Clear Control Function for the DAC.
When CLR and CLVL are taken to a logic low, the DAC
output and all internal registers are set to zero code. When
CLR is taken to a logic low and CLVL is taken to a logic high,
the DAC output and all internal registers are set to midscale
code.
REF (Pin 1): Reference Input. Typically
10V, accepts up
to
25V. In 2-quadrant mode, this pin is the reference
input. In 4-quadrant mode, this pin is driven by external
inverting reference amplifier.
R2 (Pin 2): 4-Quadrant Resistor R2. Typically
10V,
accepts up to
25V. In 2-quadrant operation, connect this
pin to ground. In 4-quadrant mode tie to the REF pin and
to the output of an external amplifier. See Figures 1 and 3.
R
COM
(Pin 3): Center Tap Point of the Two 4-Quadrant
Resistors R1 and R2. Normally tied to the inverting input
of an external amplifier in 4-quadrant operation, otherwise
connect this pin to ground. See Figures 1 and 3. The ab-
solute maximum voltage range on this pin is 0.3V to 12V.
R1 (Pin 4): 4-Quadrant Resistor R1. Typically
10V,
accepts up to
25V. In 2-quadrant operation connect this
pin to ground. In 4-quadrant mode tie to R
OFS
(Pin 5). See
Figures 1 and 3.
R
OFS
(Pin 5): Bipolar Offset Resistor. Typically swings
10V, accepts up to
25V. In 2-quadrant operation, tie to
R
FB
. In 4-quadrant operation tie to R1.
R
FB
(Pin 6): Feedback Resistor. Normally tied to the output
of the current to voltage converter op amp. Typically
swings
10V. Swings
V
REF
.
I
OUT1
(Pin 7): DAC Current Output. Tie to the inverting
input of the current to voltage converter op amp.
I
OUT2F
(Pin 8): Force Complement Current Output. Nor-
mally tied to ground.
I
OUT2S
(Pin 9): Sense Complement Current Output. Nor-
mally tied to ground.
TRUTH TABLE
Table 1
CONTROL INPUTS
CLR
WR
MLBYTE
LD
REGISTER OPERATION
0
X
X
X
Reset Input and DAC Registers to Zero Scale When CLVL = 0 and Midscale When CLVL = 1
1
0
1
Load the LSB Byte of the Input Register with All 8 Data Bits
1
1
1
Load the MSB Byte of the Input Register with All 8 Data Bits
1
1
X
Load the DAC Register with the Contents of the Input Register
1
1
X
1
No Register Operation
1
X
Flow-Through Mode. The DAC Register and the Selected Input Register Are Transparent. The Unselected Input
Register Retains Its Previous Data Byte. Note Only One Byte Is Transparent at a Time, the Selected Byte Being
Determined By the Logic Value of MLBYTE Prior to WR Being Pulsed Low.
8
LTC1599
BLOCK DIAGRA
W
TI I G DIAGRA
U
W
W
96k
12k
12k
96k
48k
96k
48k
96k
48k
48k
48k
DECODER
D15
(MSB)
D13
D14
D7
D12
D11
D0
(LSB)
LOAD
V
CC
REF
R
FB
I
OUT1
I
OUT2F
CLR
24
DGND
19
CLVL
10
I
OUT2S
9
1599 BD
DAC REGISTER
48k
48k
48k
R
48k
12k
11
20
R1 4
R
COM
3
1
LD
12
14
D6
15
D3
18
D2
21
D0
23
D1
22
WR
MLBYTE
8
7
6
R
OFS
5
12k
R2 2
EN
EN
MSB ENABLE
LSB ENABLE
RST
RST
INPUT REGISTER
MSB BYTE
INPUT REGISTER
LSB BYTE
13
POWER-ON
RESET
LOGIC
BYTE
ENABLE
LOGIC
D0 TO D7
1599 TD
t
DS
t
DH
t
BWH
t
BWS
t
BWH
t
BWS
t
WR
t
WR
WR
MLBYTE
t
LD
t
LWD
t
CLR
LD
CLR
t
DS
t
DH
9
LTC1599
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Description
The LTC1599 is a 16-bit multiplying, current output DAC
with a 2-byte (8-bit wide) digital interface. The device
operates from a single 5V supply and provides both
unipolar 0V to 10V or 0V to 10V and bipolar
10V output
ranges from a 10V or 10V reference input. It has three
additional precision resistors on chip for bipolar opera-
tion. Refer to the Block Diagram regarding the following
description.
The 16-bit DAC consists of a precision R-2R ladder for the
13LSBs. The 3MSBs are decoded into seven segments of
resistor value R (48k typ). Each of these segments and the
R-2R ladder carries an equally weighted current of one
eighth of full scale. The feedback resistor R
FB
and
4-quadrant resistor R
OFS
have a value of R/4. 4-quadrant
resistors R1 and R2 have a magnitude of R/4. R1 and R2
together with an external op amp (see Figure 4) inverts the
reference input voltage and applies it to the 16-bit DAC
input REF, in 4-quadrant operation. The REF pin presents
a constant input impedance of R/8 in unipolar mode and
R/12 in bipolar mode. The output impedance of the current
output pin I
OUT1
varies with DAC input code. The I
OUT1
capacitance due to the NMOS current steering switches
also varies with input code from 70pF to 115pF. I
OUT2F
and
I
OUT2S
are normally tied to the system analog ground. An
added feature of the LTC1599 is a proprietary deglitcher
that reduces glitch impulse to 1.5nV-s over the DAC output
voltage range.
Digital Section
The LTC1599 has a byte wide (8-bit), digital input data bus.
The device is double-buffered with two 16-bit registers.
The double-buffered feature permits the update of several
DACs simultaneously. The input register is loaded directly
from an 8-bit (or higher) microprocessor bus in a two step
sequence. The MLBYTE pin selects whether the 8 input
data bits are loaded into the LSB or the MSB byte of the
input register. When MLBYTE is brought to a logic low
level and WR is given a logic low going pulse, the 8 data
bits are loaded into the LSB byte of the input register.
Conversely, when MLBYTE is brought to a logic high level
and WR is given a logic low going pulse, the 8 data bits are
loaded into the MSB byte of the input register. If WR is
brought to a logic low level, the existing level of MLBYTE
determines which byte is loaded into the input register. If
the logic level of MLBYTE is changed while WR remains
low, no change will occur. This is because WR is an edge
triggered signal and once it goes low it locks out any
further changes in MLBYTE. WR must be brought high and
then low again to accept the new MLBYTE condition. The
second register (DAC register) is updated with the data
from the input register when the LD pin is brought to a
logic low level. Updating the DAC register updates the DAC
output with the new data. The deglitcher is activated on the
falling edge of the LD pin. The asynchronous clear pin
resets the LTC1599 to zero scale when the CLVL pin is at
a logic low level and to midscale when the CLVL pin is at
a logic high level. CLR resets both the input and DAC
registers. The device also has a power-on reset. Table 1
shows the truth table for the device.
Unipolar Mode
(2-Quadrant Multiplying, V
OUT
= 0V to V
REF
)
The LTC1599 can be used with a single op amp to provide
2-quadrant multiplying operation as shown in Figure 1.
With a fixed 10V reference, the circuit shown gives a
precision unipolar 0V to 10V output swing.
Bipolar Mode
(4-Quadrant Multiplying, V
OUT
= V
REF
to V
REF
)
The LTC1599 contains on chip all the 4-quadrant resistors
necessary for bipolar operation. 4-quadrant multiplying
operation can be achieved with a minimum of external
components, a capacitor and a dual op amp, as shown in
Figure 3. With a fixed 10V reference, the circuit shown
gives a precision bipolar 10V to 10V output swing.
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC1599, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 2 and 3 contain equations for evaluating the effects
of op amp parameters on the LTC1599's accuracy when
10
LTC1599
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
configured in unipolar or bipolar modes of operation
(Figures 1 and 3). These are the changes the op amp can
cause to the INL, DNL, unipolar offset, unipolar gain error,
bipolar zero and bipolar gain error. Table 4 contains a
partial list of LTC precision op amps recommended for use
with the LTC1599. The two sets of easy-to-use design
equations simplify the selection of op amps to meet the
system's specified error budget. Select the amplifier from
Table 4 and insert the specified op amp parameters in
either Table 2 or Table 3. Add up all the errors for each
category to determine the effect the op amp has on the
accuracy of the LTC1599. Arithmetic summation gives an
(unlikely) worst-case effect. RMS summation produces a
more realistic effect.
Op amp offset will contribute mostly to output offset and
gain error and has minimal effect on INL and DNL. For the
LTC1599, a 500
V op amp offset will cause about 0.55LSB
INL degradation and 0.15LSB DNL degradation with a 10V
full-scale range (20V range in bipolar). For the LTC1599
configured in the unipolar mode, the same 500
V op amp
offset will cause a 3.3LSB zero-scale error and a 3.45LSB
gain error with a 10V full-scale range.
While not directly addressed by the simple equations in
Tables 2 and 3, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp's data sheet to find the worst-case V
OS
and I
B
over temperature. Then, plug these numbers in the V
OS
and I
B
equations from Table 2 or Table 3 and calculate the
temperature induced effects.
For applications where fast settling time is important,
Application Note 74, entitled "
Component and Measure-
ment Advances Ensure 16-Bit DAC Settling Time," offers
a thorough discussion of 16-bit DAC settling time and op
amp selection.
Table 4. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC1599, with Relevant Specifications
Amplifier Specifications
VOLTAGE
CURRENT
SLEW
GAIN BANDWIDTH
t
SETTLING
POWER
V
OS
I
B
A
OL
NOISE
NOISE
RATE
PRODUCT
with LTC1599
DISSIPATION
AMPLIFIER
V
nA
V/mV
nV/
Hz
pA/
Hz
V/
s
MHz
s
mW
LT1001
25
2
800
10
0.12
0.25
0.8
120
46
LT1097
50
0.35
1000
14
0.008
0.2
0.7
120
11
LT1112 (Dual)
60
0.25
1500
14
0.008
0.16
0.75
115
10.5/Op Amp
LT1124 (Dual)
70
20
4000
2.7
0.3
4.5
12.5
19
69/Op Amp
LT1468
75
10
5000
5
0.6
22
90
2.5
117
Table 2. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in Unipolar Applications
OP AMP
INL (LSB)
DNL (LSB)
UNIPOLAR OFFSET (LSB)
UNIPOLAR GAIN ERROR (LSB)
V
OS
(mV)
V
OS
1.2 (10V/V
REF
)
V
OS
0.3 (10V/V
REF
)
V
OS
6.6 (10V/V
REF
)
V
OS
6.9 (10V/V
REF
)
I
B
(nA)
I
B
0.00055 (10V/V
REF
)
I
B
0.00015 (10V/V
REF
)
I
B
0.065 (10V/V
REF
)
0
A
VOL
(V/V)
10k/A
VOL
3k/A
VOL
0
131k/A
VOL
Table 3. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in Bipolar Applications
OP AMP
INL (LSB)
DNL (LSB)
BIPOLAR ZERO ERROR (LSB)
BIPOLAR GAIN ERROR (LSB)
V
OS1
(mV)
V
OS1
1.2 (10V/V
REF
)
V
OS1
0.3 (10V/V
REF
)
V
OS1
9.9 (10V/V
REF
)
V
OS1
6.9 (10V/V
REF
)
I
B1
(nA)
I
B1
0.00055 (10V/V
REF
)
I
B1
0.00015 (10V/V
REF
)
I
B1
0.065 (10V/V
REF
)
0
A
VOL1
10k/A
VOL
3k/A
VOL1
0
196k/A
VOL1
V
OS2
(mV)
0
0
V
OS2
6.7 (10V/V
REF
)
V
OS2
13.2 (10V/V
REF
)
I
B2
(nA)
0
0
I
B2
0.065 (10V/V
REF
)
I
B2
0.13 (10V/V
REF
)
A
VOL2
0
0
65k/A
VOL2
131k/A
VOL2
11
LTC1599
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
V
CC
LTC1599
R
FB
R
FB
R
OFS
R
OFS
5V
4
3
20
8
19
R1
R
COM
2
R2
1
REF
5
6
0.1
F
7
I
OUT1
33pF
V
OUT
0V TO V
REF
1599 F01
DGND
V
REF
+
LT1001
16-BIT DAC
R1
R2
Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
V
REF
(65,535/65,536)
V
REF
(32,768/65,536) = V
REF
/ 2
V
REF
(1/65,536)
0V
LSB
1111 1111 1111
0000 0000 0000
0000 0000 0001
0000 0000 0000
ANALOG OUTPUT
V
OUT
MSB
1111
1000
0000
0000
I
OUT2F
9
I
OUT2S
13
MLBYTE
MLBYTE
14 TO 18,
21 TO 23
8
DATA
INPUTS
LD
LD
12
11
24
10
WR
WR
CLR
CLVL
CLR
CLVL
3
6
2
1599 F02
V
CC
LTC1599
R
FB
R
FB
R
OFS
R
OFS
5V
4
3
20
8
19
R1
R
COM
2
R2
1
REF
5
6
0.1
F
7
I
OUT1
33pF
V
OUT
0V TO V
REF
I
OUT2F
9
I
OUT2S
DGND
+
1/2 LT1112
14 TO 18,
21 TO 23
13
MLBYTE
MLBYTE
V
REF
+
1/2 LT1112
16-BIT DAC
R1
R2
8
DATA
INPUTS
LD
LD
12
11
24
10
WR
WR
CLR
CLVL
CLR
CLVL
Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
V
REF
(65,535/65,536)
V
REF
(32,768/65,536) = V
REF
/ 2
V
REF
(1/65,536)
0V
LSB
1111 1111 1111
0000 0000 0000
0000 0000 0001
0000 0000 0000
ANALOG OUTPUT
V
OUT
MSB
1111
1000
0000
0000
3
1
2
6
7
5
Figure 2. Noninverting Unipolar Operation (2-Quadrant Multiplication) V
OUT
= 0V to V
REF
Figure 1. Unipolar Operation (2-Quadrant Multiplication) V
OUT
= 0V to V
REF
12
LTC1599
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC1599 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. As shown in the section describing
the basic operation of the LTC1599, the output voltage of
the DAC circuit is directly affected by the voltage reference;
thus, any voltage reference error will appear as a DAC
output voltage error.
There are three primary error sources to consider when
selecting a precision voltage reference for 16-bit applica-
tions: output voltage initial tolerance, output voltage tem-
perature coefficient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
(
0.05%), minimizes the gain error caused by the refer-
ence; however, a calibration sequence that corrects for
system zero- and full-scale error is always recommended.
1599 F03
Bipolar Offset Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
V
REF
(32,767/32,768)
V
REF
(1/32,768)
0V
V
REF
(1/32,768)
V
REF
LSB
1111 1111 1111
0000 0000 0001
0000 0000 0000
1111 1111 1111
0000 0000 0000
ANALOG OUTPUT
V
OUT
MSB
1111
1000
1000
0111
0000
V
CC
LTC1599
R
FB
R
FB
R
OFS
R
OFS
5V
4
3
20
8
19
R1
R
COM
2
R2
1
REF
5
6
0.1
F
7
I
OUT1
15pF
V
OUT
V
REF
TO V
REF
I
OUT2F
9
I
OUT2S
DGND
+
1/2 LT1112
14 TO 18,
21 TO 23
13
MLBYTE
MLBYTE
V
REF
+
1/2 LT1112
16-BIT DAC
R1
R2
8
DATA
INPUTS
LD
LD
12
11
24
10
WR
WR
CLR
CLVL
CLR
CLVL
3
1
2
6
7
5
Figure 3. Bipolar Operation (4-Quadrant Multiplication) V
OUT
= V
REF
to V
REF
A reference's output voltage temperature coefficient af-
fects not only the full-scale error, but can also affect the
circuit's INL and DNL performance. If a reference is
chosen with a loose output voltage temperature coeffi-
cient, then the DAC output voltage along its transfer
characteristic will be very dependent on ambient condi-
tions. Minimizing the error due to reference temperature
coefficient can be achieved by choosing a precision refer-
ence with a low output voltage temperature coefficient
and/or tightly controlling the ambient temperature of the
circuit to minimize temperature gradients.
As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contrib-
ute a dominant share of the system's noise floor. This in
turn can degrade system dynamic range and signal-to-
noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practical
for the system resolution desired. Precision voltage refer-
ences, like the LT1236, produce low output noise in the
0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V
13
LTC1599
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
or 10V full-scale systems. However, as the circuit band-
widths increase, filtering the output of the reference may
be required to minimize output noise.
Table 5. Partial List of LTC Precision References Recommended
for Use with the LTC1599, with Relevant Specifications
INITIAL
TEMPERATURE
0.1Hz to 10Hz
REFERENCE
TOLERANCE
DRIFT
NOISE
LT1019A-5,
0.05%
5ppm
12
V
P-P
LT1019A-10
LT1236A-5,
0.05%
5ppm
3
V
P-P
LT1236A-10
LT1460A-5,
0.075%
10ppm
20
V
P-P
LT1460A-10
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding should be used. I
OUT2F
and I
OUT2S
must be tied
to the star ground with as low a resistance as possible.
When it is not possible to locate star ground close to
I
OUT2F
and I
OUT2S
, separate traces should be used to route
these pins to star ground. This minimizes the voltage drop
from these pins to ground caused by the code dependent
current flowing to ground. When the resistance of these
circuit board traces becomes greater than 1
, the circuit
in Figure 4 eliminates voltage drop errors caused by high
resistance traces. This preserves the excellent accuracy
(1LSB INL and DNL) of the LTC1599.
A 16-Bit, 4mA to 20mA Current Loop Controller
for Industrial Applications
Modern process control systems must often deal with
legacy 4mA to 20mA analog current loops as a means of
interfacing with actuators and valves located at a distance.
The circuit in Figure 5 provides an output to a current loop
controlled by an LTC1599, a 16-bit current output DAC. A
dual rail-to-rail op amp (U1, LT1366) controls a P-channel
power FET (Q2) to produce a current mirror with a precise
8:1 ratio as defined by a resistor array. The input current
to this mirror circuit is produced by a grounded base
cascode stage using a high gain transistor (Q1). The use
of a bipolar transistor in this location results in an error
term associated with U1B and Q1's base current ( 0.2%
for the device shown). For control applications however,
absolute accuracy of the output to an actuator is usually
not required. If a higher degree of absolute accuracy is
required, Q1 can be replaced with an N-channel JFET;
however, this requires a single amplifier at U1B with the
ability to drive the gate below ground. An enhancement
mode N-channel FET can be used in place of Q1 but
MOSFET leakage current must be considered and gate
overdrive must be avoided.
Figure 4. Driving I
OUT2F
and I
OUT2S
with a Force/Sense Amplifier
V
CC
LTC1599
R
FB
R
FB
R
OFS
R
OFS
5V
4
3
20
8
R1
R
COM
2
R2
1
REF
5
6
0.1
F
7
I
OUT1
33pF
V
OUT
0V TO 10V
1599 F04
+
LT1001
+
LT1001
16-BIT DAC
R1
R2
I
OUT2F
I
OUT2S
13
MLBYTE
MLBYTE
14 TO 18,
21 TO 23
8
DATA
INPUTS
LD
LD
12
11
24
10
WR
WR
CLR
CLVL
CLR
19
9
DGND
CLVL
3
6
2
2
6
3
LT1236A-10
2
6 10V
15V
4
14
LTC1599
The output current of the DAC is converted to a voltage via
U3 (LT1112), producing 0V to 2.5V at Pin 1 of U3. The
resulting current in Q1 is determined by two elements of
resistor array, R
N1
(3mA max). The emitter of Q1 is
maintained at 0V by the action of U1B.
In applications that do not require 16-bit resolution and
accuracy, the LTC1599 can be replaced by the 14-bit
parallel LTC1591. Furthermore, the resistor array can be
substituted with discrete resistors, and Q2 could be re-
placed by a high gain bipolar PNP; for example, an FZT600
from Zetex.
No trim is provided a shown, as it is expected that software
control is preferable. The output range of 4mA to 20mA is
defined by software, as the full output range is nominally
0mA to 24mA.
U1 is a rail-to-rail amplifier that can operate on suppy
voltages up to 36V. This defines the maximum voltage on
the loop power. If higher loop voltages are required, a
separate low power amplifier at U1A, powered by a zener
regulated supply and referenced to loop power, would
allow voltages up to the breakdown voltages of Q1 and Q2.
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
In the example shown, the use of a dual op amp requires
a zener clamp to protect the gate of the MOS power
transistor. If a separate shunt-regulated supply is pro-
vided for the amplifier replacing U1A, the gate clamp (Z1)
is not required.
As shown, this topology uses the LTC1599's internal
divider (R1 and R2) to reduce the reference from 5V to
2.5V. If a 2.5V reference is used, it can be connected
directly to REF (Pin 1). Alternatively, if the op amp is
powered such that it has 10V output capability, the
divider and amplifier prior to the REF input are not required
and R
OFS
can be used for other purposes such as offset
trim. The two R
N1
resistors at the emitter of Q1 must be
changed in this case.
Note that the output of the current transmitter shows a
network that is intended to provide a first line of defense
against ESD and prevent oscillation (1000pF and 10
)
that could otherwise occur in the power MOSFET if lead
inductance were more than a few inches. C1 should be as
close as possible to Q2. Using MOSFETs that have higher
threshold voltages may require changing Z1 in order to
allow full current output.
V
CC
U2
LTC1599
R
FB
R
FB
R
OFS
R
OFS
5V
7
5
6
6
0.1
F
12
IF 2.5V REF USED CONNECT
DIRECTLY TO REF
4
4
3
20
8
R1
R
COM
2
R2
1
REF
5
6
0.1
F
R
N1
7
10
7
I
OUT1
C3
33pF
+
U3
1/2 LT1112
+
U1B
1/2 LT1366
+
U1A
1/2 LT1366
16-BIT DAC
R1
R2
R
N1
15
2
24V
2
8
1
4
3
C2
100pF
Z1
6.2V
R
N1
LOOP POWER
0.1
F
C1
1000pF
I
OUT
Q2
Si9407AEX
I
OUT2F
I
OUT2S
13
MLBYTE
MLBYTE
14 TO 18,
21 TO 23
8
DATA
INPUTS
LD
LD
12
11
24
10
WR
WR
CLR
CLVL
CLR
19
9
DGND
CLVL
3
1
R
N1
= 400
8 RESISTOR ARRAY
1
16
R
N1
9
8
5
6
7
R
N1
R4
1k
R5
10
R3
1k
3
14
4
13
5
12
6
11
R6
1k
Q1
MMBT6429
HFE = 500
2
+
1/2 LT1112
LT1460-5
Figure 5. 16-Bit Current Loop Controller for Industrial Applications
15
LTC1599
A 16-Bit General Purpose Analog Output Circuit
Industrial applications often use analog signals of 0V to
5V, 0V to 10V,
5V or
10V. The topology in Figure 6 uses
an LTC1599 to produce a universal analog output, capable
of operation over all these ranges, with only software
configuration. High precision analog switches are used to
provide uncompromising stability in all ranges and matched
resistors internal to the LTC1599 are used, as well as a
configuration that minimizes the effects of channel resis-
tance in the switches. Note that in all cases the analog
switches have minimal current flowing through them. The
use of unbuffered analog switches in series with the
feedback/divider resistors would result in an error be-
cause of temperature coefficient mismatch between the
internal DAC resistors and the switch channel resistances,
as well as the channel resistance variation over the signal
range. Quad analog switch U3 (DG212B) allows configu-
ration of feedback terms and selection of the reference
voltage. Switch C allows the buffered reference voltage to
be injected into the summing node via Pin 5 (R
OFS
) for
bipolar outputs. When active, switch D places R
OFS
in
parallel with R
FB
, producing an output at full scale voltage
equal to the voltage at the REF pin of the LTC1599.
The other switches in U3 (A and B) are used to select the
10V reference produced by the LT1019, or 5V produced by
the R3 and R4 divider.
An inexpensive precision divider can be implemented
using an 8-element resistor array, paralleling four resis-
tors for R3 and four resistors for R4. Symmetry in the
interconnection of these resistors will ensure compensa-
tion for temperature gradient across the resistor array. An
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
alternative to a resistor divider is the LTC1043 switched
capacitor building block. It can be configured as a high
precision divide-by-2. Please consult the LTC1043 data
sheet for more information.
The NOR gate (U4) ensures that switches C and D are not
enabled simultaneously. This eliminates contention be-
tween the reference buffer and the output amplifier.
This topology can be modified to accept a high current
buffer following the LT1112, if higher output current levels
are required or difficult loads need be driven. Adjustment
of C
FB
's value may be required for the buffer amplifier
chosen.
Note that the analog switches must handle the full output
swing in this configuration, but there is a variety of suitable
switches on the market including the LTC201. The DG212B
as shown is a newer generation part with lower leakage,
providing a performance advantage.
The DG333A, a quad single-pole, double-throw switch,
could be used for a 2-channel version similar to this
circuit. Alternatively, a single channel can be created with
the additional switches used as switched capacitor divide-
by-2, as shown on the LTC1043 data sheet. In choosing
analog switches, keep in mind the logic levels and the
signal levels required.
Table 1. Configuration Settings for the Various Output Ranges
V
OUT
MODE
REFSEL
BIPOLAR/UNIPOLAR
GAIN
0V to 5V
1
0
0
0V to 10V
1
0
1
5V to 5V
1
1
1
10V to 10V
0
1
1
16
LTC1599
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
V
CC
U2
LTC1599
R
FB
R
FB
R
OFS
R
OFS
5V
7
5
16
4
0.1
F
6
15
14
10V
15V
5
REFSEL
6
4
3
20
8
R1
R
COM
2
R2
1
REF
5
6
0.1
F
11
R3
100k
12
10
7
I
OUT1
C
FA
33pF
+
U1A
1/4 LT1114
+
U1D
1/4 LT1114
16-BIT DAC
R1
R2
I
OUT2F
I
OUT2S
13
MLBYTE
MLBYTE
14 TO 18,
21 TO 23
8
DATA
INPUTS
LD
LD
12
11
24
10
WR
WR
CLR
CLVL
CLR
19
9
DGND
CLVL
3
1
0.1
F
0.1
F
V
OUT
1599 F06
2
8
4
15V
1
2
3
BIPOLAR/UNIPOLAR
GAIN
15V
OPTIONAL
HIGH CURRENT
BUFFER
LT1010
LT1206
LT1210
+
+
U1B
1/4 LT1114
U1C
1/4 LT1114
R3
5k
R4
5k
6
2
R1 = R2 = 5k
U3A TO U3D = 1/4 DG212B
U4A, U4B = 1/4 HC02
LT1019 PINOUT FOR SO-8 PACKAGE
LT1114 PINOUT FOR SO PACKAGE
4
U4
U4
U5
LT1019-10
3
2
1
U3A
7
6
8
U3B
14
15
16
U3D
10
11
9
U3C
Figure 6. 16-Bit General Purpose Analog Output Circuit
17
LTC1599
Figure 7. Using the 68HC11 to Control the LTC1599
Interfacing to the 68HC11
The circuit in Figure 7 is an example of using the 68HC11
to control the LTC1599. Data is sent to the DAC using two
8-bit parallel transfers from the controller's Port B. The
WR signal is generated by manipulating the logic output
on Port A's bit 3, the MLBYTE command is sent to the DAC
using Port A's bit 4, and the LD command comes from the
SS output on Port D's bit 5.
The sample listing 68HC11 assembly code in Listing A is
designed to emulate the Timing Diagram found earlier in
this data sheet. After variable declaration, the main portion
of the program retrieves the least significant byte from
memory, forces MLBYTE and WR to a logic low, and then
writes the low byte data to Port B. It then sets WR and
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
LTC1599
PORT A, BIT 3
PORT D, BIT 5
PORT A , BIT 4
PORT B
8-BIT PARALLEL
68HC11
1599 F07
WR LD MLBYTE
MLBYTE high. Next, the most significant byte is copied
from memory and WR is again asserted low. The high byte
is written to Port B and WR is returned high. The transfer
of the 16 bits is completed by cycling the LD input low and
then high using the SS output on Port D.
************************************************************
*
*
* This example program uses 8-bit parallel port B, port A and port D
*
* to transfer 16-bit parallel data to the LTC1599 16-bit current output
*
* DAC. Port B at $1004 is used for two eight bit transfers. Port A,
*
* bit 3 is used for the LTC1599's WR command and bit 4 is used for the
*
* MLBYTE command. Port D' SS output is used for the LTC1599's LD
*
* command
*
*
*
************************************************************
*
*****************************************
* 68HC11 register definitions
*
*****************************************
*
* PIOC
EQU
$1002
Parallel I/O control register
*
"STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB"
PORTA
EQU
$1000
Port A data register
*
"Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0"
PORTB
EQU
$1004
Port B data register
*
"Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0"
PORTD
EQU
$1008
Port D data register
*
" - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD "
DDRD
EQU
$1009
Port D data direction register
SPCR
EQU
$1028
SPI control register
MBYTE
EQU
$00
This memory location holds the LTC1599's bits 15 - 08
LBYTE
EQU
$01
This memory location holds the LTC1599's bits 07 - 00
*
*****************************************
* Start OUTDATA Routine
*
*****************************************
*
ORG
$C000
Program start location
INIT1
LDAA
#$2F
-,-,1,0;1,1,1,1
*
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA
PORTD
Keeps SS* a logic high when DDRD, Bit5 is set
LDAA
#$38
-,-,1,1;1,0,0,0
STAA
DDRD
SS* , SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
* DDRD's Bit5 is a 1 so that port D's SS* pin is a general output
18
LTC1599
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
GETDATA PSHX
PSHY
PSHA
LDY
#$1000
Setup index
*
*****************************************
* Retrieve DAC data from memory and
*
* send it to the LTC1599
*
*****************************************
*
LDAA
LBYTE
Retrieve the least significant byte from memory
BCLR
PORTA,Y %00010000
This sets PORTA, Bit4 output to a logic
*
low, forcing MLBYTE input to a logic low
BCLR
PORTA,Y %00001000
This forces a low on the LTC1599's WR pin
STAA
PORTB
Transfer the least significant byte to the DAC
BSET
PORTA,Y %00001000
This forces a high on the LTC1599's WR pin
BSET
PORTA,Y %00010000
This sets PORTA, Bit4 output to a logic
*
high, forcing MLBYTE to a logic high
LDAA
MBYTE
Retrieve the most significant byte from memory
BCLR
PORTA,Y %00001000
This forces a low on the LTC1599's WR pin
STAA
PORTB
Transfer the most significant byte to the DAC
BSET
PORTA,Y %00001000
This forces a high on the LTC1599's WR pin
*
*******************************************
* The next two instructions exercise
*
* the LD input, latching the data
*
* that was just loaded
*
*******************************************
*
BCLR
PORTD,Y %00100000
LD goes low
BSET
PORTD,Y %00100000
and returns high
*
*******************************************
* Data transfer routine completed
*
*******************************************
*
PULA
Restore the A register
PULY
Restore the Y register
PULX
Restore the X register
RTS
19
LTC1599
V
CC
LTC1599
R
FB
R
FB
R
OFS
R
OFS
5V
LD
LD
4
3
2
3
3
2
LTC203AC
2
6
6
1
6
4
2
UNIPOLAR/
BIPOLAR
15V
14
15
16
3
12 11
24
20
8
9
R1
R
COM
2
1
R2 REF
5
6
0.1
F
7
2
6
3
I
OUT1
15pF
V
OUT
1596 TA02
I
OUT2F
I
OUT2S
DGND
19
+
LT1001
+
LT1468
WR
14 TO 18,
21 TO 23
WR
CLR
10
CLVL
CLVL
CLR
+
LT1468
16-BIT DAC
R1
R2
8
DATA
INPUTS
LT1236A-10
TYPICAL APPLICATIO
N
U
16-Bit V
OUT
DAC Programmable Unipolar/Bipolar Configuration
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
G Package
24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
G24 SSOP 1098
0.13 0.22
(0.005 0.009)
0
8
0.55 0.95
(0.022 0.037)
5.20 5.38**
(0.205 0.212)
7.65 7.90
(0.301 0.311)
1
2 3
4
5
6 7 8
9 10 11 12
8.07 8.33*
(0.318 0.328)
21
22
18 17 16 15 14 13
19
20
23
24
1.73 1.99
(0.068 0.078)
0.05 0.21
(0.002 0.008)
0.65
(0.0256)
BSC
0.25 0.38
(0.010 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
*
**
20
LTC1599
PART NUMBER
DESCRIPTION
COMMENTS
LT1236
Precision Reference
0.05% Initial Accuracy, 5ppm Temperature Drift
LT1468
16-Bit Accurate Op Amp
90MHz Gain Bandwidth, 22V/
s Slew Rate
LTC1591/LTC1597
Parallel 14/16-Bit Current Output DACs
On-Chip 4-Quadrant Resistors
LTC1595/LTC1596
Serial 16-Bit Current Output DACs
Low Glitch,
1LSB Maximum INL, DNL
LTC1650
16-Bit Voltage Output DAC
Low Power, Deglitched, 4-Quadrant Multiplying V
OUT
DAC,
4.5V Output Swing
LTC1657
16-Bit Parallel Voltage Output DAC
Low Power, 16-Bit Monotonic Over Temperature, Multiplying Capability
LTC1658
14-Bit Rail-to-Rail Micropower DAC
Low Power Multiplying V
OUT
DAC in MSOP. Output Swings from GND to REF.
1599f LT/TP 1199 4K PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
RELATED PARTS
TYPICAL APPLICATIO
N
U
V
CC
15pF
LTC1599
R
FB
R
FB
R
OFS
R
OFS
5V
LD
4
3
6
3
2
LTC203AC
2
1
6
4
2
15V
14
15
16
3
12 11
24
20
8
9
R1
R
COM
1
REF
2
R2
5
6
0.1
F
7
6
2
3
I
OUT1
20pF
V
OUT
1596 TA03
I
OUT2F
I
OUT2S
+
LT1468
WR
14 TO 18,
21 TO 23
SIGN
BIT
CLR
+
LT1468
16-BIT DAC
R1
R2
8
DATA
INPUTS
LT1236A-10
DGND
19
LD
WR
10
CLVL
CLVL
CLR
17-Bit Sign Magnitude DAC with Bipolar Zero Error of 140
V (0.92LSB at 17 Bits) at 25
C
PACKAGE DESCRIPTIO
N
U
Dimensions in inches (millimeters) unless otherwise noted.
N24 1098
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
0.255
0.015*
(6.477
0.381)
1.265*
(32.131)
MAX
1
2
3
4
5
6
7
8
9
10
19
11
12
13
14
16
15
17
18
20
21
22
23
24
0.020
(0.508)
MIN
0.125
(3.175)
MIN
0.130
0.005
(3.302
0.127)
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.018
0.003
(0.457
0.076)
0.100
(2.54)
BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N Package
24-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
PDF 
ZIP