1608f.pm6
1
LTC1608
High Speed, 16-Bit, 500ksps
Sampling A/D Converter
with Shutdown
The LTC
1608 is a 500ksps, 16-bit sampling A/D con-
verter that draws only 270mW from
5V supplies. This
high performance device includes a high dynamic range
sample-and-hold, a precision reference and a high speed
parallel output. Two digitally selectable power shutdown
modes provide power savings for low power systems.
The LTC1608's full-scale input range is
2.5V. Outstand-
ing AC performance includes 90dB S/(N+D) and 100dB
THD at a sample rate of 500ksps.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 15MHz
bandwidth. The 68dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
The ADC has
P compatible,16-bit parallel output port.
There is no pipeline delay in conversion results. A separate
convert start input and a data ready signal (BUSY) ease
connections to FlFOs, DSPs and microprocessors.
s
A Complete, 500ksps 16-Bit ADC
s
90dB S/(N+D) and 100dB THD (Typ)
s
Power Dissipation: 270mW (Typ)
s
No Pipeline Delay
s
No Missing Codes Over Temperature
s
Nap (7mW) and Sleep (10
W) Shutdown Modes
s
Operates with Internal 15ppm/
C Reference
or External Reference
s
True Differential Inputs Reject Common Mode Noise
s
5MHz Full Power Bandwidth
s
2.5V Bipolar Input Range
s
36-Pin SSOP Package
s
Pin Compatible with the LTC1604
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
Telecommunications
s
Digital Signal Processing
s
Multiplexed Data Acquisition Systems
s
High Speed Data Acquisition
s
Spectrum Analysis
s
Imaging Systems
FREQUENCY (kHz)
0
40
20
0
150
200
1608 TA02
60
80
50
100
250
100
120
140
AMPLITUDE (dB)
f
SAMPLE
= 500kHz
f
IN
= 98.754kHz
SINAD = 86.7dB
THD = 92.6dB
LTC1608 4096 Point FFT
Circuitry in the LTC1608 is covered under US Patent #5,764,175
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2.2
F
10
F
10
F
10
22
F
4
6
DIFFERENTIAL
ANALOG INPUT
2.5V
REFCOMP
CONTROL
LOGIC
AND
TIMING
B15 TO B0
16-BIT
SAMPLING
ADC
+
10
F
5V OR
3V
P
CONTROL
LINES
D15 TO D0
OUTPUT
BUFFERS
16-BIT
PARALLEL
BUS
11 TO 26
1608 TA01
OGND
OV
DD
28
29
1
2
A
IN
+
A
IN
SHDN
CS
CONVST
RD
BUSY
33
32
31
30
27
7.5k
LTC1608
3
36
35
10
9
5V
5V
AV
DD
AV
DD
DV
DD
DGND
V
REF
8
AGND
AGND
7
AGND
5
AGND
34
5V
V
SS
10
F
2.5V
REF
10
F
1.75X
+
+
+
+
+
+
2
LTC1608
ORDER
PART NUMBER
AV
DD
= DV
DD
= OV
DD
= V
DD
(Notes 1, 2)
Supply Voltage (V
DD
) ................................................ 6V
Negative Supply Voltage (V
SS
) ............................... 6V
Total Supply Voltage (V
DD
to V
SS
) .......................... 12V
Analog Input Voltage
(Note 3) ......................... (V
SS
0.3V) to (V
DD
+ 0.3V)
V
REF
Voltage (Note 4) ................. 0.3V to (V
DD
+ 0.3V)
REFCOMP Voltage (Note 4) ......... 0.3V to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) .................... 0.3V to 10V
Digital Output Voltage .................. 0.3V to (V
DD
+ 0.3V)
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1608C .............................................. 0
C to 70
C
LTC1608I ............................................ 40
C to 85
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
LTC1608CG
LTC1608ACG
LTC1608IG
LTC1608AIG
PUT
U
I
A
A
U
LOG
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Analog Input Range (Note 2)
4.75
V
DD
5.25V, 5.25
V
SS
4.75V,
2.5
V
V
SS
(A
IN
, A
IN
+
)
AV
DD
I
IN
Analog Input Leakage Current
CS = High
q
1
A
C
IN
Analog Input Capacitance
Between Conversions
43
pF
During Conversions
5
pF
t
ACQ
Sample-and-Hold Acquisition Time
380
ns
t
AP
Sample-and-Hold Acquisition Delay Time
1.5
ns
t
jitter
Sample-and-Hold Acquisition Delay Time Jitter
5
ps
RMS
CMRR
Analog Input Common Mode Rejection Ratio
2.5V < (A
IN
= A
IN
+
) < 2.5V
68
dB
The
q
denotes specifications that apply over the full operating temperature range, otherwise
specifications are at T
A
= 25
C.
T
JMAX
= 125
C,
JA
= 95
C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE
36-LEAD PLASTIC SSOP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
AV
DD
AV
DD
V
SS
SHDN
CS
CONV
RD
OV
DD
OGND
BUSY
D0
D1
D2
D3
D4
D5
D6
D7
A
IN
+
A
IN
V
REF
REFCOMP
AGND
AGND
AGND
AGND
DV
DD
DGND
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
C
C
HARA TERISTICS
CO
U
VERTER
LTC1608
LTC1608A
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
q
15
16
16
16
Bits
Integral Linearity Error
(Note 7)
q
1
4
0.5
2
LSB
Transition Noise
(Note 8)
0.7
0.7
LSB
RMS
Offset Error
(Note 9)
q
0.05
0.125
0.05
0.125
% FSR
Offset Tempco
(Note 9)
0.5
0.5
ppm/
C
Full-Scale Error
Internal Reference
0.125
0.25
0.125
0.25
%
External Reference
0.25
0.25
%
Full-Scale Tempco
I
OUT
(Reference) = 0, Internal Reference
15
15
ppm/
C
The
q
denotes specifications that apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. With Internal Reference (Notes 5, 6), unless otherwise noted.
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
Consult factory for parts specified with wider operating temperature ranges.
3
LTC1608
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/N
Signal-to-Noise Ratio
5kHz Input Signal
90
dB
100kHz Input Signal
88
dB
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
5kHz Input Signal
90
dB
100kHz Input Signal (Note 10)
84
dB
THD
Total Harmonic Distortion
5kHz Input Signal
100
dB
Up to 5th Harmonic
100kHz Input Signal
91
dB
SFDR
Spurious Free Dynamic Range
100kHz Input Signal
94
dB
IMD
Intermodulation Distortion
f
IN1
= 29.37kHz, f
IN2
= 32.446kHz
88
dB
Full Power Bandwidth
5
MHz
Full Linear Bandwidth (S/(N + D)
84dB)
350
kHz
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
REF
Output Voltage
I
OUT
= 0
2.475
2.500
2.515
V
V
REF
Output Tempco
I
OUT
= 0
15
ppm/
C
V
REF
Line Regulation
4.75
V
DD
5.25V
0.01
LSB/V
5.25V
V
SS
4.75V
0.01
LSB/V
V
REF
Output Resistance
0
I
OUT
1mA
7.5
k
REFCOMP Output Voltage
I
OUT
= 0
4.375
V
DY
A
IC ACCURACY
U
W
T
A
= 25
C (Note 5)
I TER AL REFERE CE CHARACTERISTICS
U
U
U
T
A
= 25
C (Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
U
The
q
denotes specifications that apply over the full
operating temperature range, otherwise specifications are at T
A
= 25
C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
DD
= 5.25V
q
2.4
V
V
IL
Low Level Input Voltage
V
DD
= 4.75V
q
0.8
V
I
IN
Digital Input Current
V
IN
= 0V to V
DD
q
1 0
A
C
IN
Digital Input Capacitance
5
pF
V
OH
High Level Output Voltage
V
DD
= 4.75V, I
OUT
= 10
A
4.5
V
V
DD
= 4.75V, I
OUT
= 400
A
q
4.0
V
V
OL
Low Level Output Voltage
V
DD
= 4.75V, I
OUT
= 160
A
0.05
V
V
DD
= 4.75V, I
OUT
= 1.6mA
q
0.10
0.4
V
I
OZ
Hi-Z Output Leakage D15 to D0
V
OUT
= 0V to V
DD
, CS High
q
10
A
C
OZ
Hi-Z Output Capacitance D15 to D0
CS High (Note 11)
q
15
pF
I
SOURCE
Output Source Current
V
OUT
= 0V
1 0
mA
I
SINK
Output Sink Current
V
OUT
= V
DD
10
mA
4
LTC1608
POWER REQUIRE E TS
W
U
The
q
denotes specifications that apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
Positive Supply Voltage
(Notes 12, 13)
4.75
5.25
V
V
SS
Negative Supply Voltage
(Note 12)
4.75
5.25
V
I
DD
Positive Supply Current
CS = RD = 0V
q
22
35
mA
Nap Mode
CS = 0V, SHDN = 0V
1.5
2.4
mA
Sleep Mode
CS = 5V, SHDN = 0V
1
100
A
I
SS
Negative Supply Current
CS = RD = 0V
q
32
49
mA
Nap Mode
CS = 0V, SHDN = 0V
1
100
A
Sleep Mode
CS = 5V, SHDN = 0V
1
100
A
P
D
Power Dissipation
CS = RD = 0V
q
270
420
mW
Nap Mode
CS = 0V, SHDN = 0V
7.5
12
mW
Sleep Mode
CS = 5V, SHDN = 0V
0.01
1
mW
TI I G CHARACTERISTICS
U
W
The
q
denotes specifications that apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
SMPL(MAX)
Maximum Sampling Frequency
q
500
600
kHz
t
CONV
Conversion Time
q
1.0
1.45
1.8
s
t
ACQ
Acquisition Time
(Notes 11, 14)
q
400
ns
t
ACQ+CONV(MIN)
Throughput Time (Acquisition + Conversion)
q
1.67
2
s
t
1
CS to RD Setup Time
(Notes 11, 12, 15)
q
0
ns
t
2
CS
to CONVST
Setup Time
(Notes 11, 12)
q
10
ns
t
3
SHDN
to CS
Setup Time
(Notes 11, 12)
q
10
ns
t
4
SHDN
to CONVST
Wake-Up Time
CS = Low (Note 12)
400
ns
t
5
CONVST Low Time
(Note 12)
q
40
ns
t
6
CONVST to BUSY Delay
C
L
= 25pF
36
ns
q
80
ns
t
7
Data Ready Before BUSY
60
ns
q
32
ns
t
8
Delay Between Conversions
(Note 12)
q
200
ns
t
9
Wait Time RD
After BUSY
(Note 12)
q
5
ns
t
10
Data Access Time After RD
C
L
= 25pF
25
40
ns
q
50
ns
C
L
= 100pF (Note 11)
45
60
ns
q
75
ns
t
11
Bus Relinquish Time
30
50
ns
q
60
ns
t
12
RD Low Time
(Note 12)
q
t
10
ns
t
13
CONVST High Time
(Note 12)
q
40
ns
t
14
Aperture Delay of Sample-and-Hold
2
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
5
LTC1608
Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
is measured at 100kHz. These results are used to calculate Signal-to-Nosie
Plus Distortion (SINAD).
Note 11: Guaranteed by design, not subject to test.
Note 12: Recommended operating conditions.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best performance ensure that CONVST returns high either within 250ns
after conversion start or after BUSY rises.
Note 14: The acquisition time would go up to 400ns and the conversion
time would go up to 1.8
s. However, the throughput time (acquisition +
conversion) is guaranteed by test to be 2
s max.
Note 15: If RD
precedes CS
, the output enable will be gated by CS
.
Note 4: When these pin voltages are taken below V
SS
, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, V
SS
= 5V, f
SMPL
= 500kHz, and t
r
= t
f
= 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specification apply for a single-
ended A
IN
+
input with A
IN
grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Typical RMS noise at the code transitions.
Note 9: Bipolar offset is the offset voltage measured from 0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Integral Nonlinearity
vs Output Code
CODE
32768
32767
INL (LSB)
0
0.5
16384
16384
0
1608 G01
1.0
1.5
2.0
0.5
1.0
1.5
2.0
Differential Nonlinearity
vs Output Code
CODE
32768
32767
1.0
DNL (LSB)
0.8
0.4
0.2
0
1.0
0.4
16384
16384
0
1608 G02
0.6
0.6
0.8
0.2
S/(N + D) vs Input Frequency
and Amplitude
FREQUENCY (Hz)
100
90
80
70
60
50
40
30
20
10
0
SINAD (dB)
1608 G03
1k
10k
100k
1M
V
IN
= 0dB
V
IN
= 20dB
V
IN
= 40dB
Signal-to-Noise Ratio
vs Input Frequency
Distortion vs Input Frequency
Spurious-Free Dynamic Range
vs Input Frequency
FREQUENCY (Hz)
100
90
80
70
60
50
40
30
20
10
0
SIGNAL-TO-NOISE RATIO (dB)
1608 G04
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
1608 G05
1k
10k
100k
1M
THD
3RD
2ND
INPUT FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
SPURIOUS-FREE DYNAMIC RANGE (dB)
1608 G06
1k
10k
100k
1M
PDF 
ZIP